1 /***************************************************************************//**
2 * @file
3 * @brief Clock management unit (CMU) API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30 #ifndef EM_CMU_H
31 #define EM_CMU_H
32
33 #include "em_device.h"
34 #if defined(CMU_PRESENT)
35
36 #include <stdbool.h>
37 #include "sl_assert.h"
38 #include "em_bus.h"
39 #include "em_cmu_compat.h"
40 #include "em_gpio.h"
41 #include "sl_common.h"
42 #include "sl_enum.h"
43 #include "sli_em_cmu.h"
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 /***************************************************************************//**
49 * @addtogroup cmu
50 * @{
51 ******************************************************************************/
52
53 /** Macro to set clock sources in the clock tree. */
54 #define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel
55
56 #if defined(_SILICON_LABS_32B_SERIES_2)
57
58 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
59
60 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
61 /* Enable register bit positions, for internal use. */
62 #define CMU_EN_BIT_POS 0U
63 #define CMU_EN_BIT_MASK 0x1FU
64
65 /* Enable register ID's for internal use. */
66 #define CMU_NO_EN_REG 0
67 #define CMU_CLKEN0_EN_REG 1
68 #define CMU_CLKEN1_EN_REG 2
69 #define CMU_CRYPTOACCCLKCTRL_EN_REG 3
70 #define CMU_EN_REG_POS 5U
71 #define CMU_EN_REG_MASK 0x3U
72
73 /* Clock branch ID's internal use. */
74 #define CMU_CORE_BRANCH 0
75 #define CMU_SYSCLK_BRANCH 1
76 #define CMU_SYSTICK_BRANCH 2
77 #define CMU_HCLK_BRANCH 3
78 #define CMU_EXPCLK_BRANCH 4
79 #define CMU_PCLK_BRANCH 5
80 #define CMU_LSPCLK_BRANCH 6
81 #define CMU_TRACECLK_BRANCH 7
82 #define CMU_EM01GRPACLK_BRANCH 8
83 #if defined(_CMU_EM01GRPBCLKCTRL_MASK)
84 #define CMU_EM01GRPBCLK_BRANCH 9
85 #endif
86 #define CMU_EUART0CLK_BRANCH 10
87 #define CMU_IADCCLK_BRANCH 11
88 #define CMU_EM23GRPACLK_BRANCH 12
89 #define CMU_WDOG0CLK_BRANCH 13
90 #if defined(RTCC_PRESENT)
91 #define CMU_RTCCCLK_BRANCH 14
92 #elif defined(SYSRTC_PRESENT)
93 #define CMU_SYSRTCCLK_BRANCH 14
94 #endif
95 #define CMU_EM4GRPACLK_BRANCH 15
96 #if defined(PDM_PRESENT)
97 #define CMU_PDMREF_BRANCH 16
98 #endif
99 #define CMU_DPLLREFCLK_BRANCH 17
100 #if WDOG_COUNT > 1
101 #define CMU_WDOG1CLK_BRANCH 18
102 #endif
103 #if defined(LCD_PRESENT)
104 #define CMU_LCD_BRANCH 19
105 #endif
106 #if defined(VDAC_PRESENT)
107 #define CMU_VDAC0_BRANCH 20
108 #endif
109 #if defined(PCNT_PRESENT)
110 #define CMU_PCNT_BRANCH 21
111 #endif
112 #if defined(LESENSE_PRESENT)
113 #define CMU_LESENSEHF_BRANCH 22
114 #define CMU_LESENSE_BRANCH 23
115 #endif
116 #if defined(_CMU_EM01GRPCCLKCTRL_MASK)
117 #define CMU_EM01GRPCCLK_BRANCH 24
118 #endif
119 #if defined(VDAC_PRESENT) && (VDAC_COUNT > 1)
120 #define CMU_VDAC1_BRANCH 25
121 #endif
122 #define CMU_CLK_BRANCH_POS 7U
123 #define CMU_CLK_BRANCH_MASK 0x1FU
124 #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
125
126 #if defined(_EMU_CMD_EM01VSCALE1_MASK)
127 /* Maximum clock frequency for VSCALE voltages. */
128 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL
129 #endif
130
131 /* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API.
132 * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for
133 * Series1 parts (highest VSCALE voltage = lowest numerical value). */
134 #define VSCALE_EM01_LOW_POWER 1
135 #define VSCALE_EM01_HIGH_PERFORMANCE 0
136
137 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1)
138 #define PLFRCO_PRESENT
139 #endif
140
141 /** @endcond */
142
143 /*******************************************************************************
144 ******************************** ENUMS ************************************
145 ******************************************************************************/
146
147 /** Clock divider configuration */
148 typedef uint32_t CMU_ClkDiv_TypeDef;
149
150 /** HFRCODPLL frequency bands */
SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef,uint32_t)151 SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) {
152 cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */
153 cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */
154 cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */
155 cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */
156 cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */
157 cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */
158 cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */
159 cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */
160 cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */
161 cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */
162 cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */
163 cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */
164 cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */
165 cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */
166 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
167 cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */
168 #endif
169 cmuHFRCODPLLFreq_UserDefined = 0,
170 };
171
172 #if defined(USBPLL_PRESENT)
173 /** HFXO reference frequency */
SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef,uint32_t)174 SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) {
175 cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
176 | (24UL << _USBPLL_CTRL_DIVX_SHIFT)
177 | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */
178 cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
179 | (25UL << _USBPLL_CTRL_DIVX_SHIFT)
180 | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */
181 cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
182 | (16UL << _USBPLL_CTRL_DIVX_SHIFT)
183 | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */
184 cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT)
185 | (24UL << _USBPLL_CTRL_DIVX_SHIFT)
186 | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */
187 };
188 #endif
189
190 /** HFRCODPLL maximum frequency */
191 #define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz
192 /** HFRCODPLL minimum frequency */
193 #define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz
194
195 #if defined(HFRCOEM23_PRESENT)
196 /** HFRCOEM23 frequency bands */
SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef,uint32_t)197 SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) {
198 cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */
199 cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */
200 cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */
201 cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */
202 cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */
203 cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */
204 cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */
205 cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */
206 cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */
207 cmuHFRCOEM23Freq_UserDefined = 0,
208 };
209
210 /** HFRCOEM23 maximum frequency */
211 #define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz
212 /** HFRCOEM23 minimum frequency */
213 #define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz
214 #endif // defined(HFRCOEM23_PRESENT)
215
216 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
217 /** Clock points in CMU clock-tree. */
SL_ENUM(CMU_Clock_TypeDef)218 SL_ENUM(CMU_Clock_TypeDef) {
219 /*******************/
220 /* Clock branches */
221 /*******************/
222
223 cmuClock_SYSCLK, /**< System clock. */
224 cmuClock_HCLK, /**< Core and AHB bus interface clock. */
225 cmuClock_EXPCLK, /**< Export clock. */
226 cmuClock_PCLK, /**< Peripheral APB bus interface clock. */
227 cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */
228 cmuClock_IADCCLK, /**< IADC clock. */
229 cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */
230 cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */
231 cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */
232 cmuClock_WDOG0CLK, /**< WDOG0 clock. */
233 cmuClock_WDOG1CLK, /**< WDOG1 clock. */
234 cmuClock_DPLLREFCLK, /**< DPLL reference clock. */
235 cmuClock_TRACECLK, /**< Debug trace clock. */
236 cmuClock_RTCCCLK, /**< RTCC clock. */
237 cmuClock_HFRCOEM23,
238
239 /*********************/
240 /* Peripheral clocks */
241 /*********************/
242
243 cmuClock_CORE, /**< Cortex-M33 core clock. */
244 cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */
245 cmuClock_ACMP0, /**< ACMP0 clock. */
246 cmuClock_ACMP1, /**< ACMP1 clock. */
247 cmuClock_BURTC, /**< BURTC clock. */
248 cmuClock_GPCRC, /**< GPCRC clock. */
249 cmuClock_GPIO, /**< GPIO clock. */
250 cmuClock_I2C0, /**< I2C0 clock. */
251 cmuClock_I2C1, /**< I2C1 clock. */
252 cmuClock_IADC0, /**< IADC clock. */
253 cmuClock_LDMA, /**< LDMA clock. */
254 cmuClock_LETIMER0, /**< LETIMER clock. */
255 cmuClock_PRS, /**< PRS clock. */
256 cmuClock_RTCC, /**< RTCC clock. */
257 cmuClock_TIMER0, /**< TIMER0 clock. */
258 cmuClock_TIMER1, /**< TIMER1 clock. */
259 cmuClock_TIMER2, /**< TIMER2 clock. */
260 cmuClock_TIMER3, /**< TIMER3 clock. */
261 cmuClock_USART0, /**< USART0 clock. */
262 cmuClock_USART1, /**< USART1 clock. */
263 cmuClock_USART2, /**< USART2 clock. */
264 cmuClock_WDOG0, /**< WDOG0 clock. */
265 cmuClock_WDOG1, /**< WDOG1 clock. */
266 cmuClock_PDM /**< PDM clock. */
267 };
268 #endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
269
270 /** Clock points in CMU clock-tree. */
271 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
SL_ENUM_GENERIC(CMU_Clock_TypeDef,uint32_t)272 SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) {
273 /*******************/
274 /* Clock branches */
275 /*******************/
276
277 cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */
278 cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */
279 cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */
280 cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */
281 cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */
282 cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */
283 cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */
284 cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */
285 #if defined(PDM_PRESENT)
286 cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */
287 #endif
288 #if defined(_CMU_EM01GRPCCLKCTRL_MASK)
289 cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */
290 #endif
291 #if defined(EUART_PRESENT)
292 cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */
293 #elif defined(EUSART_PRESENT)
294 cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */
295 #endif
296 cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */
297 cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */
298 cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */
299 #if WDOG_COUNT > 1
300 cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */
301 #endif
302 #if defined(RTCC_PRESENT)
303 cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */
304 #elif defined(SYSRTC_PRESENT)
305 cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */
306 #endif
307 cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */
308 cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */
309 #if defined(CRYPTOACC_PRESENT)
310 cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS)
311 | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */
312 cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS)
313 | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */
314 #endif
315 #if defined(LCD_PRESENT)
316 cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */
317 #endif
318 #if defined(VDAC_PRESENT)
319 cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */
320 #if (VDAC_COUNT > 1)
321 cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */
322 #endif
323 #endif
324 #if defined(PCNT_PRESENT)
325 cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */
326 #endif
327 #if defined(LESENSE_PRESENT)
328 cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */
329 cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */
330 #endif
331
332 cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */
333 #if defined(PDM_PRESENT)
334 cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */
335 #endif
336 /*********************/
337 /* Peripheral clocks */
338 /*********************/
339
340 cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
341 | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */
342 cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
343 | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */
344 #if defined(RADIOAES_PRESENT)
345 cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
346 | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */
347 #endif
348 cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
349 | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */
350 cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
351 | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */
352 cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
353 | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */
354 cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
355 | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */
356 cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
357 | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */
358 #if defined(_CMU_CLKEN1_TIMER4_SHIFT)
359 cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
360 | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */
361 #elif defined(_CMU_CLKEN0_TIMER4_SHIFT)
362 cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
363 | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */
364 #endif
365 #if defined(_CMU_CLKEN1_TIMER5_SHIFT)
366 cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
367 | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS),
368 #elif defined(_CMU_CLKEN0_TIMER5_SHIFT)
369 cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
370 | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS),
371 #endif
372 #if defined(_CMU_CLKEN1_TIMER6_SHIFT)
373 cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
374 | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS),
375 #elif defined(_CMU_CLKEN0_TIMER6_SHIFT)
376 cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
377 | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS),
378 #endif
379 #if defined(_CMU_CLKEN1_TIMER7_SHIFT)
380 cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
381 | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS),
382 #elif defined(_CMU_CLKEN0_TIMER7_SHIFT)
383 cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
384 | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS),
385 #endif
386 #if defined(USART_PRESENT) && USART_COUNT > 0
387 cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
388 | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */
389 #endif
390 #if defined(USART_PRESENT) && USART_COUNT > 1
391 cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
392 | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */
393 #endif
394 #if defined(IADC_PRESENT)
395 cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
396 | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */
397 #endif
398 cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
399 | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */
400 #if defined(LETIMER_PRESENT)
401 cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
402 | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */
403 #endif
404 cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
405 | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */
406 #if WDOG_COUNT > 1
407 cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
408 | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */
409 #endif
410 #if defined(I2C_PRESENT)
411 cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
412 | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */
413 #if I2C_COUNT > 1
414 cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
415 | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */
416 #endif
417 #endif
418 cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
419 | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */
420 cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
421 | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */
422 cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
423 | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */
424 #if defined(HFRCOEM23_PRESENT)
425 cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
426 | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */
427 #endif
428 #if defined(HFXO_PRESENT)
429 cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
430 | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */
431 #endif
432 cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
433 | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */
434 cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
435 | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */
436 cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
437 | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */
438 cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
439 | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */
440 #if defined(EUART_PRESENT)
441 cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
442 | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */
443 #endif
444 #if defined(PDM_PRESENT)
445 cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
446 | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */
447 #endif
448 cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
449 | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */
450 cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
451 | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */
452 cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
453 | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */
454 cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
455 | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */
456 #if defined(RTCC_PRESENT)
457 cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
458 | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */
459 #endif
460 cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
461 | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */
462 #if defined(SYSRTC_PRESENT)
463 cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
464 | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */
465 #endif
466 #if defined(EUSART_PRESENT) && EUSART_COUNT > 0
467 cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
468 | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */
469 #endif
470 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1
471 cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
472 | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */
473 #endif
474 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2
475 cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
476 | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */
477 #endif
478 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3
479 cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
480 | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */
481 #endif
482 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4
483 cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
484 | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */
485 #endif
486 #if defined(IFADCDEBUG_PRESENT)
487 cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
488 | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */
489 #endif
490 #if defined(CRYPTOACC_PRESENT)
491 cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
492 | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */
493 #endif
494 #if defined(SEMAILBOX_PRESENT)
495 cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
496 | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */
497 #endif
498 cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
499 | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */
500 #if defined(ICACHE_PRESENT)
501 cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
502 | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */
503 #endif
504 #if defined(LESENSE_PRESENT)
505 cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS)
506 | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */
507 #endif
508 #if defined(ACMP_PRESENT)
509 cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
510 | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */
511 #if ACMP_COUNT > 1
512 cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
513 | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */
514 #endif
515 #endif
516 #if defined(VDAC_PRESENT)
517 cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
518 | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */
519 #if (VDAC_COUNT > 1)
520 cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
521 | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */
522 #endif
523 #endif
524 #if defined(PCNT_PRESENT)
525 cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
526 | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */
527 #endif
528 #if defined(DMEM_PRESENT)
529 cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
530 | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */
531 #endif
532 #if defined(KEYSCAN_PRESENT)
533 cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
534 | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */
535 #endif
536 #if defined(LCD_PRESENT)
537 cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
538 | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */
539 #endif
540 #if defined(MVP_PRESENT)
541 cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
542 | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */
543 #endif
544 cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
545 | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */
546 #if defined(USB_PRESENT)
547 cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
548 | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */
549 #endif
550 #if defined(ETAMPDET_PRESENT)
551 cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
552 | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */
553 #endif
554 #if defined(RFFPLL_PRESENT)
555 cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS)
556 | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */
557 #endif
558 };
559 #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
560
561 /** Oscillator types. */
SL_ENUM(CMU_Osc_TypeDef)562 SL_ENUM(CMU_Osc_TypeDef) {
563 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
564 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
565 cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
566 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
567 cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
568 #if defined(HFRCOEM23_PRESENT)
569 cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
570 #endif
571 cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
572 };
573
574 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
575 /** Selectable clock sources. */
SL_ENUM_GENERIC(CMU_Select_TypeDef,uint32_t)576 SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) {
577 cmuSelect_Error, /**< Usage error. */
578 cmuSelect_Disabled, /**< Clock selector disabled. */
579 cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
580 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
581 cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
582 cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
583 cmuSelect_CLKIN0, /**< External clock input. */
584 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
585 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
586 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
587 cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */
588 cmuSelect_HCLK, /**< Core and AHB bus interface clock. */
589 cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */
590 cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */
591 cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */
592 cmuSelect_EXPCLK, /**< Pin export clock. */
593 cmuSelect_PRS /**< PRS input as clock. */
594 };
595 #endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
596
597 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
598 /** Selectable clock sources. */
SL_ENUM_GENERIC(CMU_Select_TypeDef,uint32_t)599 SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) {
600 cmuSelect_Error, /**< Usage error. */
601 cmuSelect_Disabled, /**< Clock selector disabled. */
602 cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
603 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
604 cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */
605 cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
606 cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */
607 #if defined(HFRCOEM23_PRESENT)
608 cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
609 #endif
610 cmuSelect_CLKIN0, /**< External clock input. */
611 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
612 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
613 #if defined(PLFRCO_PRESENT)
614 cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */
615 #endif
616 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
617 cmuSelect_HCLK, /**< Core and AHB bus interface clock. */
618 cmuSelect_SYSCLK, /**< System clock. */
619 cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */
620 cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */
621 cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */
622 #if defined(_CMU_EM01GRPCCLKCTRL_MASK)
623 cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */
624 #endif
625 cmuSelect_EXPCLK, /**< Pin export clock. */
626 cmuSelect_PRS, /**< PRS input as clock. */
627 #if defined(PCNT_PRESENT)
628 cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */
629 #endif
630 cmuSelect_TEMPOSC, /**< Temperature oscillator. */
631 cmuSelect_PFMOSC, /**< PFM oscillator. */
632 cmuSelect_BIASOSC, /**< BIAS oscillator. */
633 #if defined(USBPLL_PRESENT)
634 cmuSelect_USBPLL0, /**< PLL clock for USB. */
635 #endif
636 #if defined(RFFPLL_PRESENT)
637 cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */
638 #endif
639 };
640 #endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
641
642 /** DPLL reference clock edge detect selector. */
SL_ENUM(CMU_DPLLEdgeSel_TypeDef)643 SL_ENUM(CMU_DPLLEdgeSel_TypeDef) {
644 cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */
645 cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */
646 };
647
648 /** DPLL lock mode selector. */
SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef,uint32_t)649 SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) {
650 cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */
651 cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */
652 };
653
654 /** LFXO oscillator modes. */
SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef,uint32_t)655 SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) {
656 cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
657 cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */
658 cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */
659 };
660
661 /** LFXO start-up timeout delay. */
SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef,uint32_t)662 SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) {
663 cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */
664 cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */
665 cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */
666 cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */
667 cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */
668 cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */
669 cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */
670 cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */
671 };
672
673 /** HFXO oscillator modes. */
SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef,uint32_t)674 SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) {
675 cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
676 cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */
677 #if defined(_HFXO_CFG_MODE_EXTCLKPKDET)
678 cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */
679 #endif
680 };
681
682 /** HFXO core bias LSB change timeout. */
SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef,uint32_t)683 SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) {
684 cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */
685 cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */
686 cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */
687 cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */
688 cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */
689 cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */
690 cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */
691 cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */
692 cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */
693 cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */
694 cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */
695 cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */
696 cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */
697 cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */
698 cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */
699 cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */
700 };
701
702 /** HFXO steady state timeout. */
SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef,uint32_t)703 SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) {
704 cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */
705 cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */
706 cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */
707 cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */
708 cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */
709 cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */
710 cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */
711 cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */
712 cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */
713 cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */
714 cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */
715 cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */
716 cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */
717 cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */
718 cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */
719 #if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US)
720 cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */
721 #endif
722 };
723
724 /** HFXO core degeneration control. */
SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef,uint32_t)725 SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) {
726 cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */
727 cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */
728 cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */
729 cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */
730 };
731
732 /** HFXO XI and XO pin fixed capacitor control. */
SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef,uint32_t)733 SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) {
734 cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */
735 cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */
736 cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */
737 cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */
738 };
739
740 /** Oscillator precision modes. */
SL_ENUM(CMU_Precision_TypeDef)741 SL_ENUM(CMU_Precision_TypeDef) {
742 cmuPrecisionDefault, /**< Default precision mode. */
743 cmuPrecisionHigh, /**< High precision mode. */
744 };
745
746 /*******************************************************************************
747 ******************************* STRUCTS ***********************************
748 ******************************************************************************/
749
750 /** LFXO initialization structure.
751 * Initialization values should be obtained from a configuration tool,
752 * application note or crystal data sheet. */
753 typedef struct {
754 uint8_t gain; /**< Startup gain. */
755 uint8_t capTune; /**< Internal capacitance tuning. */
756 CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */
757 CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */
758 bool highAmplitudeEn; /**< High amplitude enable. */
759 bool agcEn; /**< AGC enable. */
760 bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */
761 bool failDetEn; /**< Oscillator failure detection enable. */
762 bool disOnDemand; /**< Disable on-demand requests. */
763 bool forceEn; /**< Force oscillator enable. */
764 bool regLock; /**< Lock register access. */
765 } CMU_LFXOInit_TypeDef;
766
767 /** Default LFXO initialization values for XTAL mode. */
768 #define CMU_LFXOINIT_DEFAULT \
769 { \
770 1, \
771 38, \
772 cmuLfxoStartupDelay_4KCycles, \
773 cmuLfxoOscMode_Crystal, \
774 false, /* highAmplitudeEn */ \
775 true, /* agcEn */ \
776 false, /* failDetEM4WUEn */ \
777 false, /* failDetEn */ \
778 false, /* DisOndemand */ \
779 false, /* ForceEn */ \
780 false /* Lock registers */ \
781 }
782
783 /** Default LFXO initialization values for external clock mode. */
784 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
785 { \
786 0U, \
787 0U, \
788 cmuLfxoStartupDelay_2Cycles, \
789 cmuLfxoOscMode_External, \
790 false, /* highAmplitudeEn */ \
791 false, /* agcEn */ \
792 false, /* failDetEM4WUEn */ \
793 false, /* failDetEn */ \
794 false, /* DisOndemand */ \
795 false, /* ForceEn */ \
796 false /* Lock registers */ \
797 }
798
799 /** Default LFXO initialization values for external sine mode. */
800 #define CMU_LFXOINIT_EXTERNAL_SINE \
801 { \
802 0U, \
803 0U, \
804 cmuLfxoStartupDelay_2Cycles, \
805 cmuLfxoOscMode_AcCoupledSine, \
806 false, /* highAmplitudeEn */ \
807 false, /* agcEn */ \
808 false, /* failDetEM4WUEn */ \
809 false, /* failDetEn */ \
810 false, /* DisOndemand */ \
811 false, /* ForceEn */ \
812 false /* Lock registers */ \
813 }
814
815 /** HFXO initialization structure.
816 * Initialization values should be obtained from a configuration tool,
817 * application note or crystal data sheet. */
818 typedef struct {
819 CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */
820 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */
821 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */
822 uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */
823 uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */
824 uint8_t coreBiasStartup; /**< Core bias startup current. */
825 uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */
826 CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */
827 CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */
828 uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */
829 uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */
830 uint8_t coreBiasAna; /**< Core bias current. */
831 bool enXiDcBiasAna; /**< Enable XI internal DC bias. */
832 CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */
833 bool forceXo2GndAna; /**< Force XO pin to ground. */
834 bool forceXi2GndAna; /**< Force XI pin to ground. */
835 bool disOnDemand; /**< Disable on-demand requests. */
836 bool forceEn; /**< Force oscillator enable. */
837 #if defined(HFXO_CTRL_EM23ONDEMAND)
838 bool em23OnDemand; /**< Enable deep sleep. */
839 #endif
840 bool regLock; /**< Lock register access. */
841 } CMU_HFXOInit_TypeDef;
842
843 #if defined(HFXO_CTRL_EM23ONDEMAND)
844
845 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \
846 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)
847 // See [PM-2871] for details.
848 /** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */
849 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo
850 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
851 && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
852 && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20)
853 // See [PM-5131] for details.
854 /**
855 * Default configuration of fixed tuning capacitance on XO for EFR32XG24
856 * when high power PA is present and output dBm equal 20 dBm.
857 */
858 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo
859 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
860 // See [PM-5638] for details.
861 /**
862 * Default configuration of fixed tuning capacitance on XO for EFR32XG25
863 */
864 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo
865 #else
866 /**
867 * Default configuration of fixed tuning capacitance on XO and XI.
868 */
869 #define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both
870 #endif
871
872 /** Default HFXO initialization values for XTAL mode. */
873 #define CMU_HFXOINIT_DEFAULT \
874 { \
875 cmuHfxoCbLsbTimeout_416us, \
876 cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
877 cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
878 0U, /* ctuneXoStartup */ \
879 0U, /* ctuneXiStartup */ \
880 32U, /* coreBiasStartup */ \
881 32U, /* imCoreBiasStartup */ \
882 cmuHfxoCoreDegen_None, \
883 CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \
884 _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
885 _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
886 60U, /* coreBiasAna */ \
887 false, /* enXiDcBiasAna */ \
888 cmuHfxoOscMode_Crystal, \
889 false, /* forceXo2GndAna */ \
890 false, /* forceXi2GndAna */ \
891 false, /* DisOndemand */ \
892 false, /* ForceEn */ \
893 false, /* em23OnDemand */ \
894 false /* Lock registers */ \
895 }
896
897 /** Default HFXO initialization values for external sine mode. */
898 #define CMU_HFXOINIT_EXTERNAL_SINE \
899 { \
900 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
901 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
902 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
903 0U, /* ctuneXoStartup */ \
904 0U, /* ctuneXiStartup */ \
905 0U, /* coreBiasStartup */ \
906 0U, /* imCoreBiasStartup */ \
907 cmuHfxoCoreDegen_None, \
908 cmuHfxoCtuneFixCap_None, \
909 0U, /* ctuneXoAna */ \
910 0U, /* ctuneXiAna */ \
911 0U, /* coreBiasAna */ \
912 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
913 cmuHfxoOscMode_ExternalSine, \
914 false, /* forceXo2GndAna */ \
915 false, /* forceXi2GndAna (Never enable in sine mode) */ \
916 false, /* DisOndemand */ \
917 false, /* ForceEn */ \
918 false, /* em23OnDemand */ \
919 false /* Lock registers */ \
920 }
921
922 /** Default HFXO initialization values for external sine mode with peak detector. */
923 #define CMU_HFXOINIT_EXTERNAL_SINEPKDET \
924 { \
925 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
926 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
927 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
928 0U, /* ctuneXoStartup */ \
929 0U, /* ctuneXiStartup */ \
930 0U, /* coreBiasStartup */ \
931 0U, /* imCoreBiasStartup */ \
932 cmuHfxoCoreDegen_None, \
933 cmuHfxoCtuneFixCap_None, \
934 0U, /* ctuneXoAna */ \
935 0U, /* ctuneXiAna */ \
936 0U, /* coreBiasAna */ \
937 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
938 cmuHfxoOscMode_ExternalSinePkDet, \
939 false, /* forceXo2GndAna */ \
940 false, /* forceXi2GndAna (Never enable in sine mode) */ \
941 false, /* DisOndemand */ \
942 false, /* ForceEn */ \
943 false, /* em23OnDemand */ \
944 false /* Lock registers */ \
945 }
946 #else
947 /** Default HFXO initialization values for XTAL mode. */
948 #define CMU_HFXOINIT_DEFAULT \
949 { \
950 cmuHfxoCbLsbTimeout_416us, \
951 cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
952 cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
953 0U, /* ctuneXoStartup */ \
954 0U, /* ctuneXiStartup */ \
955 32U, /* coreBiasStartup */ \
956 32U, /* imCoreBiasStartup */ \
957 cmuHfxoCoreDegen_None, \
958 cmuHfxoCtuneFixCap_Both, \
959 _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
960 _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
961 60U, /* coreBiasAna */ \
962 false, /* enXiDcBiasAna */ \
963 cmuHfxoOscMode_Crystal, \
964 false, /* forceXo2GndAna */ \
965 false, /* forceXi2GndAna */ \
966 false, /* DisOndemand */ \
967 false, /* ForceEn */ \
968 false /* Lock registers */ \
969 }
970
971 /** Default HFXO initialization values for external sine mode. */
972 #define CMU_HFXOINIT_EXTERNAL_SINE \
973 { \
974 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
975 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
976 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
977 0U, /* ctuneXoStartup */ \
978 0U, /* ctuneXiStartup */ \
979 0U, /* coreBiasStartup */ \
980 0U, /* imCoreBiasStartup */ \
981 cmuHfxoCoreDegen_None, \
982 cmuHfxoCtuneFixCap_None, \
983 0U, /* ctuneXoAna */ \
984 0U, /* ctuneXiAna */ \
985 0U, /* coreBiasAna */ \
986 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
987 cmuHfxoOscMode_ExternalSine, \
988 false, /* forceXo2GndAna */ \
989 false, /* forceXi2GndAna (Never enable in sine mode) */ \
990 false, /* DisOndemand */ \
991 false, /* ForceEn */ \
992 false /* Lock registers */ \
993 }
994
995 /** Default HFXO initialization values for external sine mode with peak detector. */
996 #define CMU_HFXOINIT_EXTERNAL_SINEPKDET \
997 { \
998 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
999 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
1000 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
1001 0U, /* ctuneXoStartup */ \
1002 0U, /* ctuneXiStartup */ \
1003 0U, /* coreBiasStartup */ \
1004 0U, /* imCoreBiasStartup */ \
1005 cmuHfxoCoreDegen_None, \
1006 cmuHfxoCtuneFixCap_None, \
1007 0U, /* ctuneXoAna */ \
1008 0U, /* ctuneXiAna */ \
1009 0U, /* coreBiasAna */ \
1010 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
1011 cmuHfxoOscMode_ExternalSinePkDet, \
1012 false, /* forceXo2GndAna */ \
1013 false, /* forceXi2GndAna (Never enable in sine mode) */ \
1014 false, /* DisOndemand */ \
1015 false, /* ForceEn */ \
1016 false /* Lock registers */ \
1017 }
1018 #endif
1019
1020 #if defined(_HFXO_BUFOUTCTRL_MASK)
1021
1022 /** Crystal sharing timeout start up timeout. */
SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef,uint32_t)1023 SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) {
1024 startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */
1025 startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */
1026 startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */
1027 startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */
1028 startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */
1029 startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */
1030 startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */
1031 startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */
1032 startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */
1033 startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */
1034 startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */
1035 startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */
1036 startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */
1037 startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */
1038 startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */
1039 startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */
1040 };
1041
1042 /** Crystal sharing leader initialization structure. */
1043 typedef struct {
1044 bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */
1045 CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */
1046 } CMU_BUFOUTLeaderInit_TypeDef;
1047
1048 /** Default crystal sharing master initialization values. */
1049 #define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \
1050 { \
1051 true, /* minimalStartupDelay */ \
1052 startupTimeout208Us, /* timeoutStartup */ \
1053 }
1054 #endif
1055
1056 #if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK)
1057 /** PRS status select output signal. */
SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef)1058 SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) {
1059 PRS_Status_select_0, /**< PRS status 0 output signal. */
1060 PRS_Status_select_1 /**< PRS status 1 output signal. */
1061 };
1062
1063 /** Crystal sharing follower initialization structure. */
1064 typedef struct {
1065 CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */
1066 bool em23OnDemand; /**< Enable em23 on demand. */
1067 bool regLock; /**< Lock registers. */
1068 } CMU_CrystalSharingFollowerInit_TypeDef;
1069
1070 /** Default crystal sharing follower initialization values. */
1071 #define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \
1072 { \
1073 PRS_Status_select_0, /* prsStatusSelectOutput */ \
1074 true, /* em23OnDemand */ \
1075 false /* regLock */ \
1076 }
1077 #endif
1078
1079 /** DPLL initialization structure.
1080 * Frequency will be Fref*(N+1)/(M+1). */
1081 typedef struct {
1082 uint32_t frequency; /**< PLL frequency value, max 80 MHz. */
1083 uint16_t n; /**< Factor N. 300 <= N <= 4095 */
1084 uint16_t m; /**< Factor M. M <= 4095 */
1085 CMU_Select_TypeDef refClk; /**< Reference clock selector. */
1086 CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
1087 CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
1088 bool autoRecover; /**< Enable automatic lock recovery. */
1089 bool ditherEn; /**< Enable dither functionality. */
1090 } CMU_DPLLInit_TypeDef;
1091
1092 /**
1093 * DPLL initialization values for 39,998,805 Hz using LFXO as reference
1094 * clock, M=2 and N=3661.
1095 */
1096 #define CMU_DPLL_LFXO_TO_40MHZ \
1097 { \
1098 39998805, /* Target frequency. */ \
1099 3661, /* Factor N. */ \
1100 2, /* Factor M. */ \
1101 cmuSelect_LFXO, /* Select LFXO as reference clock. */ \
1102 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1103 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1104 true, /* Enable automatic lock recovery. */ \
1105 false /* Don't enable dither function. */ \
1106 }
1107
1108 /**
1109 * DPLL initialization values for 76,800,000 Hz using HFXO as reference
1110 * clock, M = 1919, N = 3839
1111 */
1112 #define CMU_DPLL_HFXO_TO_76_8MHZ \
1113 { \
1114 76800000, /* Target frequency. */ \
1115 3839, /* Factor N. */ \
1116 1919, /* Factor M. */ \
1117 cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
1118 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1119 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1120 true, /* Enable automatic lock recovery. */ \
1121 false /* Don't enable dither function. */ \
1122 }
1123
1124 /**
1125 * DPLL initialization values for 80,000,000 Hz using HFXO as reference
1126 * clock, M = 1919, N = 3999.
1127 */
1128 #define CMU_DPLL_HFXO_TO_80MHZ \
1129 { \
1130 80000000, /* Target frequency. */ \
1131 (4000 - 1), /* Factor N. */ \
1132 (1920 - 1), /* Factor M. */ \
1133 cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
1134 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1135 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1136 true, /* Enable automatic lock recovery. */ \
1137 false /* Don't enable dither function. */ \
1138 }
1139
1140 /**
1141 * Default configurations for DPLL initialization. When using this macro
1142 * you need to modify the N and M factor and the desired frequency to match
1143 * the components placed on the board.
1144 */
1145 #define CMU_DPLLINIT_DEFAULT \
1146 { \
1147 80000000, /* Target frequency. */ \
1148 (4000 - 1), /* Factor N. */ \
1149 (1920 - 1), /* Factor M. */ \
1150 cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
1151 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
1152 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
1153 true, /* Enable automatic lock recovery. */ \
1154 false /* Don't enable dither function. */ \
1155 }
1156
1157 #if defined(USBPLL_PRESENT)
1158 /** USB PLL initialization structure. */
1159 typedef struct {
1160 CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */
1161 bool shuntRegEn; /**< Shunt regulator enable. */
1162 bool disOnDemand; /**< Disable on-demand requests. */
1163 bool forceEn; /**< Force oscillator enable. */
1164 bool regLock; /**< Enable register lock. */
1165 } CMU_USBPLL_Init_TypeDef;
1166
1167 /**
1168 * Default configurations for USB PLL initialization if the HFXO frequency is
1169 * 38 MHz.
1170 */
1171 #define CMU_USBPLL_REFFREQ_38MHZ \
1172 { \
1173 cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \
1174 false, /* Disable shunt regulator. */ \
1175 false, /* Disable PLL always on. */ \
1176 false, /* Force enable. */ \
1177 true /* Enable register lock. */ \
1178 }
1179
1180 /**
1181 * Default configurations for USB PLL initialization if the HFXO frequency is
1182 * 38.4 MHz.
1183 */
1184 #define CMU_USBPLL_REFFREQ_38_4MHZ \
1185 { \
1186 cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \
1187 false, /* Disable shunt regulator. */ \
1188 false, /* Disable PLL always on. */ \
1189 false, /* Force enable. */ \
1190 true /* Enable register lock. */ \
1191 }
1192
1193 /**
1194 * Default configurations for USB PLL initialization if the HFXO frequency is
1195 * 39 MHz.
1196 */
1197 #define CMU_USBPLL_REFFREQ_39MHZ \
1198 { \
1199 cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \
1200 false, /* Disable shunt regulator. */ \
1201 false, /* Disable PLL always on. */ \
1202 false, /* Force enable. */ \
1203 true /* Enable register lock. */ \
1204 }
1205
1206 /**
1207 * Default configurations for USB PLL initialization if the HFXO frequency is
1208 * 40 MHz.
1209 */
1210 #define CMU_USBPLL_REFFREQ_40MHZ \
1211 { \
1212 cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \
1213 false, /* Disable shunt regulator. */ \
1214 false, /* Disable PLL always on. */ \
1215 false, /* Force enable. */ \
1216 true /* Enable register lock. */ \
1217 }
1218 #endif
1219
1220 #if defined(RFFPLL_PRESENT)
1221 /**
1222 * RFF PLL initialization structure.
1223 * When using this structure you need to modify the X, Y and N factor
1224 * and the desired host target frequency to match the components placed
1225 * on the board (namely the RFFPLL reference clock).
1226 * X, Y, N values for a 39MHz HFXO:
1227 * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY
1228 * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2)
1229 */
1230 typedef struct {
1231 uint32_t frequency; /**< Host target frequency. */
1232 bool disOnDemand; /**< Disable on-demand requests. */
1233 bool forceEn; /**< Force oscillator enable. */
1234 bool regLock; /**< Enable register lock. */
1235 uint8_t dividerY; /**< Divider Y for digital. */
1236 uint8_t dividerX; /**< Divider X for Radio. */
1237 uint8_t dividerN; /**< Feedback divider N. */
1238 } CMU_RFFPLL_Init_TypeDef;
1239
1240 /** Radio frequency locked loop default initialization values. */
1241 #define CMU_RFFPLL_DEFAULT \
1242 { \
1243 100000000UL, /* Host target frequency. */ \
1244 false, /* Disable on-demand requests. */ \
1245 false, /* Force enable. */ \
1246 true, /* Enable register lock. */ \
1247 _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \
1248 _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \
1249 _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \
1250 }
1251
1252 /** Radio frequency locked loop initialization values for 97.5MHz. */
1253 #define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \
1254 { \
1255 97500000UL, /* Host target frequency. */ \
1256 false, /* Disable on-demand requests. */ \
1257 false, /* Force enable. */ \
1258 true, /* Enable register lock. */ \
1259 20U, /* Divider Y for digital. */ \
1260 6U, /* Divider X for Radio. */ \
1261 100U /* Feedback divider N. */ \
1262 }
1263 #endif
1264
1265 /*******************************************************************************
1266 ***************************** PROTOTYPES **********************************
1267 ******************************************************************************/
1268 uint32_t CMU_Calibrate(uint32_t cycles,
1269 CMU_Select_TypeDef reference);
1270 void CMU_CalibrateConfig(uint32_t downCycles,
1271 CMU_Select_TypeDef downSel,
1272 CMU_Select_TypeDef upSel);
1273 uint32_t CMU_CalibrateCountGet(void);
1274 void CMU_ClkOutPinConfig(uint32_t clkno,
1275 CMU_Select_TypeDef sel,
1276 CMU_ClkDiv_TypeDef clkdiv,
1277 GPIO_Port_TypeDef port,
1278 unsigned int pin);
1279 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
1280 void CMU_ClockDivSet(CMU_Clock_TypeDef clock,
1281 CMU_ClkDiv_TypeDef div);
1282 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
1283 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
1284 #endif
1285 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
1286 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
1287 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock,
1288 CMU_Select_TypeDef ref);
1289 uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock);
1290 CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void);
1291 void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq);
1292 bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init);
1293 #if defined(USBPLL_PRESENT)
1294 void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit);
1295 __STATIC_INLINE void CMU_WaitUSBPLLLock(void);
1296 #endif
1297 #if defined(RFFPLL_PRESENT)
1298 void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit);
1299 __STATIC_INLINE void CMU_WaitRFFPLLLock(void);
1300 #endif
1301 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
1302 #if defined(HFXO0_BUFOUT)
1303 void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit,
1304 GPIO_Port_TypeDef port,
1305 unsigned int pin);
1306 #endif
1307 #if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK)
1308 void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput,
1309 unsigned int prsAsyncCh,
1310 GPIO_Port_TypeDef port,
1311 unsigned int pin);
1312 #endif
1313 void CMU_HFXOCTuneSet(uint32_t ctune);
1314 uint32_t CMU_HFXOCTuneGet(void);
1315 void CMU_HFXOCTuneDeltaSet(int32_t delta);
1316 int32_t CMU_HFXOCTuneDeltaGet(void);
1317 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
1318 void CMU_LFXOPrecisionSet(uint16_t precision);
1319 uint16_t CMU_LFXOPrecisionGet(void);
1320 #if defined(PLFRCO_PRESENT)
1321 void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision);
1322 #endif
1323 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
1324 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc,
1325 uint32_t val);
1326 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
1327 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
1328
1329 #if defined(HFRCOEM23_PRESENT)
1330 CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void);
1331 void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq);
1332 #endif
1333
1334 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
1335 /***************************************************************************//**
1336 * @brief
1337 * Enable/disable a clock.
1338 *
1339 * @note
1340 * This is a dummy function to solve backward compatibility issues.
1341 *
1342 * @param[in] clock
1343 * The clock to enable/disable.
1344 *
1345 * @param[in] enable
1346 * @li true - enable specified clock.
1347 * @li false - disable specified clock.
1348 ******************************************************************************/
CMU_ClockEnable(CMU_Clock_TypeDef clock,bool enable)1349 __STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
1350 {
1351 (void)clock;
1352 (void)enable;
1353 }
1354 #endif
1355
1356 /***************************************************************************//**
1357 * @brief
1358 * Configure continuous calibration mode.
1359 * @param[in] enable
1360 * If true, enables continuous calibration, if false disables continuous
1361 * calibration.
1362 ******************************************************************************/
CMU_CalibrateCont(bool enable)1363 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
1364 {
1365 BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable);
1366 }
1367
1368 /***************************************************************************//**
1369 * @brief
1370 * Start calibration.
1371 * @note
1372 * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly
1373 * @ref CMU_CalibrateCont().
1374 ******************************************************************************/
CMU_CalibrateStart(void)1375 __STATIC_INLINE void CMU_CalibrateStart(void)
1376 {
1377 CMU->CALCMD = CMU_CALCMD_CALSTART;
1378 }
1379
1380 /***************************************************************************//**
1381 * @brief
1382 * Stop calibration counters.
1383 ******************************************************************************/
CMU_CalibrateStop(void)1384 __STATIC_INLINE void CMU_CalibrateStop(void)
1385 {
1386 CMU->CALCMD = CMU_CALCMD_CALSTOP;
1387 }
1388
1389 /***************************************************************************//**
1390 * @brief
1391 * Unlock the DPLL.
1392 * @note
1393 * The HFRCODPLL oscillator is not turned off.
1394 ******************************************************************************/
CMU_DPLLUnlock(void)1395 __STATIC_INLINE void CMU_DPLLUnlock(void)
1396 {
1397 DPLL0->EN_CLR = DPLL_EN_EN;
1398 #if defined(DPLL_EN_DISABLING)
1399 while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) {
1400 }
1401 #endif
1402 }
1403
1404 /***************************************************************************//**
1405 * @brief
1406 * Clear one or more pending CMU interrupt flags.
1407 *
1408 * @param[in] flags
1409 * CMU interrupt sources to clear.
1410 ******************************************************************************/
CMU_IntClear(uint32_t flags)1411 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
1412 {
1413 CMU->IF_CLR = flags;
1414 }
1415
1416 /***************************************************************************//**
1417 * @brief
1418 * Disable one or more CMU interrupt sources.
1419 *
1420 * @param[in] flags
1421 * CMU interrupt sources to disable.
1422 ******************************************************************************/
CMU_IntDisable(uint32_t flags)1423 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
1424 {
1425 CMU->IEN_CLR = flags;
1426 }
1427
1428 /***************************************************************************//**
1429 * @brief
1430 * Enable one or more CMU interrupt sources.
1431 *
1432 * @note
1433 * Depending on the use, a pending interrupt may already be set prior to
1434 * enabling the interrupt. Consider using @ref CMU_IntClear() prior to
1435 * enabling if such a pending interrupt should be ignored.
1436 *
1437 * @param[in] flags
1438 * CMU interrupt sources to enable.
1439 ******************************************************************************/
CMU_IntEnable(uint32_t flags)1440 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
1441 {
1442 CMU->IEN_SET = flags;
1443 }
1444
1445 /***************************************************************************//**
1446 * @brief
1447 * Get pending CMU interrupt sources.
1448 *
1449 * @return
1450 * CMU interrupt sources pending.
1451 ******************************************************************************/
CMU_IntGet(void)1452 __STATIC_INLINE uint32_t CMU_IntGet(void)
1453 {
1454 return CMU->IF;
1455 }
1456
1457 /***************************************************************************//**
1458 * @brief
1459 * Get enabled and pending CMU interrupt flags.
1460 *
1461 * @details
1462 * Useful for handling more interrupt sources in the same interrupt handler.
1463 *
1464 * @note
1465 * The event bits are not cleared by the use of this function.
1466 *
1467 * @return
1468 * Pending and enabled CMU interrupt sources.
1469 * The return value is the bitwise AND of
1470 * - the enabled interrupt sources in CMU_IEN and
1471 * - the pending interrupt flags CMU_IF
1472 ******************************************************************************/
CMU_IntGetEnabled(void)1473 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
1474 {
1475 uint32_t ien;
1476
1477 ien = CMU->IEN;
1478 return CMU->IF & ien;
1479 }
1480
1481 /**************************************************************************//**
1482 * @brief
1483 * Set one or more pending CMU interrupt sources.
1484 *
1485 * @param[in] flags
1486 * CMU interrupt sources to set to pending.
1487 *****************************************************************************/
CMU_IntSet(uint32_t flags)1488 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
1489 {
1490 CMU->IF_SET = flags;
1491 }
1492
1493 /***************************************************************************//**
1494 * @brief
1495 * Lock CMU register access in order to protect registers contents against
1496 * unintended modification.
1497 *
1498 * @details
1499 * See the reference manual for CMU registers that will be
1500 * locked.
1501 *
1502 * @note
1503 * If locking the CMU registers, they must be unlocked prior to using any
1504 * CMU API functions modifying CMU registers protected by the lock.
1505 ******************************************************************************/
CMU_Lock(void)1506 __STATIC_INLINE void CMU_Lock(void)
1507 {
1508 CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK;
1509 }
1510
1511 /***************************************************************************//**
1512 * @brief
1513 * Enable/disable oscillator.
1514 *
1515 * @note
1516 * This is a dummy function to solve backward compatibility issues.
1517 *
1518 * @param[in] osc
1519 * The oscillator to enable/disable.
1520 *
1521 * @param[in] enable
1522 * @li true - enable specified oscillator.
1523 * @li false - disable specified oscillator.
1524 *
1525 * @param[in] wait
1526 * Only used if @p enable is true.
1527 * @li true - wait for oscillator start-up time to timeout before returning.
1528 * @li false - do not wait for oscillator start-up time to timeout before
1529 * returning.
1530 ******************************************************************************/
CMU_OscillatorEnable(CMU_Osc_TypeDef osc,bool enable,bool wait)1531 __STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc,
1532 bool enable,
1533 bool wait)
1534 {
1535 (void)osc;
1536 (void)enable;
1537 (void)wait;
1538 }
1539
1540 /***************************************************************************//**
1541 * @brief
1542 * Unlock CMU register access so that writing to registers is possible.
1543 ******************************************************************************/
CMU_Unlock(void)1544 __STATIC_INLINE void CMU_Unlock(void)
1545 {
1546 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
1547 }
1548
1549 /***************************************************************************//**
1550 * @brief
1551 * Lock WDOG register access in order to protect registers contents against
1552 * unintended modification.
1553 *
1554 * @note
1555 * If locking the WDOG registers, they must be unlocked prior to using any
1556 * emlib API functions modifying registers protected by the lock.
1557 ******************************************************************************/
CMU_WdogLock(void)1558 __STATIC_INLINE void CMU_WdogLock(void)
1559 {
1560 CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK;
1561 }
1562
1563 /***************************************************************************//**
1564 * @brief
1565 * Unlock WDOG register access so that writing to registers is possible.
1566 ******************************************************************************/
CMU_WdogUnlock(void)1567 __STATIC_INLINE void CMU_WdogUnlock(void)
1568 {
1569 CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK;
1570 }
1571
1572 #if defined(USBPLL_PRESENT)
1573 /***************************************************************************//**
1574 * @brief
1575 * Wait for USB PLL lock and ready.
1576 ******************************************************************************/
CMU_WaitUSBPLLLock()1577 __STATIC_INLINE void CMU_WaitUSBPLLLock()
1578 {
1579 while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK))
1580 != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) {
1581 /* Wait for USB PLL lock and ready */
1582 }
1583 }
1584 #endif
1585
1586 #if defined(RFFPLL_PRESENT)
1587 /***************************************************************************//**
1588 * @brief
1589 * Wait for RFF PLL lock and ready.
1590 ******************************************************************************/
CMU_WaitRFFPLLLock()1591 __STATIC_INLINE void CMU_WaitRFFPLLLock()
1592 {
1593 while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY))
1594 != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) {
1595 /* Wait for RFF PLL lock and ready. */
1596 }
1597 }
1598 #endif
1599
1600 #else // defined(_SILICON_LABS_32B_SERIES_2)
1601
1602 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
1603
1604 /* Select register IDs for internal use. */
1605 #define CMU_NOSEL_REG 0
1606 #define CMU_HFCLKSEL_REG 1
1607 #define CMU_LFACLKSEL_REG 2
1608 #define CMU_LFBCLKSEL_REG 3
1609 #define CMU_LFCCLKSEL_REG 4
1610 #define CMU_LFECLKSEL_REG 5
1611 #define CMU_DBGCLKSEL_REG 6
1612 #define CMU_USBCCLKSEL_REG 7
1613 #define CMU_ADC0ASYNCSEL_REG 8
1614 #define CMU_ADC1ASYNCSEL_REG 9
1615 #define CMU_SDIOREFSEL_REG 10
1616 #define CMU_QSPI0REFSEL_REG 11
1617 #define CMU_USBRCLKSEL_REG 12
1618 #define CMU_PDMREFSEL_REG 13
1619
1620 #define CMU_SEL_REG_POS 0U
1621 #define CMU_SEL_REG_MASK 0xfU
1622
1623 /* Divisor/prescaler register IDs for internal use. */
1624 #define CMU_NODIV_REG 0
1625 #define CMU_NOPRESC_REG 0
1626 #define CMU_HFPRESC_REG 1
1627 #define CMU_HFCLKDIV_REG 1
1628 #define CMU_HFEXPPRESC_REG 2
1629 #define CMU_HFCLKLEPRESC_REG 3
1630 #define CMU_HFPERPRESC_REG 4
1631 #define CMU_HFPERCLKDIV_REG 4
1632 #define CMU_HFPERPRESCB_REG 5
1633 #define CMU_HFPERPRESCC_REG 6
1634 #define CMU_HFCOREPRESC_REG 7
1635 #define CMU_HFCORECLKDIV_REG 7
1636 #define CMU_LFAPRESC0_REG 8
1637 #define CMU_LFBPRESC0_REG 9
1638 #define CMU_LFEPRESC0_REG 10
1639 #define CMU_ADCASYNCDIV_REG 11
1640 #define CMU_HFBUSPRESC_REG 12
1641 #define CMU_HFCORECLKLEDIV_REG 13
1642
1643 #define CMU_PRESC_REG_POS 4U
1644 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
1645 #define CMU_PRESC_REG_MASK 0xfU
1646 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
1647
1648 /* Enable register IDs for internal use. */
1649 #define CMU_NO_EN_REG 0
1650 #define CMU_CTRL_EN_REG 1
1651 #define CMU_HFPERCLKDIV_EN_REG 1
1652 #define CMU_HFPERCLKEN0_EN_REG 2
1653 #define CMU_HFCORECLKEN0_EN_REG 3
1654 #define CMU_PDMREF_EN_REG 4
1655 #define CMU_HFBUSCLKEN0_EN_REG 5
1656 #define CMU_LFACLKEN0_EN_REG 6
1657 #define CMU_LFBCLKEN0_EN_REG 7
1658 #define CMU_LFCCLKEN0_EN_REG 8
1659 #define CMU_LFECLKEN0_EN_REG 9
1660 #define CMU_PCNT_EN_REG 10
1661 #define CMU_SDIOREF_EN_REG 11
1662 #define CMU_QSPI0REF_EN_REG 12
1663 #define CMU_QSPI1REF_EN_REG 13
1664 #define CMU_HFPERCLKEN1_EN_REG 14
1665 #define CMU_USBRCLK_EN_REG 15
1666
1667 #define CMU_EN_REG_POS 8U
1668 #define CMU_EN_REG_MASK 0xfU
1669
1670 /* Enable register bit positions, for internal use. */
1671 #define CMU_EN_BIT_POS 12U
1672 #define CMU_EN_BIT_MASK 0x1fU
1673
1674 /* Clock branch bitfield positions, for internal use. */
1675 #define CMU_HF_CLK_BRANCH 0
1676 #define CMU_HFCORE_CLK_BRANCH 1
1677 #define CMU_HFPER_CLK_BRANCH 2
1678 #define CMU_HFPERB_CLK_BRANCH 3
1679 #define CMU_HFPERC_CLK_BRANCH 4
1680 #define CMU_HFBUS_CLK_BRANCH 5
1681 #define CMU_HFEXP_CLK_BRANCH 6
1682 #define CMU_DBG_CLK_BRANCH 7
1683 #define CMU_AUX_CLK_BRANCH 8
1684 #define CMU_RTC_CLK_BRANCH 9
1685 #define CMU_RTCC_CLK_BRANCH 10
1686 #define CMU_LETIMER0_CLK_BRANCH 11
1687 #define CMU_LETIMER1_CLK_BRANCH 12
1688 #define CMU_LEUART0_CLK_BRANCH 13
1689 #define CMU_LEUART1_CLK_BRANCH 14
1690 #define CMU_LFA_CLK_BRANCH 15
1691 #define CMU_LFB_CLK_BRANCH 16
1692 #define CMU_LFC_CLK_BRANCH 17
1693 #define CMU_LFE_CLK_BRANCH 18
1694 #define CMU_USBC_CLK_BRANCH 19
1695 #define CMU_USBLE_CLK_BRANCH 20
1696 #define CMU_LCDPRE_CLK_BRANCH 21
1697 #define CMU_LCD_CLK_BRANCH 22
1698 #define CMU_LESENSE_CLK_BRANCH 23
1699 #define CMU_CSEN_LF_CLK_BRANCH 24
1700 #define CMU_ADC0ASYNC_CLK_BRANCH 25
1701 #define CMU_ADC1ASYNC_CLK_BRANCH 26
1702 #define CMU_SDIOREF_CLK_BRANCH 27
1703 #define CMU_QSPI0REF_CLK_BRANCH 28
1704 #define CMU_USBR_CLK_BRANCH 29
1705 #define CMU_PDMREF_CLK_BRANCH 30
1706 #define CMU_HFLE_CLK_BRANCH 31
1707
1708 #define CMU_CLK_BRANCH_POS 17U
1709 #define CMU_CLK_BRANCH_MASK 0x1fU
1710
1711 #if defined(_EMU_CMD_EM01VSCALE0_MASK)
1712 /* Maximum clock frequency for VSCALE voltages. */
1713 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL
1714 #endif
1715
1716 /* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API.
1717 * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for
1718 * Series1 parts (highest VSCALE voltage = lowest numerical value). */
1719 #define VSCALE_EM01_LOW_POWER 2
1720 #define VSCALE_EM01_HIGH_PERFORMANCE 0
1721
1722 #if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK)
1723 #define USBC_CLOCK_PRESENT
1724 #endif
1725 #if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK)
1726 #define USBR_CLOCK_PRESENT
1727 #endif
1728 #if defined(CMU_OSCENCMD_PLFRCOEN)
1729 #define PLFRCO_PRESENT
1730 #endif
1731
1732 /** @endcond */
1733
1734 /*******************************************************************************
1735 ******************************** ENUMS ************************************
1736 ******************************************************************************/
1737
1738 /** Clock divisors. These values are valid for prescalers. */
1739 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
1740 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
1741 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
1742 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
1743 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
1744 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
1745 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
1746 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
1747 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
1748 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
1749 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
1750 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
1751 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
1752 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
1753 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
1754 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
1755
1756 /** Clock divider configuration */
1757 typedef uint32_t CMU_ClkDiv_TypeDef;
1758
1759 #if defined(_SILICON_LABS_32B_SERIES_1)
1760 /** Clockprescaler configuration */
1761 typedef uint32_t CMU_ClkPresc_TypeDef;
1762 #endif
1763
1764 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
1765 /** High-frequency system RCO bands */
1766 SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) {
1767 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */
1768 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */
1769 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */
1770 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */
1771 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */
1772 #if defined(CMU_HFRCOCTRL_BAND_28MHZ)
1773 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */
1774 #endif
1775 };
1776 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
1777
1778 #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
1779 /** AUX high-frequency RCO bands */
1780 SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) {
1781 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */
1782 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */
1783 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */
1784 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */
1785 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */
1786 #if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ)
1787 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */
1788 #endif
1789 };
1790 #endif
1791
1792 #if defined(_CMU_USHFRCOCONF_BAND_MASK)
1793 /** Universal serial high-frequency RC bands */
1794 SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) {
1795 /** 24 MHz RC band. */
1796 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
1797 /** 48 MHz RC band. */
1798 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
1799 };
1800 #endif
1801
1802 #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
1803 /** High-USHFRCO bands */
1804 SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) {
1805 cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */
1806 cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */
1807 cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */
1808 cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */
1809 cmuUSHFRCOFreq_UserDefined = 0,
1810 };
1811 /** USHFRCO minimum frequency */
1812 #define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz
1813 /** USHFRCO maximum frequency */
1814 #define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz
1815 #endif
1816
1817 #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
1818 /** High-frequency system RCO bands */
1819 SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) {
1820 cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */
1821 cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */
1822 cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */
1823 cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */
1824 cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */
1825 cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */
1826 cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */
1827 cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */
1828 cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */
1829 cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */
1830 #if defined(_DEVINFO_HFRCOCAL13_MASK)
1831 cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */
1832 #endif
1833 #if defined(_DEVINFO_HFRCOCAL14_MASK)
1834 cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */
1835 #endif
1836 #if defined(_DEVINFO_HFRCOCAL15_MASK)
1837 cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */
1838 #endif
1839 #if defined(_DEVINFO_HFRCOCAL16_MASK)
1840 cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */
1841 #endif
1842 cmuHFRCOFreq_UserDefined = 0,
1843 };
1844
1845 /** HFRCO minimum frequency. */
1846 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
1847 #if defined(_DEVINFO_HFRCOCAL16_MASK)
1848 /** HFRCO maximum frequency. */
1849 #define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
1850 #elif defined(_DEVINFO_HFRCOCAL15_MASK)
1851 /** HFRCO maximum frequency. */
1852 #define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz
1853 #elif defined(_DEVINFO_HFRCOCAL14_MASK)
1854 /** HFRCO maximum frequency. */
1855 #define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz
1856 #elif defined(_DEVINFO_HFRCOCAL13_MASK)
1857 /** HFRCO maximum frequency. */
1858 #define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz
1859 #else
1860 /** HFRCO maximum frequency. */
1861 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
1862 #endif
1863 #endif
1864
1865 #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
1866 /** AUX high-frequency RCO bands */
1867 SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) {
1868 cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */
1869 cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */
1870 cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */
1871 cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */
1872 cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */
1873 cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */
1874 cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */
1875 cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */
1876 cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */
1877 cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */
1878 #if defined(_DEVINFO_AUXHFRCOCAL13_MASK)
1879 cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */
1880 #endif
1881 #if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
1882 cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */
1883 #endif
1884 cmuAUXHFRCOFreq_UserDefined = 0,
1885 };
1886 /** AUXHFRCO minimum frequency. */
1887 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
1888 #if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
1889 /** AUXHFRCO maximum frequency. */
1890 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz
1891 #elif defined(_DEVINFO_AUXHFRCOCAL13_MASK)
1892 /** AUXHFRCO maximum frequency. */
1893 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz
1894 #else
1895 /** AUXHFRCO maximum frequency. */
1896 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
1897 #endif
1898 #endif
1899
1900 /** Clock points in CMU. See CMU overview in the reference manual. */
1901 SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) {
1902 /*******************/
1903 /* HF clock branch */
1904 /*******************/
1905
1906 /** High-frequency clock */
1907 #if defined(_CMU_CTRL_HFCLKDIV_MASK) \
1908 || defined(_CMU_HFPRESC_MASK)
1909 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
1910 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
1911 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1912 | (0 << CMU_EN_BIT_POS)
1913 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1914 #else
1915 cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
1916 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
1917 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1918 | (0 << CMU_EN_BIT_POS)
1919 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1920 #endif
1921
1922 /** Debug clock */
1923 cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
1924 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
1925 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1926 | (0 << CMU_EN_BIT_POS)
1927 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1928
1929 /** AUX clock */
1930 cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
1931 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1932 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1933 | (0 << CMU_EN_BIT_POS)
1934 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1935
1936 #if defined(_CMU_HFEXPPRESC_MASK)
1937 /**********************/
1938 /* HF export sub-branch */
1939 /**********************/
1940
1941 /** Export clock */
1942 cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
1943 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1944 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1945 | (0 << CMU_EN_BIT_POS)
1946 | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1947 #endif
1948
1949 #if defined(_CMU_HFBUSCLKEN0_MASK)
1950 /**********************************/
1951 /* HF bus clock sub-branch */
1952 /**********************************/
1953
1954 /** High-frequency bus clock */
1955 #if defined(_CMU_HFBUSPRESC_MASK)
1956 cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS)
1957 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1958 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1959 | (0 << CMU_EN_BIT_POS)
1960 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1961 #else
1962 cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
1963 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1964 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
1965 | (0 << CMU_EN_BIT_POS)
1966 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1967 #endif
1968
1969 #if defined(CMU_HFBUSCLKEN0_CRYPTO)
1970 /** Cryptography accelerator clock */
1971 cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
1972 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1973 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
1974 | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
1975 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1976 #endif
1977
1978 #if defined(CMU_HFBUSCLKEN0_CRYPTO0)
1979 /** Cryptography accelerator 0 clock */
1980 cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
1981 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1982 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
1983 | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS)
1984 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1985 #endif
1986
1987 #if defined(CMU_HFBUSCLKEN0_CRYPTO1)
1988 /** Cryptography accelerator 1 clock */
1989 cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
1990 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
1991 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
1992 | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS)
1993 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
1994 #endif
1995
1996 #if defined(CMU_HFBUSCLKEN0_LDMA)
1997 /** Direct-memory access controller clock */
1998 cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
1999 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2000 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2001 | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
2002 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2003 #endif
2004
2005 #if defined(CMU_HFBUSCLKEN0_QSPI0)
2006 /** Quad SPI clock */
2007 cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2008 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2009 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2010 | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS)
2011 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2012 #endif
2013
2014 #if defined(CMU_HFBUSCLKEN0_GPCRC)
2015 /** General-purpose cyclic redundancy checksum clock */
2016 cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2017 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2018 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2019 | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
2020 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2021 #endif
2022
2023 #if defined(CMU_HFBUSCLKEN0_GPIO)
2024 /** General-purpose input/output clock */
2025 cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2026 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2027 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2028 | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
2029 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2030 #endif
2031
2032 /** Low-energy clock divided down from HFCLK */
2033 cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS)
2034 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2035 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2036 | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
2037 | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2038
2039 #if defined(CMU_HFBUSCLKEN0_PRS)
2040 /** Peripheral reflex system clock */
2041 cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2042 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2043 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2044 | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
2045 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2046 #endif
2047 #endif
2048
2049 /**********************************/
2050 /* HF peripheral clock sub-branch */
2051 /**********************************/
2052
2053 /** High-frequency peripheral clock */
2054 #if defined(_CMU_HFPRESC_MASK)
2055 cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
2056 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2057 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
2058 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2059 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2060 #else
2061 cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
2062 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2063 | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
2064 | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2065 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2066 #endif
2067
2068 #if defined(_CMU_HFPERPRESCB_MASK)
2069 /** Branch B figh-frequency peripheral clock */
2070 cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS)
2071 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2072 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
2073 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2074 | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2075 #endif
2076
2077 #if defined(_CMU_HFPERPRESCC_MASK)
2078 /** Branch C figh-frequency peripheral clock */
2079 cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS)
2080 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2081 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
2082 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
2083 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2084 #endif
2085
2086 #if defined(CMU_HFPERCLKEN0_PDM)
2087 /** PDM clock */
2088 cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2089 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2090 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2091 | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS)
2092 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2093 #endif
2094
2095 #if defined(CMU_HFPERCLKEN0_USART0)
2096 /** Universal sync/async receiver/transmitter 0 clock */
2097 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2098 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2099 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2100 | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
2101 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2102 #endif
2103
2104 #if defined(CMU_HFPERCLKEN0_USARTRF0)
2105 /** Universal sync/async receiver/transmitter 0 clock */
2106 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2107 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2108 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2109 | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
2110 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2111 #endif
2112
2113 #if defined(CMU_HFPERCLKEN0_USARTRF1)
2114 /** Universal sync/async receiver/transmitter 0 clock */
2115 cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2116 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2117 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2118 | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
2119 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2120 #endif
2121
2122 #if defined(CMU_HFPERCLKEN0_USART1)
2123 /** Universal sync/async receiver/transmitter 1 clock */
2124 cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2125 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2126 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2127 | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
2128 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2129 #endif
2130
2131 #if defined(CMU_HFPERCLKEN0_USART2)
2132 /** Universal sync/async receiver/transmitter 2 clock */
2133 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2134 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2135 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2136 | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
2137 #if defined(_CMU_HFPERPRESCB_MASK)
2138 | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2139 #else
2140 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2141 #endif
2142 #endif
2143
2144 #if defined(CMU_HFPERCLKEN0_USART3)
2145 /** Universal sync/async receiver/transmitter 3 clock */
2146 cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2147 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2148 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2149 | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
2150 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2151 #endif
2152
2153 #if defined(CMU_HFPERCLKEN0_USART4)
2154 /** Universal sync/async receiver/transmitter 4 clock */
2155 cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2156 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2157 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2158 | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
2159 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2160 #endif
2161
2162 #if defined(CMU_HFPERCLKEN0_USART5)
2163 /** Universal sync/async receiver/transmitter 5 clock */
2164 cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2165 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2166 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2167 | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
2168 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2169 #endif
2170
2171 #if defined(CMU_HFPERCLKEN0_UART0)
2172 /** Universal async receiver/transmitter 0 clock */
2173 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2174 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2175 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2176 | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
2177 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2178 #elif defined(_CMU_HFPERCLKEN1_UART0_MASK)
2179 /** Universal async receiver/transmitter 0 clock */
2180 cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2181 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2182 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2183 | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS)
2184 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2185 #endif
2186
2187 #if defined(CMU_HFPERCLKEN0_UART1)
2188 /** Universal async receiver/transmitter 1 clock */
2189 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2190 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2191 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2192 | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
2193 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2194 #elif defined(_CMU_HFPERCLKEN1_UART1_MASK)
2195 /** Universal async receiver/transmitter 1 clock */
2196 cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2197 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2198 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2199 | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS)
2200 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2201 #endif
2202
2203 #if defined(CMU_HFPERCLKEN0_TIMER0)
2204 /** Timer 0 clock */
2205 cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2206 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2207 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2208 | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
2209 #if defined(_CMU_HFPERPRESCB_MASK)
2210 | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2211 #else
2212 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2213 #endif
2214 #endif
2215
2216 #if defined(CMU_HFPERCLKEN0_TIMER1)
2217 /** Timer 1 clock */
2218 cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2219 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2220 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2221 | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
2222 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2223 #endif
2224
2225 #if defined(CMU_HFPERCLKEN0_TIMER2)
2226 /** Timer 2 clock */
2227 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2228 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2229 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2230 | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
2231 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2232 #endif
2233
2234 #if defined(CMU_HFPERCLKEN0_TIMER3)
2235 /** Timer 3 clock */
2236 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2237 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2238 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2239 | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
2240 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2241 #endif
2242
2243 #if defined(CMU_HFPERCLKEN0_TIMER4)
2244 /** Timer 4 clock */
2245 cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2246 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2247 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2248 | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS)
2249 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2250 #endif
2251
2252 #if defined(CMU_HFPERCLKEN0_TIMER5)
2253 /** Timer 5 clock */
2254 cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2255 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2256 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2257 | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS)
2258 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2259 #endif
2260
2261 #if defined(CMU_HFPERCLKEN0_TIMER6)
2262 /** Timer 6 clock */
2263 cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2264 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2265 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2266 | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS)
2267 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2268 #endif
2269
2270 #if defined(CMU_HFPERCLKEN0_WTIMER0)
2271 /** Wide-timer 0 clock */
2272 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2273 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2274 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2275 | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
2276 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2277 #elif defined(CMU_HFPERCLKEN1_WTIMER0)
2278 /** Wide-timer 0 clock */
2279 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2280 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2281 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2282 | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS)
2283 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2284 #endif
2285
2286 #if defined(CMU_HFPERCLKEN0_WTIMER1)
2287 /** Wide-timer 1 clock */
2288 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2289 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2290 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2291 | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
2292 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2293 #elif defined(CMU_HFPERCLKEN1_WTIMER1)
2294 /** Wide-timer 1 clock */
2295 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2296 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2297 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2298 | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS)
2299 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2300 #endif
2301
2302 #if defined(CMU_HFPERCLKEN1_WTIMER2)
2303 /** Wide-timer 2 clock */
2304 cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2305 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2306 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2307 | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS)
2308 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2309 #endif
2310
2311 #if defined(CMU_HFPERCLKEN1_WTIMER3)
2312 /** Wide-timer 3 clock */
2313 cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2314 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2315 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2316 | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS)
2317 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2318 #endif
2319
2320 #if defined(CMU_HFPERCLKEN0_CRYOTIMER)
2321 /** CRYOtimer clock */
2322 cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2323 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2324 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2325 | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
2326 #if defined(_CMU_HFPERPRESCC_MASK)
2327 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2328 #else
2329 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2330 #endif
2331 #endif
2332
2333 #if defined(CMU_HFPERCLKEN0_ACMP0)
2334 /** Analog comparator 0 clock */
2335 cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2336 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2337 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2338 | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
2339 #if defined(_CMU_HFPERPRESCC_MASK)
2340 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2341 #else
2342 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2343 #endif
2344 #endif
2345
2346 #if defined(CMU_HFPERCLKEN0_ACMP1)
2347 /** Analog comparator 1 clock */
2348 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2349 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2350 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2351 | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
2352 #if defined(_CMU_HFPERPRESCC_MASK)
2353 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2354 #else
2355 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2356 #endif
2357 #endif
2358
2359 #if defined(CMU_HFPERCLKEN0_ACMP2)
2360 /** Analog comparator 2 clock */
2361 cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2362 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2363 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2364 | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS)
2365 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2366 #endif
2367
2368 #if defined(CMU_HFPERCLKEN0_ACMP3)
2369 /** Analog comparator 3 clock */
2370 cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2371 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2372 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2373 | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS)
2374 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2375 #endif
2376
2377 #if defined(CMU_HFPERCLKEN0_PRS)
2378 /** Peripheral-reflex system clock */
2379 cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2380 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2381 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2382 | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
2383 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2384 #endif
2385
2386 #if defined(CMU_HFPERCLKEN0_DAC0)
2387 /** Digital-to-analog converter 0 clock */
2388 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2389 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2390 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2391 | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
2392 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2393 #endif
2394
2395 #if defined(CMU_HFPERCLKEN0_VDAC0)
2396 /** Voltage digital-to-analog converter 0 clock */
2397 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2398 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2399 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2400 | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
2401 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2402 #elif defined(CMU_HFPERCLKEN1_VDAC0)
2403 /** Voltage digital-to-analog converter 0 clock */
2404 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2405 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2406 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2407 | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS)
2408 #if defined(_CMU_HFPERPRESCC_MASK)
2409 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2410 #else
2411 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2412 #endif
2413 #endif
2414
2415 #if defined(CMU_HFPERCLKEN0_IDAC0)
2416 /** Current digital-to-analog converter 0 clock */
2417 cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2418 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2419 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2420 | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
2421 #if defined(_CMU_HFPERPRESCC_MASK)
2422 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2423 #else
2424 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2425 #endif
2426 #endif
2427
2428 #if defined(CMU_HFPERCLKEN0_GPIO)
2429 /** General-purpose input/output clock */
2430 cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2431 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2432 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2433 | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
2434 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2435 #endif
2436
2437 #if defined(CMU_HFPERCLKEN0_VCMP)
2438 /** Voltage comparator clock */
2439 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2440 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2441 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2442 | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
2443 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2444 #endif
2445
2446 #if defined(CMU_HFPERCLKEN0_ADC0)
2447 /** Analog-to-digital converter 0 clock */
2448 cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2449 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2450 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2451 | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
2452 #if defined(_CMU_HFPERPRESCC_MASK)
2453 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2454 #else
2455 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2456 #endif
2457 #endif
2458
2459 #if defined(CMU_HFPERCLKEN0_ADC1)
2460 /** Analog-to-digital converter 1 clock */
2461 cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2462 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2463 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2464 | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS)
2465 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2466 #endif
2467
2468 #if defined(CMU_HFPERCLKEN0_I2C0)
2469 /** I2C 0 clock */
2470 cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2471 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2472 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2473 | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
2474 #if defined(_CMU_HFPERPRESCC_MASK)
2475 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2476 #else
2477 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2478 #endif
2479 #endif
2480
2481 #if defined(CMU_HFPERCLKEN0_I2C1)
2482 /** I2C 1 clock */
2483 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2484 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2485 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2486 | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
2487 #if defined(_CMU_HFPERPRESCC_MASK)
2488 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2489 #else
2490 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2491 #endif
2492 #endif
2493
2494 #if defined(CMU_HFPERCLKEN0_I2C2)
2495 /** I2C 2 clock */
2496 cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2497 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2498 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2499 | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
2500 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2501 #endif
2502
2503 #if defined(CMU_HFPERCLKEN0_CSEN)
2504 /** Capacitive Sense HF clock */
2505 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2506 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2507 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2508 | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
2509 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2510 #elif defined(CMU_HFPERCLKEN1_CSEN)
2511 /** Capacitive Sense HF clock */
2512 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2513 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2514 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2515 | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS)
2516 | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2517 #endif
2518
2519 #if defined(CMU_HFPERCLKEN0_TRNG0)
2520 /** True random number generator clock */
2521 cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2522 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2523 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
2524 | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
2525 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2526 #endif
2527
2528 #if defined(_CMU_HFPERCLKEN1_CAN0_MASK)
2529 /** Controller Area Network 0 clock */
2530 cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2531 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2532 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2533 | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS)
2534 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2535 #endif
2536
2537 #if defined(_CMU_HFPERCLKEN1_CAN1_MASK)
2538 /** Controller Area Network 1 clock. */
2539 cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2540 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2541 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
2542 | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS)
2543 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2544 #endif
2545
2546 /**********************/
2547 /* HF core sub-branch */
2548 /**********************/
2549
2550 /** Core clock */
2551 cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
2552 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2553 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2554 | (0 << CMU_EN_BIT_POS)
2555 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2556
2557 #if defined(CMU_HFCORECLKEN0_AES)
2558 /** Advanced encryption standard accelerator clock */
2559 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2560 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2561 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2562 | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
2563 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2564 #endif
2565
2566 #if defined(CMU_HFCORECLKEN0_DMA)
2567 /** Direct memory access controller clock */
2568 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2569 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2570 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2571 | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
2572 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2573 #endif
2574
2575 #if defined(CMU_HFCORECLKEN0_LE)
2576 /** Low-energy clock divided down from HFCORECLK */
2577 cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS)
2578 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2579 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2580 | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
2581 | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2582 #endif
2583
2584 #if defined(CMU_HFCORECLKEN0_EBI)
2585 /** External bus interface clock */
2586 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2587 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2588 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2589 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
2590 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2591 #elif defined(_CMU_HFBUSCLKEN0_EBI_MASK)
2592 /** External bus interface clock */
2593 cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2594 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2595 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2596 | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
2597 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2598 #endif
2599
2600 #if defined(_CMU_HFBUSCLKEN0_ETH_MASK)
2601 /** Ethernet clock */
2602 cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2603 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2604 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2605 | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS)
2606 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2607 #endif
2608
2609 #if defined(_CMU_HFBUSCLKEN0_SDIO_MASK)
2610 /** SDIO clock */
2611 cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2612 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2613 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2614 | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS)
2615 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2616 #endif
2617
2618 #if defined(USBC_CLOCK_PRESENT)
2619 /** USB Core clock */
2620 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2621 | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
2622 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2623 | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
2624 | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2625 #endif
2626 #if defined (USBR_CLOCK_PRESENT)
2627 /** USB Rate clock */
2628 cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2629 | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS)
2630 | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS)
2631 | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS)
2632 | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2633 #endif
2634
2635 #if defined(CMU_HFCORECLKEN0_USB)
2636 /** USB clock */
2637 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2638 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2639 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
2640 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
2641 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2642 #elif defined(CMU_HFBUSCLKEN0_USB)
2643 /** USB clock */
2644 cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2645 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2646 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
2647 | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
2648 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2649 #endif
2650
2651 /***************/
2652 /* LF A branch */
2653 /***************/
2654
2655 /** Low-frequency A clock */
2656 cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2657 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
2658 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2659 | (0 << CMU_EN_BIT_POS)
2660 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2661
2662 #if defined(CMU_LFACLKEN0_RTC)
2663 /** Real time counter clock */
2664 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2665 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2666 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2667 | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
2668 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2669 #endif
2670
2671 #if defined(CMU_LFACLKEN0_LETIMER0)
2672 /** Low-energy timer 0 clock */
2673 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2674 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2675 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2676 | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
2677 | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2678 #endif
2679
2680 #if defined(CMU_LFACLKEN0_LETIMER1)
2681 /** Low-energy timer 1 clock */
2682 cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2683 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2684 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2685 | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS)
2686 | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2687 #endif
2688
2689 #if defined(CMU_LFACLKEN0_LCD)
2690 /** Liquid crystal display, pre FDIV clock */
2691 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2692 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2693 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2694 | (0 << CMU_EN_BIT_POS)
2695 | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2696
2697 /** Liquid crystal display clock. Note that FDIV prescaler
2698 * must be set by special API. */
2699 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2700 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2701 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2702 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
2703 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2704 #endif
2705
2706 #if defined(CMU_PCNTCTRL_PCNT0CLKEN)
2707 /** Pulse counter 0 clock */
2708 cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2709 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2710 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
2711 | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
2712 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2713 #endif
2714
2715 #if defined(CMU_PCNTCTRL_PCNT1CLKEN)
2716 /** Pulse counter 1 clock */
2717 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2718 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2719 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
2720 | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
2721 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2722 #endif
2723
2724 #if defined(CMU_PCNTCTRL_PCNT2CLKEN)
2725 /** Pulse counter 2 clock */
2726 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2727 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2728 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
2729 | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
2730 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2731 #endif
2732 #if defined(CMU_LFACLKEN0_LESENSE)
2733 /** LESENSE clock */
2734 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
2735 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2736 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
2737 | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
2738 | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2739 #endif
2740
2741 /***************/
2742 /* LF B branch */
2743 /***************/
2744
2745 /** Low-frequency B clock */
2746 cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2747 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
2748 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2749 | (0 << CMU_EN_BIT_POS)
2750 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2751
2752 #if defined(CMU_LFBCLKEN0_LEUART0)
2753 /** Low-energy universal asynchronous receiver/transmitter 0 clock */
2754 cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2755 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2756 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2757 | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
2758 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2759 #endif
2760
2761 #if defined(CMU_LFBCLKEN0_CSEN)
2762 /** Capacitive Sense LF clock */
2763 cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2764 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2765 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2766 | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
2767 | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2768 #endif
2769
2770 #if defined(CMU_LFBCLKEN0_LEUART1)
2771 /** Low-energy universal asynchronous receiver/transmitter 1 clock */
2772 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2773 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2774 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2775 | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
2776 | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2777 #endif
2778
2779 #if defined(CMU_LFBCLKEN0_SYSTICK)
2780 /** Cortex SYSTICK LF clock */
2781 cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
2782 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2783 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
2784 | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS)
2785 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2786 #endif
2787
2788 #if defined(_CMU_LFCCLKEN0_MASK)
2789 /***************/
2790 /* LF C branch */
2791 /***************/
2792
2793 /** Low-frequency C clock */
2794 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2795 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
2796 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2797 | (0 << CMU_EN_BIT_POS)
2798 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2799
2800 #if defined(CMU_LFCCLKEN0_USBLE)
2801 /** USB LE clock */
2802 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2803 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
2804 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
2805 | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
2806 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2807 #elif defined(CMU_LFCCLKEN0_USB)
2808 /** USB LE clock */
2809 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2810 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
2811 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
2812 | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
2813 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2814 #endif
2815 #endif
2816
2817 #if defined(_CMU_LFECLKEN0_MASK)
2818 /***************/
2819 /* LF E branch */
2820 /***************/
2821
2822 /** Low-frequency E clock */
2823 cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
2824 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
2825 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2826 | (0 << CMU_EN_BIT_POS)
2827 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2828
2829 /** Real-time counter and calendar clock */
2830 #if defined (CMU_LFECLKEN0_RTCC)
2831 cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
2832 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
2833 | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
2834 | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
2835 | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2836 #endif
2837 #endif
2838
2839 /**********************************/
2840 /* Asynchronous peripheral clocks */
2841 /**********************************/
2842
2843 #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
2844 /** ADC0 asynchronous clock */
2845 cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
2846 | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS)
2847 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2848 | (0 << CMU_EN_BIT_POS)
2849 | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2850 #endif
2851
2852 #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
2853 /** ADC1 asynchronous clock */
2854 cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
2855 | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS)
2856 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
2857 | (0 << CMU_EN_BIT_POS)
2858 | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2859 #endif
2860
2861 #if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK)
2862 /** SDIO reference clock */
2863 cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2864 | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS)
2865 | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS)
2866 | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS)
2867 | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2868 #endif
2869
2870 #if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK)
2871 /** QSPI0 reference clock */
2872 cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2873 | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS)
2874 | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS)
2875 | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS)
2876 | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2877 #endif
2878
2879 #if defined(_CMU_PDMCTRL_PDMCLKEN_MASK)
2880 /** PDM reference clock */
2881 cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
2882 | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS)
2883 | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS)
2884 | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS)
2885 | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
2886 #endif
2887 };
2888
2889 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
2890 /* Deprecated CMU_Clock_TypeDef member */
2891 #define cmuClock_CORELE cmuClock_HFLE
2892 /** @endcond */
2893
2894 /** Oscillator types. */
2895 SL_ENUM(CMU_Osc_TypeDef) {
2896 cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */
2897 cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */
2898 cmuOsc_HFXO, /**< High-frequency crystal oscillator. */
2899 cmuOsc_HFRCO, /**< High-frequency RC oscillator. */
2900 cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */
2901 #if defined(_CMU_STATUS_USHFRCOENS_MASK)
2902 cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */
2903 #endif
2904 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
2905 cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */
2906 #endif
2907 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0)
2908 cmuOsc_CLKIN0, /**< External oscillator. */
2909 #endif
2910 #if defined(PLFRCO_PRESENT)
2911 cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */
2912 #endif
2913 };
2914
2915 /** Oscillator modes. */
2916 SL_ENUM(CMU_OscMode_TypeDef) {
2917 cmuOscMode_Crystal, /**< Crystal oscillator. */
2918 cmuOscMode_AcCoupled, /**< AC-coupled buffer. */
2919 cmuOscMode_External, /**< External digital clock. */
2920 };
2921
2922 /** Selectable clock sources. */
2923 SL_ENUM(CMU_Select_TypeDef) {
2924 cmuSelect_Error, /**< Usage error. */
2925 cmuSelect_Disabled, /**< Clock selector disabled. */
2926 cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */
2927 cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */
2928 cmuSelect_HFXO, /**< High-frequency crystal oscillator. */
2929 cmuSelect_HFRCO, /**< High-frequency RC oscillator. */
2930 cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */
2931 cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */
2932 cmuSelect_HFSRCCLK, /**< High-frequency source clock. */
2933 cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
2934 Tiny Gecko and for USBC (not used on Gecko). */
2935 #if defined(CMU_STATUS_USHFRCOENS)
2936 cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */
2937 #endif
2938 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2)
2939 cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */
2940 #endif
2941 #if defined(CMU_HFXOCTRL_HFXOX2EN)
2942 cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */
2943 #endif
2944 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
2945 cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */
2946 #endif
2947 #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2)
2948 cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */
2949 #endif
2950 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0)
2951 cmuSelect_CLKIN0, /**< External clock input. */
2952 #endif
2953 #if defined(PLFRCO_PRESENT)
2954 cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */
2955 #endif
2956 };
2957
2958 #if defined(CMU_HFCORECLKEN0_LE)
2959 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
2960 /* Deprecated CMU_Select_TypeDef member */
2961 #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
2962 /** @endcond */
2963 #endif
2964
2965 #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
2966 /** HFXO tuning modes */
2967 SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) {
2968 cmuHFXOTuningMode_Auto = 0,
2969 cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */
2970 #if defined(CMU_CMD_HFXOSHUNTOPTSTART)
2971 cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */
2972 cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */
2973 | CMU_CMD_HFXOSHUNTOPTSTART,
2974 #endif
2975 };
2976 #endif
2977
2978 #if defined(_CMU_CTRL_LFXOBOOST_MASK)
2979 /** LFXO Boost values. */
2980 SL_ENUM(CMU_LFXOBoost_TypeDef) {
2981 cmuLfxoBoost70 = 0x0,
2982 cmuLfxoBoost100 = 0x2,
2983 #if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK)
2984 cmuLfxoBoost70Reduced = 0x1,
2985 cmuLfxoBoost100Reduced = 0x3,
2986 #endif
2987 };
2988 #endif
2989
2990 #if defined(CMU_OSCENCMD_DPLLEN)
2991 /** DPLL reference clock selector. */
2992 SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) {
2993 cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */
2994 cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */
2995 cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */
2996 };
2997
2998 /** DPLL reference clock edge detect selector. */
2999 SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) {
3000 cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */
3001 cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */
3002 };
3003
3004 /** DPLL lock mode selector. */
3005 SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) {
3006 cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */
3007 cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */
3008 };
3009 #endif // CMU_OSCENCMD_DPLLEN
3010
3011 /*******************************************************************************
3012 ******************************* STRUCTS ***********************************
3013 ******************************************************************************/
3014
3015 /** LFXO initialization structure.
3016 * Initialization values should be obtained from a configuration tool,
3017 * application note or crystal data sheet. */
3018 typedef struct {
3019 #if defined(_CMU_LFXOCTRL_MASK)
3020 uint8_t ctune; /**< CTUNE (load capacitance) value */
3021 uint8_t gain; /**< Gain/max startup margin */
3022 #else
3023 CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */
3024 #endif
3025 uint8_t timeout; /**< Startup delay */
3026 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
3027 } CMU_LFXOInit_TypeDef;
3028
3029 #if defined(_CMU_LFXOCTRL_MASK)
3030 /** Default LFXO initialization values. */
3031 #define CMU_LFXOINIT_DEFAULT \
3032 { \
3033 _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
3034 _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
3035 _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \
3036 cmuOscMode_Crystal, /* Crystal oscillator */ \
3037 }
3038 /** Default LFXO initialization for external clock */
3039 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
3040 { \
3041 0, /* No CTUNE value needed */ \
3042 0, /* No LFXO startup gain */ \
3043 _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
3044 cmuOscMode_External, /* External digital clock */ \
3045 }
3046 #else
3047 /** Default LFXO initialization values. */
3048 #define CMU_LFXOINIT_DEFAULT \
3049 { \
3050 cmuLfxoBoost70, \
3051 _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
3052 cmuOscMode_Crystal, \
3053 }
3054 /** Default LFXO initialization for external clock */
3055 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
3056 { \
3057 cmuLfxoBoost70, \
3058 _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
3059 cmuOscMode_External, \
3060 }
3061 #endif
3062
3063 /** HFXO initialization structure.
3064 * Initialization values should be obtained from a configuration tool,
3065 * application note or crystal data sheet. */
3066 typedef struct {
3067 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
3068 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
3069 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
3070 uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
3071 uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
3072 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
3073 uint8_t timeoutSteady; /**< Timeout - steady-state */
3074 uint8_t timeoutStartup; /**< Timeout - startup */
3075 #elif defined(_CMU_HFXOCTRL_MASK)
3076 bool lowPowerMode; /**< Enable low-power mode */
3077 bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
3078 bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
3079 bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
3080 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
3081 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
3082 uint8_t regIshSteadyState; /**< Shunt steady-state current */
3083 uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
3084 uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
3085 uint8_t thresholdPeakDetect; /**< Peak detection threshold */
3086 uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */
3087 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
3088 uint8_t timeoutSteady; /**< Timeout - steady-state */
3089 uint8_t timeoutStartup; /**< Timeout - startup */
3090 #else
3091 uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */
3092 uint8_t timeout; /**< Startup delay */
3093 bool glitchDetector; /**< Enable/disable glitch detector */
3094 #endif
3095 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
3096 } CMU_HFXOInit_TypeDef;
3097
3098 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
3099 /** Default HFXO init. */
3100 #define CMU_HFXOINIT_DEFAULT \
3101 { \
3102 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3103 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3104 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
3105 _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
3106 _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
3107 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
3108 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3109 cmuOscMode_Crystal, \
3110 }
3111 /** Init of HFXO with external clock. */
3112 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
3113 { \
3114 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3115 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3116 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
3117 _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
3118 _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
3119 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
3120 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3121 cmuOscMode_External, \
3122 }
3123 #elif defined(_CMU_HFXOCTRL_MASK)
3124 /**
3125 * Default HFXO initialization values for Platform 2 devices, which contain a
3126 * separate HFXOCTRL register.
3127 */
3128 #if defined(_EFR_DEVICE)
3129 #define CMU_HFXOINIT_DEFAULT \
3130 { \
3131 false, /* Low-noise mode for EFR32 */ \
3132 false, /* @deprecated no longer in use */ \
3133 false, /* @deprecated no longer in use */ \
3134 false, /* @deprecated no longer in use */ \
3135 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3136 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3137 0xA, /* Default Shunt steady-state current */ \
3138 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
3139 0x7, /* Recommended steady-state XO core bias current */ \
3140 0x6, /* Recommended peak detection threshold */ \
3141 0x2, /* Recommended shunt optimization timeout */ \
3142 0xA, /* Recommended peak detection timeout */ \
3143 0x4, /* Recommended steady timeout */ \
3144 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3145 cmuOscMode_Crystal, \
3146 }
3147 #else /* EFM32 device */
3148 #define CMU_HFXOINIT_DEFAULT \
3149 { \
3150 true, /* Low-power mode for EFM32 */ \
3151 false, /* @deprecated no longer in use */ \
3152 false, /* @deprecated no longer in use */ \
3153 false, /* @deprecated no longer in use */ \
3154 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
3155 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
3156 0xA, /* Default shunt steady-state current */ \
3157 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
3158 0x7, /* Recommended steady-state osc core bias current */ \
3159 0x6, /* Recommended peak detection threshold */ \
3160 0x2, /* Recommended shunt optimization timeout */ \
3161 0xA, /* Recommended peak detection timeout */ \
3162 0x4, /* Recommended steady timeout */ \
3163 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
3164 cmuOscMode_Crystal, \
3165 }
3166 #endif /* _EFR_DEVICE */
3167 /** Init of HFXO with external clock. */
3168 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
3169 { \
3170 true, /* Low-power mode */ \
3171 false, /* @deprecated no longer in use */ \
3172 false, /* @deprecated no longer in use */ \
3173 false, /* @deprecated no longer in use */ \
3174 0, /* Startup CTUNE=0 recommended for external clock */ \
3175 0, /* Steady CTUNE=0 recommended for external clock */ \
3176 0xA, /* Default shunt steady-state current */ \
3177 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
3178 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
3179 0x6, /* Recommended peak detection threshold */ \
3180 0x2, /* Recommended shunt optimization timeout */ \
3181 0x0, /* Peak-detect not recommended for external clock usage */ \
3182 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
3183 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
3184 cmuOscMode_External, \
3185 }
3186 #else /* _CMU_HFXOCTRL_MASK */
3187 /**
3188 * Default HFXO initialization values for Platform 1 devices.
3189 */
3190 #define CMU_HFXOINIT_DEFAULT \
3191 { \
3192 _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
3193 _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \
3194 false, /* Disable glitch detector */ \
3195 cmuOscMode_Crystal, /* Crystal oscillator */ \
3196 }
3197 /** Default HFXO initialization for external clock */
3198 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
3199 { \
3200 0, /* Minimal HFXO boost, 50% */ \
3201 _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
3202 false, /* Disable glitch detector */ \
3203 cmuOscMode_External, /* External digital clock */ \
3204 }
3205 #endif /* _CMU_HFXOCTRL_MASK */
3206
3207 #if defined(CMU_OSCENCMD_DPLLEN)
3208 /** DPLL initialization structure.
3209 * Frequency will be Fref*(N+1)/(M+1). */
3210 typedef struct {
3211 uint32_t frequency; /**< PLL frequency value, max 40 MHz. */
3212 uint16_t n; /**< Factor N. 300 <= N <= 4095 */
3213 uint16_t m; /**< Factor M. M <= 4095 */
3214 uint8_t ssInterval; /**< Spread spectrum update interval. */
3215 uint8_t ssAmplitude; /**< Spread spectrum amplitude. */
3216 CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */
3217 CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
3218 CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
3219 bool autoRecover; /**< Enable automatic lock recovery. */
3220 } CMU_DPLLInit_TypeDef;
3221
3222 /**
3223 * DPLL initialization values for 39,998,805 Hz using LFXO as reference
3224 * clock, M=2 and N=3661.
3225 */
3226 #define CMU_DPLL_LFXO_TO_40MHZ \
3227 { \
3228 39998805, /* Target frequency. */ \
3229 3661, /* Factor N. */ \
3230 2, /* Factor M. */ \
3231 0, /* No spread spectrum clocking. */ \
3232 0, /* No spread spectrum clocking. */ \
3233 cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \
3234 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
3235 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
3236 true /* Enable automatic lock recovery. */ \
3237 }
3238 #endif // CMU_OSCENCMD_DPLLEN
3239
3240 /*******************************************************************************
3241 ***************************** PROTOTYPES **********************************
3242 ******************************************************************************/
3243
3244 #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
3245 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
3246 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
3247
3248 #elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
3249 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
3250 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
3251 #endif
3252
3253 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
3254
3255 #if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK)
3256 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
3257 CMU_Osc_TypeDef upSel);
3258 #endif
3259
3260 uint32_t CMU_CalibrateCountGet(void);
3261 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
3262 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
3263 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
3264 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
3265
3266 #if defined(_SILICON_LABS_32B_SERIES_1)
3267 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc);
3268 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
3269 #endif
3270
3271 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
3272 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
3273 uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock);
3274
3275 #if defined(CMU_OSCENCMD_DPLLEN)
3276 bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init);
3277 #endif
3278 void CMU_FreezeEnable(bool enable);
3279
3280 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
3281 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
3282 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
3283
3284 #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
3285 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
3286 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
3287 #endif
3288
3289 #if defined(_CMU_HFRCOCTRL_SUDELAY_MASK)
3290 uint32_t CMU_HFRCOStartupDelayGet(void);
3291 void CMU_HFRCOStartupDelaySet(uint32_t delay);
3292 #endif
3293
3294 #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
3295 CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void);
3296 void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq);
3297 uint32_t CMU_USHFRCOFreqGet(void);
3298 #endif
3299
3300 #if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK)
3301 void CMU_HFXOAutostartEnable(uint32_t userSel,
3302 bool enEM0EM1Start,
3303 bool enEM0EM1StartSel);
3304 #endif
3305
3306 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
3307
3308 uint32_t CMU_LCDClkFDIVGet(void);
3309 void CMU_LCDClkFDIVSet(uint32_t div);
3310 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
3311 void CMU_LFXOPrecisionSet(uint16_t precision);
3312 uint16_t CMU_LFXOPrecisionGet(void);
3313
3314 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
3315 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
3316 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
3317
3318 #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
3319 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
3320 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
3321 CMU_HFXOTuningMode_TypeDef mode,
3322 bool wait);
3323 #endif
3324
3325 #if (_SILICON_LABS_32B_SERIES < 2)
3326 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
3327 bool CMU_PCNTClockExternalGet(unsigned int instance);
3328 #endif
3329
3330 #if defined(_CMU_USHFRCOCONF_BAND_MASK)
3331 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
3332 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
3333 uint32_t CMU_USHFRCOFreqGet(void);
3334 #endif
3335 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
3336
3337 #if defined(CMU_CALCTRL_CONT)
3338 /***************************************************************************//**
3339 * @brief
3340 * Configure continuous calibration mode.
3341 * @param[in] enable
3342 * If true, enables continuous calibration, if false disables continuous
3343 * calibration.
3344 ******************************************************************************/
3345 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
3346 {
3347 BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable);
3348 }
3349 #endif
3350
3351 /***************************************************************************//**
3352 * @brief
3353 * Start calibration.
3354 * @note
3355 * This call is usually invoked after CMU_CalibrateConfig() and possibly
3356 * CMU_CalibrateCont().
3357 ******************************************************************************/
3358 __STATIC_INLINE void CMU_CalibrateStart(void)
3359 {
3360 CMU->CMD = CMU_CMD_CALSTART;
3361 }
3362
3363 #if defined(CMU_CMD_CALSTOP)
3364 /***************************************************************************//**
3365 * @brief
3366 * Stop the calibration counters.
3367 ******************************************************************************/
3368 __STATIC_INLINE void CMU_CalibrateStop(void)
3369 {
3370 CMU->CMD = CMU_CMD_CALSTOP;
3371 }
3372 #endif
3373
3374 /***************************************************************************//**
3375 * @brief
3376 * Convert divider to logarithmic value. It only works for even
3377 * numbers equal to 2^n.
3378 *
3379 * @param[in] div
3380 * An unscaled divider.
3381 *
3382 * @return
3383 * Logarithm base 2 (binary) value, i.e. exponent as used by fixed
3384 * 2^n prescalers.
3385 ******************************************************************************/
3386 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
3387 {
3388 uint32_t log2;
3389
3390 /* Fixed 2^n prescalers take argument of 32768 or less. */
3391 EFM_ASSERT((div > 0U) && (div <= 32768U));
3392
3393 /* Count leading zeroes and "reverse" result */
3394 log2 = 31UL - __CLZ(div);
3395
3396 return log2;
3397 }
3398
3399 #if defined(CMU_OSCENCMD_DPLLEN)
3400 /***************************************************************************//**
3401 * @brief
3402 * Unlock DPLL.
3403 * @note
3404 * HFRCO is not turned off.
3405 ******************************************************************************/
3406 __STATIC_INLINE void CMU_DPLLUnlock(void)
3407 {
3408 CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
3409 }
3410 #endif
3411
3412 /***************************************************************************//**
3413 * @brief
3414 * Clear one or more pending CMU interrupts.
3415 *
3416 * @param[in] flags
3417 * CMU interrupt sources to clear.
3418 ******************************************************************************/
3419 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
3420 {
3421 CMU->IFC = flags;
3422 }
3423
3424 /***************************************************************************//**
3425 * @brief
3426 * Disable one or more CMU interrupts.
3427 *
3428 * @param[in] flags
3429 * CMU interrupt sources to disable.
3430 ******************************************************************************/
3431 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
3432 {
3433 CMU->IEN &= ~flags;
3434 }
3435
3436 /***************************************************************************//**
3437 * @brief
3438 * Enable one or more CMU interrupts.
3439 *
3440 * @note
3441 * Depending on use case, a pending interrupt may already be set prior to
3442 * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling
3443 * if the pending interrupt should be ignored.
3444 *
3445 * @param[in] flags
3446 * CMU interrupt sources to enable.
3447 ******************************************************************************/
3448 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
3449 {
3450 CMU->IEN |= flags;
3451 }
3452
3453 /***************************************************************************//**
3454 * @brief
3455 * Get pending CMU interrupts.
3456 *
3457 * @return
3458 * CMU interrupt sources pending.
3459 ******************************************************************************/
3460 __STATIC_INLINE uint32_t CMU_IntGet(void)
3461 {
3462 return CMU->IF;
3463 }
3464
3465 /***************************************************************************//**
3466 * @brief
3467 * Get enabled and pending CMU interrupt flags.
3468 *
3469 * @details
3470 * Useful for handling more interrupt sources in the same interrupt handler.
3471 *
3472 * @note
3473 * This function does not clear event bits.
3474 *
3475 * @return
3476 * Pending and enabled CMU interrupt sources.
3477 * The return value is the bitwise AND of
3478 * - the enabled interrupt sources in CMU_IEN and
3479 * - the pending interrupt flags CMU_IF
3480 ******************************************************************************/
3481 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
3482 {
3483 uint32_t ien;
3484
3485 ien = CMU->IEN;
3486 return CMU->IF & ien;
3487 }
3488
3489 /**************************************************************************//**
3490 * @brief
3491 * Set one or more pending CMU interrupts.
3492 *
3493 * @param[in] flags
3494 * CMU interrupt sources to set to pending.
3495 *****************************************************************************/
3496 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
3497 {
3498 CMU->IFS = flags;
3499 }
3500
3501 /***************************************************************************//**
3502 * @brief
3503 * Lock the CMU to protect some of its registers against unintended
3504 * modification.
3505 *
3506 * @details
3507 * See the reference manual for CMU registers that will be
3508 * locked.
3509 *
3510 * @note
3511 * If locking the CMU registers, they must be unlocked prior to using any
3512 * CMU API functions modifying CMU registers protected by the lock.
3513 ******************************************************************************/
3514 __STATIC_INLINE void CMU_Lock(void)
3515 {
3516 CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
3517 }
3518
3519 /***************************************************************************//**
3520 * @brief
3521 * Convert logarithm of 2 prescaler to division factor.
3522 * @deprecated
3523 * Deprecated and marked for removal in a later release. It will be replaced
3524 * by SL_Log2ToDiv.
3525 * @param[in] log2
3526 * Logarithm of 2, as used by fixed prescalers.
3527 *
3528 * @return
3529 * Dividend.
3530 ******************************************************************************/
3531 __STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 uint32_t CMU_Log2ToDiv(uint32_t log2)
3532 {
3533 return SL_Log2ToDiv(log2);
3534 }
3535
3536 /***************************************************************************//**
3537 * @brief
3538 * Unlock the CMU so that writing to locked registers again is possible.
3539 ******************************************************************************/
3540 __STATIC_INLINE void CMU_Unlock(void)
3541 {
3542 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
3543 }
3544
3545 #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
3546 /***************************************************************************//**
3547 * @brief
3548 * Get the current HFRCO frequency.
3549 *
3550 * @deprecated
3551 * A deprecated function. New code should use @ref CMU_HFRCOBandGet().
3552 *
3553 * @return
3554 * HFRCO frequency.
3555 ******************************************************************************/
3556 __STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
3557 {
3558 return CMU_HFRCOBandGet();
3559 }
3560
3561 /***************************************************************************//**
3562 * @brief
3563 * Set HFRCO calibration for the selected target frequency.
3564 *
3565 * @deprecated
3566 * A deprecated function. New code should use @ref CMU_HFRCOBandSet().
3567 *
3568 * @param[in] setFreq
3569 * HFRCO frequency to set.
3570 ******************************************************************************/
3571 __STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
3572 {
3573 CMU_HFRCOBandSet(setFreq);
3574 }
3575 #endif
3576
3577 #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
3578 /***************************************************************************//**
3579 * @brief
3580 * Get the current AUXHFRCO frequency.
3581 *
3582 * @deprecated
3583 * A deprecated function. New code should use @ref CMU_AUXHFRCOBandGet().
3584 *
3585 * @return
3586 * AUXHFRCO frequency.
3587 ******************************************************************************/
3588 __STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
3589 {
3590 return CMU_AUXHFRCOBandGet();
3591 }
3592
3593 /***************************************************************************//**
3594 * @brief
3595 * Set AUXHFRCO calibration for the selected target frequency.
3596 *
3597 * @deprecated
3598 * A deprecated function. New code should use @ref CMU_AUXHFRCOBandSet().
3599 *
3600 * @param[in] setFreq
3601 * AUXHFRCO frequency to set.
3602 ******************************************************************************/
3603 __STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
3604 {
3605 CMU_AUXHFRCOBandSet(setFreq);
3606 }
3607 #endif
3608
3609 #endif // defined(_SILICON_LABS_32B_SERIES_2)
3610
3611 #if !defined(_SILICON_LABS_32B_SERIES_0)
3612 /***************************************************************************//**
3613 * @brief
3614 * Convert prescaler divider to a logarithmic value. It only works for even
3615 * numbers equal to 2^n.
3616 *
3617 * @param[in] presc
3618 * Prescaler value used to set the frequency divider. The divider is equal to
3619 * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be
3620 * equal to (divider - 1).
3621 *
3622 * @return
3623 * Logarithm base 2 (binary) value, i.e. exponent as used by fixed
3624 * 2^n prescalers.
3625 ******************************************************************************/
CMU_PrescToLog2(uint32_t presc)3626 __STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc)
3627 {
3628 uint32_t log2;
3629
3630 /* Integer prescalers take argument less than 32768. */
3631 EFM_ASSERT(presc < 32768U);
3632
3633 /* Count leading zeroes and "reverse" result. Consider divider value to get
3634 * exponent n from 2^n, so ('presc' +1). */
3635 log2 = 31UL - __CLZ(presc + (uint32_t) 1);
3636
3637 /* Check that prescaler is a 2^n number. */
3638 EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U));
3639
3640 return log2;
3641 }
3642 #endif // !defined(_SILICON_LABS_32B_SERIES_0)
3643
3644 /** @} (end addtogroup cmu) */
3645
3646 #ifdef __cplusplus
3647 }
3648 #endif
3649
3650 #endif /* defined(CMU_PRESENT) */
3651 #endif /* EM_CMU_H */
3652
