1 /*
2 * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
3 * Copyright (c) 2020 Nordic Semiconductor ASA.
4 * Copyright (c) 2021 Laird Connectivity.
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 #include "target_cfg.h"
20 #include "region_defs.h"
21 #include "tfm_plat_defs.h"
22 #include "tfm_peripherals_config.h"
23 #include "region.h"
24 #include "array.h"
25
26 #include <spu.h>
27 #include <nrfx.h>
28 #include <nrfx_nvmc.h>
29 #include <hal/nrf_nvmc.h>
30 #include <hal/nrf_gpio.h>
31 #include <hal/nrf_spu.h>
32
33 #define PIN_XL1 0
34 #define PIN_XL2 1
35
36 #if !(defined(NRF91_SERIES) || defined(NRF53_SERIES))
37 #error "Invalid configuration"
38 #endif
39
40
41 #if TFM_PERIPHERAL_DCNF_SECURE
42 struct platform_data_t tfm_peripheral_dcnf = {
43 NRF_DCNF_S_BASE,
44 NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1),
45 };
46 #endif
47
48 #if TFM_PERIPHERAL_FPU_SECURE
49 struct platform_data_t tfm_peripheral_fpu = {
50 NRF_FPU_S_BASE,
51 NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1),
52 };
53 #endif
54
55 #if TFM_PERIPHERAL_OSCILLATORS_SECURE
56 struct platform_data_t tfm_peripheral_oscillators = {
57 NRF_OSCILLATORS_S_BASE,
58 NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1),
59 };
60 #endif
61
62 #if TFM_PERIPHERAL_REGULATORS_SECURE
63 struct platform_data_t tfm_peripheral_regulators = {
64 NRF_REGULATORS_S_BASE,
65 NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1),
66 };
67 #endif
68
69 #if TFM_PERIPHERAL_CLOCK_SECURE
70 struct platform_data_t tfm_peripheral_clock = {
71 NRF_CLOCK_S_BASE,
72 NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1),
73 };
74 #endif
75
76 #if TFM_PERIPHERAL_POWER_SECURE
77 struct platform_data_t tfm_peripheral_power = {
78 NRF_POWER_S_BASE,
79 NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1),
80 };
81 #endif
82
83 #if TFM_PERIPHERAL_RESET_SECURE
84 struct platform_data_t tfm_peripheral_reset = {
85 NRF_RESET_S_BASE,
86 NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1),
87 };
88 #endif
89
90 #if TFM_PERIPHERAL_SPIM0_SECURE
91 struct platform_data_t tfm_peripheral_spim0 = {
92 NRF_SPIM0_S_BASE,
93 NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
94 };
95 #endif
96
97 #if TFM_PERIPHERAL_SPIS0_SECURE
98 struct platform_data_t tfm_peripheral_spis0 = {
99 NRF_SPIS0_S_BASE,
100 NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
101 };
102 #endif
103
104 #if TFM_PERIPHERAL_TWIM0_SECURE
105 struct platform_data_t tfm_peripheral_twim0 = {
106 NRF_TWIM0_S_BASE,
107 NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
108 };
109 #endif
110
111 #if TFM_PERIPHERAL_TWIS0_SECURE
112 struct platform_data_t tfm_peripheral_twis0 = {
113 NRF_TWIS0_S_BASE,
114 NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
115 };
116 #endif
117
118 #if TFM_PERIPHERAL_UARTE0_SECURE
119 struct platform_data_t tfm_peripheral_uarte0 = {
120 NRF_UARTE0_S_BASE,
121 NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
122 };
123 #endif
124
125 #if TFM_PERIPHERAL_SPIM1_SECURE
126 struct platform_data_t tfm_peripheral_spim1 = {
127 NRF_SPIM1_S_BASE,
128 NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
129 };
130 #endif
131
132 #if TFM_PERIPHERAL_SPIS1_SECURE
133 struct platform_data_t tfm_peripheral_spis1 = {
134 NRF_SPIS1_S_BASE,
135 NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
136 };
137 #endif
138
139 #if TFM_PERIPHERAL_TWIM1_SECURE
140 struct platform_data_t tfm_peripheral_twim1 = {
141 NRF_TWIM1_S_BASE,
142 NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
143 };
144 #endif
145
146 #if TFM_PERIPHERAL_TWIS1_SECURE
147 struct platform_data_t tfm_peripheral_twis1 = {
148 NRF_TWIS1_S_BASE,
149 NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
150 };
151 #endif
152
153 #if TFM_PERIPHERAL_UARTE1_SECURE
154 struct platform_data_t tfm_peripheral_uarte1 = {
155 NRF_UARTE1_S_BASE,
156 NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
157 };
158 #endif
159
160 #if TFM_PERIPHERAL_SPIM4_SECURE
161 struct platform_data_t tfm_peripheral_spim4 = {
162 NRF_SPIM4_S_BASE,
163 NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
164 };
165 #endif
166
167 #if TFM_PERIPHERAL_SPIM2_SECURE
168 struct platform_data_t tfm_peripheral_spim2 = {
169 NRF_SPIM2_S_BASE,
170 NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
171 };
172 #endif
173
174 #if TFM_PERIPHERAL_SPIS2_SECURE
175 struct platform_data_t tfm_peripheral_spis2 = {
176 NRF_SPIS2_S_BASE,
177 NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
178 };
179 #endif
180
181 #if TFM_PERIPHERAL_TWIM2_SECURE
182 struct platform_data_t tfm_peripheral_twim2 = {
183 NRF_TWIM2_S_BASE,
184 NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
185 };
186 #endif
187
188 #if TFM_PERIPHERAL_TWIS2_SECURE
189 struct platform_data_t tfm_peripheral_twis2 = {
190 NRF_TWIS2_S_BASE,
191 NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
192 };
193 #endif
194
195 #if TFM_PERIPHERAL_UARTE2_SECURE
196 struct platform_data_t tfm_peripheral_uarte2 = {
197 NRF_UARTE2_S_BASE,
198 NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
199 };
200 #endif
201
202 #if TFM_PERIPHERAL_SPIM3_SECURE
203 struct platform_data_t tfm_peripheral_spim3 = {
204 NRF_SPIM3_S_BASE,
205 NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1),
206 };
207 #endif
208
209 #if TFM_PERIPHERAL_SPIS3_SECURE
210 struct platform_data_t tfm_peripheral_spis3 = {
211 NRF_SPIS3_S_BASE,
212 NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1),
213 };
214 #endif
215
216 #if TFM_PERIPHERAL_TWIM3_SECURE
217 struct platform_data_t tfm_peripheral_twim3 = {
218 NRF_TWIM3_S_BASE,
219 NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1),
220 };
221 #endif
222
223 #if TFM_PERIPHERAL_TWIS3_SECURE
224 struct platform_data_t tfm_peripheral_twis3 = {
225 NRF_TWIS3_S_BASE,
226 NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1),
227 };
228 #endif
229
230 #if TFM_PERIPHERAL_UARTE3_SECURE
231 struct platform_data_t tfm_peripheral_uarte3 = {
232 NRF_UARTE3_S_BASE,
233 NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1),
234 };
235 #endif
236
237 #if TFM_PERIPHERAL_SAADC_SECURE
238 struct platform_data_t tfm_peripheral_saadc = {
239 NRF_SAADC_S_BASE,
240 NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1),
241 };
242 #endif
243
244 #if TFM_PERIPHERAL_TIMER0_SECURE
245 struct platform_data_t tfm_peripheral_timer0 = {
246 NRF_TIMER0_S_BASE,
247 NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1),
248 };
249 #endif
250
251 #if TFM_PERIPHERAL_TIMER1_SECURE
252 struct platform_data_t tfm_peripheral_timer1 = {
253 NRF_TIMER1_S_BASE,
254 NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1),
255 };
256 #endif
257
258 #if TFM_PERIPHERAL_TIMER2_SECURE
259 struct platform_data_t tfm_peripheral_timer2 = {
260 NRF_TIMER2_S_BASE,
261 NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1),
262 };
263 #endif
264
265 #if TFM_PERIPHERAL_RTC0_SECURE
266 struct platform_data_t tfm_peripheral_rtc0 = {
267 NRF_RTC0_S_BASE,
268 NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1),
269 };
270 #endif
271
272 #if TFM_PERIPHERAL_RTC1_SECURE
273 struct platform_data_t tfm_peripheral_rtc1 = {
274 NRF_RTC1_S_BASE,
275 NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1),
276 };
277 #endif
278
279 #if TFM_PERIPHERAL_DPPI_SECURE
280 struct platform_data_t tfm_peripheral_dppi = {
281 NRF_DPPIC_S_BASE,
282 NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1),
283 };
284 #endif
285
286 #if TFM_PERIPHERAL_WDT_SECURE
287 struct platform_data_t tfm_peripheral_wdt = {
288 NRF_WDT_S_BASE,
289 NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1),
290 };
291 #endif
292
293 #if TFM_PERIPHERAL_WDT0_SECURE
294 struct platform_data_t tfm_peripheral_wdt0 = {
295 NRF_WDT0_S_BASE,
296 NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1),
297 };
298 #endif
299
300 #if TFM_PERIPHERAL_WDT1_SECURE
301 struct platform_data_t tfm_peripheral_wdt1 = {
302 NRF_WDT1_S_BASE,
303 NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1),
304 };
305 #endif
306
307 #if TFM_PERIPHERAL_COMP_SECURE
308 struct platform_data_t tfm_peripheral_comp = {
309 NRF_COMP_S_BASE,
310 NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1),
311 };
312 #endif
313
314 #if TFM_PERIPHERAL_LPCOMP_SECURE
315 struct platform_data_t tfm_peripheral_lpcomp = {
316 NRF_LPCOMP_S_BASE,
317 NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1),
318 };
319 #endif
320
321 #if TFM_PERIPHERAL_EGU0_SECURE
322 struct platform_data_t tfm_peripheral_egu0 = {
323 NRF_EGU0_S_BASE,
324 NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1),
325 };
326 #endif
327
328 #if TFM_PERIPHERAL_EGU1_SECURE
329 struct platform_data_t tfm_peripheral_egu1 = {
330 NRF_EGU1_S_BASE,
331 NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1),
332 };
333 #endif
334
335 #if TFM_PERIPHERAL_EGU2_SECURE
336 struct platform_data_t tfm_peripheral_egu2 = {
337 NRF_EGU2_S_BASE,
338 NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1),
339 };
340 #endif
341
342 #if TFM_PERIPHERAL_EGU3_SECURE
343 struct platform_data_t tfm_peripheral_egu3 = {
344 NRF_EGU3_S_BASE,
345 NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1),
346 };
347 #endif
348
349 #if TFM_PERIPHERAL_EGU4_SECURE
350 struct platform_data_t tfm_peripheral_egu4 = {
351 NRF_EGU4_S_BASE,
352 NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1),
353 };
354 #endif
355
356 #if TFM_PERIPHERAL_EGU5_SECURE
357 struct platform_data_t tfm_peripheral_egu5 = {
358 NRF_EGU5_S_BASE,
359 NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1),
360 };
361 #endif
362
363 #if TFM_PERIPHERAL_PWM0_SECURE
364 struct platform_data_t tfm_peripheral_pwm0 = {
365 NRF_PWM0_S_BASE,
366 NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1),
367 };
368 #endif
369
370 #if TFM_PERIPHERAL_PWM1_SECURE
371 struct platform_data_t tfm_peripheral_pwm1 = {
372 NRF_PWM1_S_BASE,
373 NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1),
374 };
375 #endif
376
377 #if TFM_PERIPHERAL_PWM2_SECURE
378 struct platform_data_t tfm_peripheral_pwm2 = {
379 NRF_PWM2_S_BASE,
380 NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1),
381 };
382 #endif
383
384 #if TFM_PERIPHERAL_PWM3_SECURE
385 struct platform_data_t tfm_peripheral_pwm3 = {
386 NRF_PWM3_S_BASE,
387 NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1),
388 };
389 #endif
390
391 #if TFM_PERIPHERAL_PDM0_SECURE
392 struct platform_data_t tfm_peripheral_pdm0 = {
393 NRF_PDM0_S_BASE,
394 NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1),
395 };
396 #endif
397
398 #if TFM_PERIPHERAL_PDM_SECURE
399 struct platform_data_t tfm_peripheral_pdm = {
400 NRF_PDM_S_BASE,
401 NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1),
402 };
403 #endif
404
405 #if TFM_PERIPHERAL_I2S0_SECURE
406 struct platform_data_t tfm_peripheral_i2s0 = {
407 NRF_I2S0_S_BASE,
408 NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1),
409 };
410 #endif
411
412 #if TFM_PERIPHERAL_I2S_SECURE
413 struct platform_data_t tfm_peripheral_i2s = {
414 NRF_I2S_S_BASE,
415 NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1),
416 };
417 #endif
418
419 #if TFM_PERIPHERAL_IPC_SECURE
420 struct platform_data_t tfm_peripheral_ipc = {
421 NRF_IPC_S_BASE,
422 NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1),
423 };
424 #endif
425
426 #if TFM_PERIPHERAL_FPU_SECURE
427 struct platform_data_t tfm_peripheral_fpu = {
428 NRF_FPU_S_BASE,
429 NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1),
430 };
431 #endif
432
433 #if TFM_PERIPHERAL_QSPI_SECURE
434 struct platform_data_t tfm_peripheral_qspi = {
435 NRF_QSPI_S_BASE,
436 NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1),
437 };
438 #endif
439
440 #if TFM_PERIPHERAL_NFCT_SECURE
441 struct platform_data_t tfm_peripheral_nfct = {
442 NRF_NFCT_S_BASE,
443 NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1),
444 };
445 #endif
446
447 #if TFM_PERIPHERAL_MUTEX_SECURE
448 struct platform_data_t tfm_peripheral_mutex = {
449 NRF_MUTEX_S_BASE,
450 NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1),
451 };
452 #endif
453
454 #if TFM_PERIPHERAL_QDEC0_SECURE
455 struct platform_data_t tfm_peripheral_qdec0 = {
456 NRF_QDEC0_S_BASE,
457 NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1),
458 };
459 #endif
460
461 #if TFM_PERIPHERAL_QDEC1_SECURE
462 struct platform_data_t tfm_peripheral_qdec1 = {
463 NRF_QDEC1_S_BASE,
464 NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1),
465 };
466 #endif
467
468 #if TFM_PERIPHERAL_USBD_SECURE
469 struct platform_data_t tfm_peripheral_usbd = {
470 NRF_USBD_S_BASE,
471 NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1),
472 };
473 #endif
474
475 #if TFM_PERIPHERAL_USBREG_SECURE
476 struct platform_data_t tfm_peripheral_usbreg = {
477 NRF_USBREGULATOR_S_BASE,
478 NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1),
479 };
480 #endif
481
482 #if TFM_PERIPHERAL_NVMC_SECURE
483 struct platform_data_t tfm_peripheral_nvmc = {
484 NRF_NVMC_S_BASE,
485 NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1),
486 };
487 #endif
488
489 #if TFM_PERIPHERAL_GPIO0_SECURE
490 struct platform_data_t tfm_peripheral_gpio0 = {
491 NRF_P0_S_BASE,
492 NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1),
493 };
494 #endif
495
496 #if TFM_PERIPHERAL_GPIO1_SECURE
497 struct platform_data_t tfm_peripheral_gpio1 = {
498 NRF_P1_S_BASE,
499 NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1),
500 };
501 #endif
502
503 #if TFM_PERIPHERAL_VMC_SECURE
504 struct platform_data_t tfm_peripheral_vmc = {
505 NRF_VMC_S_BASE,
506 NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1),
507 };
508 #endif
509
510 #ifdef PSA_API_TEST_IPC
511 struct platform_data_t
512 tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = {
513 FF_TEST_SERVER_PARTITION_MMIO_START,
514 FF_TEST_SERVER_PARTITION_MMIO_END
515 };
516
517 struct platform_data_t
518 tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO = {
519 FF_TEST_DRIVER_PARTITION_MMIO_START,
520 FF_TEST_DRIVER_PARTITION_MMIO_END
521 };
522
523 /* This platform implementation uses PSA_TEST_SCRATCH_AREA for
524 * storing the state between resets, but the FF_TEST_NVMEM_REGIONS
525 * definitons are still needed for tests to compile.
526 */
527 #define FF_TEST_NVMEM_REGION_START 0xFFFFFFFF
528 #define FF_TEST_NVMEM_REGION_END 0xFFFFFFFF
529 struct platform_data_t
530 tfm_peripheral_FF_TEST_NVMEM_REGION = {
531 FF_TEST_NVMEM_REGION_START,
532 FF_TEST_NVMEM_REGION_END
533 };
534 #endif /* PSA_API_TEST_IPC */
535
536
537 /* The section names come from the scatter file */
538 REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
539 REGION_DECLARE(Image$$, ER_VENEER, $$Base);
540 REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
541
542 const struct memory_region_limits memory_regions = {
543 .non_secure_code_start =
544 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
545 BL2_HEADER_SIZE,
546
547 .non_secure_partition_base =
548 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
549
550 .non_secure_partition_limit =
551 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
552 NS_PARTITION_SIZE - 1,
553
554 .veneer_base =
555 (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base),
556
557 .veneer_limit =
558 (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit),
559
560 #ifdef NRF_NS_SECONDARY
561 .secondary_partition_base = SECONDARY_PARTITION_START,
562 .secondary_partition_limit = SECONDARY_PARTITION_START +
563 SECONDARY_PARTITION_SIZE - 1,
564 #endif /* NRF_NS_SECONDARY */
565
566 #ifdef NRF_NS_STORAGE_PARTITION_START
567 .non_secure_storage_partition_base = NRF_NS_STORAGE_PARTITION_START,
568 .non_secure_storage_partition_limit = NRF_NS_STORAGE_PARTITION_START +
569 NRF_NS_STORAGE_PARTITION_SIZE - 1,
570 #endif /* NRF_NS_STORAGE_PARTITION_START */
571 };
572
573 /* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
574 * otherwise the processor ignores the write.
575 */
576 #define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
577
enable_fault_handlers(void)578 enum tfm_plat_err_t enable_fault_handlers(void)
579 {
580 /* Explicitly set secure fault priority to the highest */
581 NVIC_SetPriority(SecureFault_IRQn, 0);
582
583 /* Enables BUS, MEM, USG and Secure faults */
584 SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk |
585 SCB_SHCSR_BUSFAULTENA_Msk |
586 SCB_SHCSR_MEMFAULTENA_Msk |
587 SCB_SHCSR_SECUREFAULTENA_Msk;
588
589 return TFM_PLAT_ERR_SUCCESS;
590 }
591
system_reset_cfg(void)592 enum tfm_plat_err_t system_reset_cfg(void)
593 {
594 uint32_t reg_value = SCB->AIRCR;
595
596 /* Clear SCB_AIRCR_VECTKEY value */
597 reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
598
599 /* Enable system reset request only to the secure world */
600 reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk);
601
602 SCB->AIRCR = reg_value;
603
604 return TFM_PLAT_ERR_SUCCESS;
605 }
606
init_debug(void)607 enum tfm_plat_err_t init_debug(void)
608 {
609 #if defined(NRF91_SERIES)
610
611 #if !defined(DAUTH_CHIP_DEFAULT)
612 #error "Debug access on this platform can only be configured by programming the corresponding registers in UICR."
613 #endif
614
615 #elif defined(NRF53_SERIES)
616
617 #if defined(DAUTH_NONE)
618 /* Disable debugging */
619 NRF_CTRLAP->APPROTECT.DISABLE = 0;
620 NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0;
621 #elif defined(DAUTH_NS_ONLY)
622 /* Allow debugging Non-Secure only */
623 NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT;
624 NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0;
625 #elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT)
626 /* Allow debugging */
627 /* Use the configuration in UICR. */
628 NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT;
629 NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT;
630 #else
631 #error "No debug authentication setting is provided."
632 #endif
633
634 /* Lock access to APPROTECT, SECUREAPPROTECT */
635 NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked <<
636 CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk;
637 NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked <<
638 CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk;
639
640 #endif
641
642 return TFM_PLAT_ERR_SUCCESS;
643 }
644
645 /*----------------- NVIC interrupt target state to NS configuration ----------*/
nvic_interrupt_target_state_cfg(void)646 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
647 {
648 /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */
649 for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) {
650 NVIC->ITNS[i] = 0xFFFFFFFF;
651 }
652
653 /* Make sure that the SPU is targeted to S state */
654 NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_SPU));
655
656 #ifdef SECURE_UART1
657 /* UARTE1 is a secure peripheral, so its IRQ has to target S state */
658 NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_UARTE1));
659 #endif
660
661 return TFM_PLAT_ERR_SUCCESS;
662 }
663
664 /*----------------- NVIC interrupt enabling for S peripherals ----------------*/
nvic_interrupt_enable(void)665 enum tfm_plat_err_t nvic_interrupt_enable(void)
666 {
667 /* SPU interrupt enabling */
668 spu_enable_interrupts();
669
670 NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU));
671 NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU));
672
673 return TFM_PLAT_ERR_SUCCESS;
674 }
675
676 /*------------------- SAU/IDAU configuration functions -----------------------*/
677
sau_and_idau_cfg(void)678 void sau_and_idau_cfg(void)
679 {
680 /* IDAU (SPU) is always enabled. SAU is non-existent.
681 * Allow SPU to have precedence over (non-existing) ARMv8-M SAU.
682 */
683 TZ_SAU_Disable();
684 SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
685 }
686
spu_init_cfg(void)687 enum tfm_plat_err_t spu_init_cfg(void)
688 {
689 /*
690 * Configure SPU Regions for Non-Secure Code and SRAM (Data)
691 * Configure SPU for Peripheral Security
692 * Configure Non-Secure Callable Regions
693 * Configure Secondary Image Partition
694 * Configure Non-Secure Storage Partition
695 */
696
697 /* Reset Flash and SRAM configuration of regions that are not owned by
698 * the bootloader(s) to all-Secure.
699 */
700 spu_regions_reset_unlocked_secure();
701
702 uint32_t perm;
703
704 /* Configure Secure Code to be secure and RX */
705 perm = 0;
706 perm |= NRF_SPU_MEM_PERM_READ;
707 /* Do not permit writes to secure flash */
708 perm |= NRF_SPU_MEM_PERM_EXECUTE;
709
710 spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm,
711 SPU_LOCK_CONF_LOCKED);
712
713 /* Configure Secure RAM to be secure and RWX */
714 perm = 0;
715 perm |= NRF_SPU_MEM_PERM_READ;
716 perm |= NRF_SPU_MEM_PERM_WRITE;
717 /* Permit execute from Secure RAM because otherwise Crypto fails
718 * to initialize. */
719 perm |= NRF_SPU_MEM_PERM_EXECUTE;
720
721 spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm,
722 SPU_LOCK_CONF_LOCKED);
723
724 /* Configures SPU Code and Data regions to be non-secure */
725 perm = 0;
726 perm |= NRF_SPU_MEM_PERM_READ;
727 perm |= NRF_SPU_MEM_PERM_WRITE;
728 perm |= NRF_SPU_MEM_PERM_EXECUTE;
729
730 spu_regions_flash_config(memory_regions.non_secure_partition_base,
731 memory_regions.non_secure_partition_limit, SPU_SECURE_ATTR_NONSECURE,
732 perm, SPU_LOCK_CONF_LOCKED);
733
734 spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm,
735 SPU_LOCK_CONF_LOCKED);
736
737 /* Configures veneers region to be non-secure callable */
738 spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base,
739 memory_regions.veneer_limit - 1);
740
741 #ifdef NRF_NS_SECONDARY
742 perm = 0;
743 perm |= NRF_SPU_MEM_PERM_READ;
744 perm |= NRF_SPU_MEM_PERM_WRITE;
745
746 /* Secondary image partition */
747 spu_regions_flash_config(memory_regions.secondary_partition_base,
748 memory_regions.secondary_partition_limit, SPU_SECURE_ATTR_NONSECURE,
749 perm, SPU_LOCK_CONF_LOCKED);
750 #endif /* NRF_NS_SECONDARY */
751
752 #ifdef NRF_NS_STORAGE_PARTITION_START
753 /* Configures storage partition to be non-secure */
754 perm = 0;
755 perm |= NRF_SPU_MEM_PERM_READ;
756 perm |= NRF_SPU_MEM_PERM_WRITE;
757
758 spu_regions_flash_config(memory_regions.non_secure_storage_partition_base,
759 memory_regions.non_secure_storage_partition_limit,
760 SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED);
761 #endif /* NRF_NS_STORAGE_PARTITION_START */
762
763 return TFM_PLAT_ERR_SUCCESS;
764 }
765
spu_periph_init_cfg(void)766 enum tfm_plat_err_t spu_periph_init_cfg(void)
767 {
768 /* Peripheral configuration */
769 static const uint8_t target_peripherals[] = {
770 /* The following peripherals share ID:
771 * - FPU (FPU cannot be configured in NRF91 series, it's always NS)
772 * - DCNF (On 53, but not 91)
773 */
774 #ifndef NRF91_SERIES
775 NRFX_PERIPHERAL_ID_GET(NRF_FPU),
776 #endif
777 /* The following peripherals share ID:
778 * - REGULATORS
779 * - OSCILLATORS
780 */
781 NRFX_PERIPHERAL_ID_GET(NRF_REGULATORS),
782 /* The following peripherals share ID:
783 * - CLOCK
784 * - POWER
785 * - RESET (On 53, but not 91)
786 */
787 NRFX_PERIPHERAL_ID_GET(NRF_CLOCK),
788 /* The following peripherals share ID: (referred to as Serial-Box)
789 * - SPIMx
790 * - SPISx
791 * - TWIMx
792 * - TWISx
793 * - UARTEx
794 */
795 NRFX_PERIPHERAL_ID_GET(NRF_SPIM0),
796 #ifndef SECURE_UART1
797 /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */
798 NRFX_PERIPHERAL_ID_GET(NRF_SPIM1),
799 #endif
800 NRFX_PERIPHERAL_ID_GET(NRF_SPIM2),
801 NRFX_PERIPHERAL_ID_GET(NRF_SPIM3),
802 #ifdef NRF_SPIM4
803 NRFX_PERIPHERAL_ID_GET(NRF_SPIM4),
804 #endif
805 NRFX_PERIPHERAL_ID_GET(NRF_SAADC),
806 NRFX_PERIPHERAL_ID_GET(NRF_TIMER0),
807 NRFX_PERIPHERAL_ID_GET(NRF_TIMER1),
808 NRFX_PERIPHERAL_ID_GET(NRF_TIMER2),
809 NRFX_PERIPHERAL_ID_GET(NRF_RTC0),
810 NRFX_PERIPHERAL_ID_GET(NRF_RTC1),
811 NRFX_PERIPHERAL_ID_GET(NRF_DPPIC),
812 #ifndef PSA_API_TEST_IPC
813 #ifdef NRF_WDT0
814 /* WDT0 is used as a secure peripheral in PSA FF tests */
815 NRFX_PERIPHERAL_ID_GET(NRF_WDT0),
816 #endif
817 #ifdef NRF_WDT
818 NRFX_PERIPHERAL_ID_GET(NRF_WDT),
819 #endif
820 #endif /* PSA_API_TEST_IPC */
821 #ifdef NRF_WDT1
822 NRFX_PERIPHERAL_ID_GET(NRF_WDT1),
823 #endif
824 /* The following peripherals share ID:
825 * - COMP
826 * - LPCOMP
827 */
828 #ifdef NRF_COMP
829 NRFX_PERIPHERAL_ID_GET(NRF_COMP),
830 #endif
831 NRFX_PERIPHERAL_ID_GET(NRF_EGU0),
832 NRFX_PERIPHERAL_ID_GET(NRF_EGU1),
833 NRFX_PERIPHERAL_ID_GET(NRF_EGU2),
834 NRFX_PERIPHERAL_ID_GET(NRF_EGU3),
835 NRFX_PERIPHERAL_ID_GET(NRF_EGU4),
836 #ifndef PSA_API_TEST_IPC
837 /* EGU5 is used as a secure peripheral in PSA FF tests */
838 NRFX_PERIPHERAL_ID_GET(NRF_EGU5),
839 #endif
840 NRFX_PERIPHERAL_ID_GET(NRF_PWM0),
841 NRFX_PERIPHERAL_ID_GET(NRF_PWM1),
842 NRFX_PERIPHERAL_ID_GET(NRF_PWM2),
843 NRFX_PERIPHERAL_ID_GET(NRF_PWM3),
844 #ifdef NRF_PDM
845 NRFX_PERIPHERAL_ID_GET(NRF_PDM),
846 #endif
847 #ifdef NRF_PDM0
848 NRFX_PERIPHERAL_ID_GET(NRF_PDM0),
849 #endif
850 #ifdef NRF_I2S
851 NRFX_PERIPHERAL_ID_GET(NRF_I2S),
852 #endif
853 #ifdef NRF_I2S0
854 NRFX_PERIPHERAL_ID_GET(NRF_I2S0),
855 #endif
856 NRFX_PERIPHERAL_ID_GET(NRF_IPC),
857 #ifndef SECURE_QSPI
858 #ifdef NRF_QSPI
859 NRFX_PERIPHERAL_ID_GET(NRF_QSPI),
860 #endif
861 #endif
862 #ifdef NRF_NFCT
863 NRFX_PERIPHERAL_ID_GET(NRF_NFCT),
864 #endif
865 #ifdef NRF_MUTEX
866 NRFX_PERIPHERAL_ID_GET(NRF_MUTEX),
867 #endif
868 #ifdef NRF_QDEC0
869 NRFX_PERIPHERAL_ID_GET(NRF_QDEC0),
870 #endif
871 #ifdef NRF_QDEC1
872 NRFX_PERIPHERAL_ID_GET(NRF_QDEC1),
873 #endif
874 #ifdef NRF_USBD
875 NRFX_PERIPHERAL_ID_GET(NRF_USBD),
876 #endif
877 #ifdef NRF_USBREGULATOR
878 NRFX_PERIPHERAL_ID_GET(NRF_USBREGULATOR),
879 #endif
880 NRFX_PERIPHERAL_ID_GET(NRF_NVMC),
881 NRFX_PERIPHERAL_ID_GET(NRF_P0),
882 #ifdef NRF_P1
883 NRFX_PERIPHERAL_ID_GET(NRF_P1),
884 #endif
885 NRFX_PERIPHERAL_ID_GET(NRF_VMC),
886 };
887
888 for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) {
889 spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED);
890 }
891
892 /* DPPI channel configuration */
893 spu_dppi_config_non_secure(TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, SPU_LOCK_CONF_LOCKED);
894
895 /* GPIO pin configuration */
896 spu_gpio_config_non_secure(0, TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, SPU_LOCK_CONF_LOCKED);
897 #ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE
898 spu_gpio_config_non_secure(1, TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, SPU_LOCK_CONF_LOCKED);
899 #endif
900
901 #ifdef NRF53_SERIES
902 /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal
903 * oscillator (LFXO) can be used.
904 * This configuration can be done only from secure code, as otherwise those
905 * register fields are not accessible. That's why it is placed here.
906 */
907 nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
908 nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
909 #endif
910
911 /*
912 * 91 has an instruction cache.
913 * 53 has both instruction cache and a data cache.
914 *
915 * 53's instruction cache has an nrfx driver, but 91's cache is
916 * not supported by nrfx at time of writing.
917 *
918 * We enable all caches available here because non-secure cannot
919 * configure caches.
920 */
921 #if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK
922 nrfx_nvmc_icache_enable();
923 #elif defined(CACHE_PRESENT) // From MDK
924 NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
925 #endif
926
927 /* Enforce that the nRF5340 Network MCU is in the Non-Secure
928 * domain. Non-secure is the HW reset value for the network core
929 * so configuring this should not be necessary, but we want to
930 * make sure that the bootloader has not accidentally configured
931 * it to be secure. Additionally we lock the register to make sure
932 * it doesn't get changed by accident.
933 */
934 nrf_spu_extdomain_set(NRF_SPU, 0, false, true);
935
936 return TFM_PLAT_ERR_SUCCESS;
937 }
938
