1 /* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include "target_cfg.h" 9 #include "cmsis.h" 10 11 struct platform_data_t tfm_peripheral_gpio0 = { 12 GPIO0_CMSDK_BASE_S, 13 GPIO0_CMSDK_BASE_S + 0xFFF, 14 PPC_SP_MAIN_EXP0, 15 GPIO0_MAIN_PPCEXP0_POS_MASK 16 }; 17 18 struct platform_data_t tfm_peripheral_gpio1 = { 19 GPIO1_CMSDK_BASE_S, 20 GPIO1_CMSDK_BASE_S + 0xFFF, 21 PPC_SP_MAIN_EXP0, 22 GPIO1_MAIN_PPCEXP0_POS_MASK 23 }; 24 25 struct platform_data_t tfm_peripheral_gpio2 = { 26 GPIO2_CMSDK_BASE_S, 27 GPIO2_CMSDK_BASE_S + 0xFFF, 28 PPC_SP_MAIN_EXP0, 29 GPIO2_MAIN_PPCEXP0_POS_MASK 30 }; 31 32 struct platform_data_t tfm_peripheral_gpio3 = { 33 GPIO3_CMSDK_BASE_S, 34 GPIO3_CMSDK_BASE_S + 0xFFF, 35 PPC_SP_MAIN_EXP0, 36 GPIO3_MAIN_PPCEXP0_POS_MASK 37 }; 38 39 struct platform_data_t tfm_peripheral_dma1 = { 40 DMA_1_BASE_S, 41 DMA_1_BASE_S + 0xFFF, 42 PPC_SP_MAIN_EXP1, 43 DMA1_MAIN_PPCEXP1_POS_MASK 44 }; 45 46 struct platform_data_t tfm_peripheral_dma2 = { 47 DMA_2_BASE_S, 48 DMA_2_BASE_S + 0xFFF, 49 PPC_SP_MAIN_EXP1, 50 DMA2_MAIN_PPCEXP1_POS_MASK 51 }; 52 53 struct platform_data_t tfm_peripheral_dma3 = { 54 DMA_3_BASE_S, 55 DMA_3_BASE_S + 0xFFF, 56 PPC_SP_MAIN_EXP1, 57 DMA3_MAIN_PPCEXP1_POS_MASK 58 }; 59 60 struct platform_data_t tfm_peripheral_ethernet = { 61 ETHERNET_BASE_S, 62 ETHERNET_BASE_S + 0xFFFFF, 63 PPC_SP_MAIN_EXP0, 64 USB_AND_ETHERNET_MAIN_PPCEXP0_POS_MASK 65 }; 66 67 struct platform_data_t tfm_peripheral_usb = { 68 USB_BASE_S, 69 USB_BASE_S + 0xFFFFF, 70 PPC_SP_MAIN_EXP0, 71 USB_AND_ETHERNET_MAIN_PPCEXP0_POS_MASK 72 }; 73 74 struct platform_data_t tfm_peripheral_timer0 = { 75 SYSTIMER0_ARMV8_M_BASE_S, 76 SYSTIMER0_ARMV8_M_BASE_S + 0xFFF, 77 PPC_SP_PERIPH0, 78 SYSTEM_TIMER0_PERIPH_PPC0_POS_MASK 79 }; 80 81 struct platform_data_t tfm_peripheral_timer1 = { 82 SYSTIMER1_ARMV8_M_BASE_S, 83 SYSTIMER1_ARMV8_M_BASE_S + 0xFFF, 84 PPC_SP_PERIPH0, 85 SYSTEM_TIMER1_PERIPH_PPC0_POS_MASK 86 }; 87 88 struct platform_data_t tfm_peripheral_timer2 = { 89 SYSTIMER2_ARMV8_M_BASE_S, 90 SYSTIMER2_ARMV8_M_BASE_S + 0xFFF, 91 PPC_SP_PERIPH0, 92 SYSTEM_TIMER2_PERIPH_PPC0_POS_MASK 93 }; 94 95 struct platform_data_t tfm_peripheral_timer3 = { 96 SYSTIMER3_ARMV8_M_BASE_S, 97 SYSTIMER3_ARMV8_M_BASE_S + 0xFFF, 98 PPC_SP_PERIPH0, 99 SYSTEM_TIMER3_PERIPH_PPC0_POS_MASK 100 }; 101 102 struct platform_data_t tfm_peripheral_slowclk = { 103 SLOWCLK_TIMER_CMSDK_BASE_S, 104 SLOWCLK_TIMER_CMSDK_BASE_S + 0xFFF, 105 PPC_SP_PERIPH1, 106 SLOWCLK_TIMER_PERIPH_PPC1_POS_MASK 107 }; 108 109 struct platform_data_t tfm_peripheral_touch_i2c = { 110 FPGA_SBCon_I2C_TOUCH_BASE_S, 111 FPGA_SBCon_I2C_TOUCH_BASE_S + 0xFFF, 112 PPC_SP_PERIPH_EXP1, 113 FPGA_I2C_TOUCH_PERIPH_PPCEXP1_POS_MASK 114 }; 115 116 struct platform_data_t tfm_peripheral_audio_i2c = { 117 FPGA_SBCon_I2C_AUDIO_BASE_S, 118 FPGA_SBCon_I2C_AUDIO_BASE_S + 0xFFF, 119 PPC_SP_PERIPH_EXP1, 120 FPGA_I2C_AUDIO_PERIPH_PPCEXP1_POS_MASK 121 }; 122 123 struct platform_data_t tfm_peripheral_adc_spi = { 124 FPGA_SPI_ADC_BASE_S, 125 FPGA_SPI_ADC_BASE_S + 0xFFF, 126 PPC_SP_PERIPH_EXP1, 127 FPGA_SPI_ADC_PERIPH_PPCEXP1_POS_MASK 128 }; 129 130 struct platform_data_t tfm_peripheral_shield0_spi = { 131 FPGA_SPI_SHIELD0_BASE_S, 132 FPGA_SPI_SHIELD0_BASE_S + 0xFFF, 133 PPC_SP_PERIPH_EXP1, 134 FPGA_SPI_SHIELD0_PERIPH_PPCEXP1_POS_MASK 135 }; 136 137 struct platform_data_t tfm_peripheral_shield1_spi = { 138 FPGA_SPI_SHIELD1_BASE_S, 139 FPGA_SPI_SHIELD1_BASE_S + 0xFFF, 140 PPC_SP_PERIPH_EXP1, 141 FPGA_SPI_SHIELD1_PERIPH_PPCEXP1_POS_MASK 142 }; 143 144 struct platform_data_t tfm_peripheral_shield0_i2c = { 145 SBCon_I2C_SHIELD0_BASE_S, 146 SBCon_I2C_SHIELD0_BASE_S + 0xFFF, 147 PPC_SP_PERIPH_EXP1, 148 SBCon_I2C_SHIELD0_PERIPH_PPCEXP1_POS_MASK 149 }; 150 151 struct platform_data_t tfm_peripheral_shield1_i2c = { 152 SBCon_I2C_SHIELD1_BASE_S, 153 SBCon_I2C_SHIELD1_BASE_S + 0xFFF, 154 PPC_SP_PERIPH_EXP1, 155 SBCon_I2C_SHIELD1_PERIPH_PPCEXP1_POS_MASK 156 }; 157 158 struct platform_data_t tfm_peripheral_ddr4_eeprom_i2c = { 159 FPGA_DDR4_EEPROM_BASE_S, 160 FPGA_DDR4_EEPROM_BASE_S + 0xFFF, 161 PPC_SP_PERIPH_EXP1, 162 FPGA_SBCon_I2C_PERIPH_PPCEXP1_POS_MASK 163 }; 164 165 struct platform_data_t tfm_peripheral_fpga_scc = { 166 FPGA_SCC_BASE_S, 167 FPGA_SCC_BASE_S + 0xFFF, 168 PPC_SP_PERIPH_EXP2, 169 FPGA_SCC_PERIPH_PPCEXP2_POS_MASK 170 }; 171 172 struct platform_data_t tfm_peripheral_fpga_i2s = { 173 FPGA_I2S_BASE_S, 174 FPGA_I2S_BASE_S + 0xFFF, 175 PPC_SP_PERIPH_EXP2, 176 FPGA_I2S_PERIPH_PPCEXP2_POS_MASK 177 }; 178 179 struct platform_data_t tfm_peripheral_fpga_io = { 180 FPGA_IO_BASE_S, 181 FPGA_IO_BASE_S + 0xFFF, 182 PPC_SP_PERIPH_EXP2, 183 FPGA_IO_PERIPH_PPCEXP2_POS_MASK 184 }; 185 186 struct platform_data_t tfm_peripheral_std_uart = { 187 UART0_BASE_NS, 188 UART0_BASE_NS + 0xFFF, 189 PPC_SP_DO_NOT_CONFIGURE, 190 -1 191 }; 192 193 struct platform_data_t tfm_peripheral_uart1 = { 194 UART1_BASE_S, 195 UART1_BASE_S + 0xFFF, 196 PPC_SP_PERIPH_EXP2, 197 UART1_PERIPH_PPCEXP2_POS_MASK 198 }; 199 200 struct platform_data_t tfm_peripheral_uart2 = { 201 UART2_BASE_S, 202 UART2_BASE_S + 0xFFF, 203 PPC_SP_PERIPH_EXP2, 204 UART2_PERIPH_PPCEXP2_POS_MASK 205 }; 206 207 struct platform_data_t tfm_peripheral_uart3 = { 208 UART3_BASE_S, 209 UART3_BASE_S + 0xFFF, 210 PPC_SP_PERIPH_EXP2, 211 UART3_PERIPH_PPCEXP2_POS_MASK 212 }; 213 214 struct platform_data_t tfm_peripheral_uart4 = { 215 UART4_BASE_S, 216 UART4_BASE_S + 0xFFF, 217 PPC_SP_PERIPH_EXP2, 218 UART4_PERIPH_PPCEXP2_POS_MASK 219 }; 220 221 struct platform_data_t tfm_peripheral_uart5 = { 222 UART5_BASE_S, 223 UART5_BASE_S + 0xFFF, 224 PPC_SP_PERIPH_EXP2, 225 UART5_PERIPH_PPCEXP2_POS_MASK 226 }; 227 228 struct platform_data_t tfm_peripheral_clcd = { 229 CLCD_Config_Reg_BASE_S, 230 CLCD_Config_Reg_BASE_S + 0xFFF, 231 PPC_SP_PERIPH_EXP2, 232 CLCD_PERIPH_PPCEXP2_POS_MASK 233 }; 234 235 struct platform_data_t tfm_peripheral_rtc = { 236 RTC_BASE_S, 237 RTC_BASE_S + 0xFFF, 238 PPC_SP_PERIPH_EXP2, 239 RTC_PERIPH_PPCEXP2_POS_MASK 240 }; 241
