1 /*
2  * Copyright  2019 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "tfa2_dev.h"
9 
10 /*
11  * TODO can factory_trimmer for tfa9892 done after optimal settings?
12  */
13 
tfa9894_init(struct tfa2_device * tfa)14 static int tfa9894_init(struct tfa2_device *tfa)
15 {
16     int rc = 0;
17 
18     if (tfa->in_use == 0)
19         return -ENOENT;
20 
21     /* Unlock keys to write settings */
22     tfa2_i2c_hap_key2(tfa->i2c, 0);
23 
24     /* The optimal settings */
25     if (tfa->rev == 0x1a94)
26     {
27         /* V14 */
28         /* ----- generated code start ----- */
29         tfa2_i2c_write_reg(tfa->i2c, 0x00, 0xa245); // POR=0x8245
30         tfa2_i2c_write_reg(tfa->i2c, 0x01, 0x15da); // POR=0x11ca
31         tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x5288); // POR=0x55c8
32         tfa2_i2c_write_reg(tfa->i2c, 0x52, 0xbe17); // POR=0xb617
33         tfa2_i2c_write_reg(tfa->i2c, 0x53, 0x0dbe); // POR=0x0d9e
34         tfa2_i2c_write_reg(tfa->i2c, 0x56, 0x05c3); // POR=0x07c3
35         tfa2_i2c_write_reg(tfa->i2c, 0x57, 0x0344); // POR=0x0366
36         tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0032); // POR=0x0073
37         tfa2_i2c_write_reg(tfa->i2c, 0x71, 0x00cf); // POR=0x018d
38         tfa2_i2c_write_reg(tfa->i2c, 0x72, 0x34a9); // POR=0x44e8
39         tfa2_i2c_write_reg(tfa->i2c, 0x73, 0x38c8); // POR=0x3806
40         tfa2_i2c_write_reg(tfa->i2c, 0x76, 0x0067); // POR=0x0065
41         tfa2_i2c_write_reg(tfa->i2c, 0x80, 0x0000); // POR=0x0003
42         tfa2_i2c_write_reg(tfa->i2c, 0x81, 0x5799); // POR=0x561a
43         tfa2_i2c_write_reg(tfa->i2c, 0x82, 0x0104); // POR=0x0044
44         /* ----- generated code end ----- */
45     }
46     else if ((tfa->rev == 0x2a94) || (tfa->rev == 0x3a94))
47     {
48         /* V10 */
49         /* ----- generated code start ----- */
50         tfa2_i2c_write_reg(tfa->i2c, 0x00, 0xa245); // POR=0x8245
51         tfa2_i2c_write_reg(tfa->i2c, 0x01, 0x15da); // POR=0x11ca
52         tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x51e8); // POR=0x55c8
53         tfa2_i2c_write_reg(tfa->i2c, 0x52, 0xbe17); // POR=0xb617
54         tfa2_i2c_write_reg(tfa->i2c, 0x53, 0x0dbe); // POR=0x0d9e k2
55         tfa2_i2c_write_reg(tfa->i2c, 0x57, 0x0344); // POR=0x0366
56         tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0033); // POR=0x0073
57         tfa2_i2c_write_reg(tfa->i2c, 0x71, 0x6ecf); // POR=0x6f8d
58         tfa2_i2c_write_reg(tfa->i2c, 0x72, 0x34a9); // POR=0x44e8
59         tfa2_i2c_write_reg(tfa->i2c, 0x73, 0x38c8); // POR=0x3806
60         tfa2_i2c_write_reg(tfa->i2c, 0x76, 0x0067); // POR=0x0065 k2
61         tfa2_i2c_write_reg(tfa->i2c, 0x80, 0x0000); // POR=0x0003 k2
62         tfa2_i2c_write_reg(tfa->i2c, 0x81, 0x5799); // POR=0x561a k2
63         tfa2_i2c_write_reg(tfa->i2c, 0x82, 0x0104); // POR=0x0044 k2
64         /* ----- generated code end   ----- */
65     }
66     else
67     {
68         dev_err(&tfa->i2c->dev, "%s: unknown device revision: 0x%02x\n", __FUNCTION__, tfa->rev);
69         rc = -EINVAL;
70     }
71 
72     /* re-lock */
73     tfa2_i2c_hap_key2(tfa->i2c, 1);
74 
75     return rc;
76 }
tfa9894_tfa_mtp_write_wrapper(struct tfa2_device * tfa,uint16_t addr,uint16_t mtp_new,int (* mtp_write)(struct tfa2_device *,uint16_t,uint16_t))77 int tfa9894_tfa_mtp_write_wrapper(struct tfa2_device *tfa,
78                                   uint16_t addr,
79                                   uint16_t mtp_new,
80                                   int (*mtp_write)(struct tfa2_device *, uint16_t, uint16_t))
81 {
82     int rc;
83     int save_bit1, save_bit2;
84     // int save_state;
85     int lpm1mode;
86     /********************** mtp setup ************************************/
87     /*
88      * disable_auto_sel_refclk and FAIMVBGOVRRL need to be set to allow
89      * MTP writes in init_cf state
90      */
91     /* { 0x470, "disable_auto_sel_refclk"},    Automatic PLL reference clock selection for cold start, */
92     save_bit1 = tfa2_i2c_read_bf(tfa->i2c, 0x470);
93     /*  { 0x1f0, "FAIMVBGOVRRL"},     Overrule the enabling of VBG for faim erase/write access, */
94     save_bit2 = tfa2_i2c_read_bf(tfa->i2c, 0x1f0);
95 
96     lpm1mode = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_lpm1mode);
97 
98     /* disable low power mode */
99     tfa2_i2c_write_bf(tfa->i2c, tfa->bf_lpm1mode, 1);
100 
101     tfa2_i2c_unlock(tfa->i2c); /* key1 */
102     tfa2_i2c_write_bf(tfa->i2c, 0x470, 1);
103     tfa2_i2c_write_bf(tfa->i2c, 0x1f0, 1);
104 
105     /* do the write */
106     rc = (*mtp_write)(tfa, addr, mtp_new);
107     if (rc < 0)
108     {
109         dev_err(&tfa->i2c->dev, "error writing MTP: 0x%02x 0x%04x\n", addr, mtp_new);
110     }
111     /* unlock can't be done anymore tfa2_i2c_lock() open key1 */
112     /* restore */
113     tfa2_i2c_write_bf(tfa->i2c, 0x470, save_bit1);
114     tfa2_i2c_write_bf(tfa->i2c, 0x1f0, save_bit2);
115     tfa2_i2c_write_bf(tfa->i2c, tfa->bf_lpm1mode, lpm1mode);
116 
117     return rc;
118 }
119 
tfa9872_init(struct tfa2_device * tfa)120 static int tfa9872_init(struct tfa2_device *tfa)
121 {
122     const uint16_t bypass_ovp = 0xb020;
123     int rc                    = 0;
124 
125     if (tfa->in_use == 0)
126         return -ENOENT;
127 
128     /* Unlock keys to write settings */
129     tfa2_i2c_unlock(tfa->i2c); /* key1 */
130     tfa2_i2c_hap_key2(tfa->i2c, 0);
131 
132     switch (tfa->rev)
133     {
134         case 0x1a72:
135         case 0x2a72:
136             /* ----- generated code start ----- */
137             /* -----  version 26 ----- */
138             tfa2_i2c_write_reg(tfa->i2c, 0x00, 0x1801); // POR=0x0001
139             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x2dc8); // POR=0x2028
140             tfa2_i2c_write_reg(tfa->i2c, 0x20, 0x0890); // POR=0x2890
141             tfa2_i2c_write_reg(tfa->i2c, 0x22, 0x043c); // POR=0x045c
142             tfa2_i2c_write_reg(tfa->i2c, 0x51, 0x0000); // POR=0x0080
143             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x1a1c); // POR=0x7ae8
144             tfa2_i2c_write_reg(tfa->i2c, 0x58, 0x161c); // POR=0x101c
145             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0198); // POR=0x0000
146             tfa2_i2c_write_reg(tfa->i2c, 0x65, 0x0a8b); // POR=0x0a9a
147             tfa2_i2c_write_reg(tfa->i2c, 0x70, 0x07f5); // POR=0x06e6
148             tfa2_i2c_write_reg(tfa->i2c, 0x74, 0xcc84); // POR=0xd823
149             tfa2_i2c_write_reg(tfa->i2c, 0x82, 0x01ed); // POR=0x000d
150             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x0014); // POR=0x0013
151             tfa2_i2c_write_reg(tfa->i2c, 0x84, 0x0021); // POR=0x0020
152             tfa2_i2c_write_reg(tfa->i2c, 0x85, 0x0001); // POR=0x0003
153             /* ----- generated code end   ----- */
154             break;
155         case 0x1b72:
156         case 0x2b72:
157         case 0x3b72:
158             /* ----- generated code start ----- */
159             /*  -----  version 25.00 ----- */
160             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x2dc8); // POR=0x2828
161             tfa2_i2c_write_reg(tfa->i2c, 0x20, 0x0890); // POR=0x2890
162             tfa2_i2c_write_reg(tfa->i2c, 0x22, 0x043c); // POR=0x045c
163             tfa2_i2c_write_reg(tfa->i2c, 0x23, 0x0001); // POR=0x0003
164             tfa2_i2c_write_reg(tfa->i2c, 0x51, 0x0000); // POR=0x0080
165             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x5a1c); // POR=0x7a08
166             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0198); // POR=0x0000
167             tfa2_i2c_write_reg(tfa->i2c, 0x63, 0x0a9a); // POR=0x0a93
168             tfa2_i2c_write_reg(tfa->i2c, 0x65, 0x0a82); // POR=0x0a8d
169             tfa2_i2c_write_reg(tfa->i2c, 0x6f, 0x01e3); // POR=0x02e4
170             tfa2_i2c_write_reg(tfa->i2c, 0x70, 0x06fd); // POR=0x06e6
171             tfa2_i2c_write_reg(tfa->i2c, 0x71, 0x307e); // POR=0x207e
172             tfa2_i2c_write_reg(tfa->i2c, 0x74, 0xcc84); // POR=0xd913
173             tfa2_i2c_write_reg(tfa->i2c, 0x75, 0x1132); // POR=0x118a
174             tfa2_i2c_write_reg(tfa->i2c, 0x82, 0x01ed); // POR=0x000d
175             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x001a); // POR=0x0013
176             /* ----- generated code end   ----- */
177             break;
178         default:
179             dev_err(&tfa->i2c->dev, "%s: unknown device revision: 0x%02x\n", __FUNCTION__, tfa->rev);
180             rc = -EINVAL;
181             break;
182     }
183 
184     if (rc == 0)
185     {
186         /* Bypass OVP (bypass_ovp=1): PLMA5258 */
187         rc = tfa2_i2c_write_bf(tfa->i2c, bypass_ovp, 1);
188     }
189 
190     /* re-lock can't be done anymore tfa2_i2c_lock() open key1 */
191 
192     return rc;
193 }
194 
tfa9873_init(struct tfa2_device * tfa)195 static int tfa9873_init(struct tfa2_device *tfa)
196 {
197     int rc = 0;
198 
199     if (tfa->in_use == 0)
200         return -ENOENT;
201 
202     /* Unlock keys to write settings */
203     tfa2_i2c_unlock(tfa->i2c); /* key1 */
204     tfa2_i2c_hap_key2(tfa->i2c, 0);
205 
206     switch (tfa->rev)
207     {
208         case 0x0a73: /* Initial revision ID */
209             /* ----- generated code start ----- */
210             /* -----  version 22 ----- */
211             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x0628); // POR=0x0008
212             tfa2_i2c_write_reg(tfa->i2c, 0x4c, 0x00e9); // POR=0x00ff
213             tfa2_i2c_write_reg(tfa->i2c, 0x56, 0x0011); // POR=0x0019
214             tfa2_i2c_write_reg(tfa->i2c, 0x5f, 0x0180); // POR=0x0100
215             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0183); // POR=0x0a82
216             tfa2_i2c_write_reg(tfa->i2c, 0x63, 0x055a); // POR=0x0a9a
217             tfa2_i2c_write_reg(tfa->i2c, 0x65, 0x0542); // POR=0x0a82
218             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x009a); // POR=0x0799
219             tfa2_i2c_write_reg(tfa->i2c, 0x84, 0x0211); // POR=0x0011
220             tfa2_i2c_write_reg(tfa->i2c, 0x8c, 0x0210); // POR=0x0010
221             /* ----- generated code end   ----- */
222             break;
223         case 0x1a73:
224             break;
225         default:
226             dev_err(&tfa->i2c->dev, "%s: unknown device revision: 0x%02x\n", __FUNCTION__, tfa->rev);
227             rc = -EINVAL;
228             break;
229     }
230 
231     /* re-lock can't be done anymore tfa2_i2c_lock() open key1 */
232 
233     return rc;
234 }
235 
tfa9874_init(struct tfa2_device * tfa)236 static int tfa9874_init(struct tfa2_device *tfa)
237 {
238     int rc = 0;
239 
240     if (tfa->in_use == 0)
241         return -ENOENT;
242 
243     /* Unlock keys to write settings */
244     tfa2_i2c_unlock(tfa->i2c); /* key1 */
245     tfa2_i2c_hap_key2(tfa->i2c, 0);
246 
247     switch (tfa->rev)
248     {
249         case 0x0a74: /* Initial revision ID */
250             /* ----- generated code start ----- */
251             /* V25 */
252             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x22a8); // POR=0x25c8
253             tfa2_i2c_write_reg(tfa->i2c, 0x51, 0x0020); // POR=0x0000
254             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x57dc); // POR=0x56dc
255             tfa2_i2c_write_reg(tfa->i2c, 0x58, 0x16a4); // POR=0x1614
256             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0110); // POR=0x0198
257             tfa2_i2c_write_reg(tfa->i2c, 0x66, 0x0701); // POR=0x0700
258             tfa2_i2c_write_reg(tfa->i2c, 0x6f, 0x00a3); // POR=0x01a3
259             tfa2_i2c_write_reg(tfa->i2c, 0x70, 0x07f8); // POR=0x06f8
260             tfa2_i2c_write_reg(tfa->i2c, 0x73, 0x0007); // POR=0x0005
261             tfa2_i2c_write_reg(tfa->i2c, 0x74, 0x5068); // POR=0xcc80
262             tfa2_i2c_write_reg(tfa->i2c, 0x75, 0x0d28); // POR=0x1138
263             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x0594); // POR=0x061a
264             tfa2_i2c_write_reg(tfa->i2c, 0x84, 0x0001); // POR=0x0021
265             tfa2_i2c_write_reg(tfa->i2c, 0x85, 0x0001); // POR=0x0003
266             tfa2_i2c_write_reg(tfa->i2c, 0x88, 0x0000); // POR=0x0002
267             tfa2_i2c_write_reg(tfa->i2c, 0xc4, 0x2001); // POR=0x0001
268             /* ----- generated code end   ----- */
269             break;
270         case 0x0b74:
271             /* ----- generated code start ----- */
272             /* V1.6 */
273             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x22a8); // POR=0x25c8
274             tfa2_i2c_write_reg(tfa->i2c, 0x51, 0x0020); // POR=0x0000
275             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x57dc); // POR=0x56dc
276             tfa2_i2c_write_reg(tfa->i2c, 0x58, 0x16a4); // POR=0x1614
277             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0110); // POR=0x0198
278             tfa2_i2c_write_reg(tfa->i2c, 0x66, 0x0701); // POR=0x0700
279             tfa2_i2c_write_reg(tfa->i2c, 0x6f, 0x00a3); // POR=0x01a3
280             tfa2_i2c_write_reg(tfa->i2c, 0x70, 0x07f8); // POR=0x06f8
281             tfa2_i2c_write_reg(tfa->i2c, 0x73, 0x0047); // POR=0x0045
282             tfa2_i2c_write_reg(tfa->i2c, 0x74, 0x5068); // POR=0xcc80
283             tfa2_i2c_write_reg(tfa->i2c, 0x75, 0x0d28); // POR=0x1138
284             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x0595); // POR=0x061a
285             tfa2_i2c_write_reg(tfa->i2c, 0x84, 0x0001); // POR=0x0021
286             tfa2_i2c_write_reg(tfa->i2c, 0x85, 0x0001); // POR=0x0003
287             tfa2_i2c_write_reg(tfa->i2c, 0x88, 0x0000); // POR=0x0002
288             tfa2_i2c_write_reg(tfa->i2c, 0xc4, 0x2001); // POR=0x0001
289             /* ----- generated code end   ----- */
290             break;
291         case 0x0c74:
292             /* ----- generated code start ----- */
293             /* V1.16 */
294             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x22c8); // POR=0x25c8
295             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x57dc); // POR=0x56dc
296             tfa2_i2c_write_reg(tfa->i2c, 0x53, 0x003e); // POR=0x001e
297             tfa2_i2c_write_reg(tfa->i2c, 0x56, 0x0400); // POR=0x0600
298             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0110); // POR=0x0198
299             tfa2_i2c_write_reg(tfa->i2c, 0x6f, 0x00a5); // POR=0x01a3
300             tfa2_i2c_write_reg(tfa->i2c, 0x70, 0x07f8); // POR=0x06f8
301             tfa2_i2c_write_reg(tfa->i2c, 0x73, 0x0047); // POR=0x0045
302             tfa2_i2c_write_reg(tfa->i2c, 0x74, 0x5098); // POR=0xcc80
303             tfa2_i2c_write_reg(tfa->i2c, 0x75, 0x8d28); // POR=0x1138
304             tfa2_i2c_write_reg(tfa->i2c, 0x80, 0x0000); // POR=0x0003
305             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x0799); // POR=0x061a
306             tfa2_i2c_write_reg(tfa->i2c, 0x84, 0x0081); // POR=0x0021
307             /* ----- generated code end   ----- */
308             break;
309         default:
310             dev_err(&tfa->i2c->dev, "%s: unknown device revision: 0x%02x\n", __FUNCTION__, tfa->rev);
311             rc = -EINVAL;
312             break;
313     }
314 
315     /* re-lock can't be done anymore tfa2_i2c_lock() open key1 */
316 
317     return rc;
318 }
319 
tfa9878_init(struct tfa2_device * tfa)320 static int tfa9878_init(struct tfa2_device *tfa)
321 {
322     int rc = 0;
323 
324     if (tfa->in_use == 0)
325         return -ENOENT;
326 
327     /* Unlock keys to write settings */
328     tfa2_i2c_unlock(tfa->i2c); /* key1 */
329     tfa2_i2c_hap_key2(tfa->i2c, 0);
330 
331     switch (tfa->rev)
332     {
333         case 0x0a78:
334             /* ----- generated code start ----- */
335             /* -----  version 28 ----- */
336             tfa2_i2c_write_reg(tfa->i2c, 0x01, 0x2e18); // POR=0x2e88
337             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x0628); // POR=0x0008
338             tfa2_i2c_write_reg(tfa->i2c, 0x04, 0x0240); // POR=0x0340
339             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x587c); // POR=0x57dc
340             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0183); // POR=0x0a82
341             tfa2_i2c_write_reg(tfa->i2c, 0x63, 0x055a); // POR=0x0a9a
342             tfa2_i2c_write_reg(tfa->i2c, 0x65, 0x0542); // POR=0x0a82
343             tfa2_i2c_write_reg(tfa->i2c, 0x71, 0x303e); // POR=0x307e
344             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x009a); // POR=0x0799
345             /* ----- generated code end   ----- */
346             break;
347         case 0x1a78:
348             /* ----- generated code start ----- */
349             /* -----  version 4 ----- */
350             tfa2_i2c_write_reg(tfa->i2c, 0x01, 0x2e18); // POR=0x2e88
351             tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x0628); // POR=0x0008
352             tfa2_i2c_write_reg(tfa->i2c, 0x04, 0x0240); // POR=0x0340
353             tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x587c); // POR=0x57dc
354             tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x0183); // POR=0x0a82
355             tfa2_i2c_write_reg(tfa->i2c, 0x63, 0x055a); // POR=0x0a9a
356             tfa2_i2c_write_reg(tfa->i2c, 0x65, 0x0542); // POR=0x0a82
357             tfa2_i2c_write_reg(tfa->i2c, 0x71, 0x303e); // POR=0x307e
358             tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x009a); // POR=0x0799
359             /* ----- generated code end   ----- */
360             break;
361         default:
362             dev_err(&tfa->i2c->dev, "%s: unknown device revision: 0x%02x\n", __FUNCTION__, tfa->rev);
363             rc = -EINVAL;
364             break;
365     }
366 
367     /* re-lock can't be done anymore tfa2_i2c_lock() open key1 */
368 
369     return rc;
370 }
371 
372 /***********************************************************************************/
373 /* TFA9912                                                                         */
374 /***********************************************************************************/
375 
tfa9912_init(struct tfa2_device * tfa)376 static int tfa9912_init(struct tfa2_device *tfa)
377 {
378     if (tfa->in_use == 0)
379         return -ENOENT;
380 
381     /* Unlock keys to write settings */
382     tfa2_i2c_unlock(tfa->i2c); /* key1 */
383     tfa2_i2c_hap_key2(tfa->i2c, 0);
384 
385     /* The optimal settings */
386     if (tfa->rev == 0x1a13)
387     {
388         /* ----- generated code start ----- */
389         /* -----  version 1.41  ----- */
390         tfa2_i2c_write_reg(tfa->i2c, 0x00, 0x0255); // POR=0x0245
391         tfa2_i2c_write_reg(tfa->i2c, 0x01, 0x838a); // POR=0x83ca
392         tfa2_i2c_write_reg(tfa->i2c, 0x02, 0x2dc8); // POR=0x2828
393         tfa2_i2c_write_reg(tfa->i2c, 0x05, 0x762a); // POR=0x766a
394         tfa2_i2c_write_reg(tfa->i2c, 0x22, 0x543c); // POR=0x545c
395         tfa2_i2c_write_reg(tfa->i2c, 0x26, 0x0100); // POR=0x0010
396         tfa2_i2c_write_reg(tfa->i2c, 0x51, 0x0000); // POR=0x0080
397         tfa2_i2c_write_reg(tfa->i2c, 0x52, 0x551c); // POR=0x1afc
398         tfa2_i2c_write_reg(tfa->i2c, 0x53, 0x003e); // POR=0x001e
399         tfa2_i2c_write_reg(tfa->i2c, 0x61, 0x000c); // POR=0x0018
400         tfa2_i2c_write_reg(tfa->i2c, 0x63, 0x0a96); // POR=0x0a9a
401         tfa2_i2c_write_reg(tfa->i2c, 0x65, 0x0a82); // POR=0x0a8b
402         tfa2_i2c_write_reg(tfa->i2c, 0x66, 0x0701); // POR=0x0700
403         tfa2_i2c_write_reg(tfa->i2c, 0x6c, 0x00d5); // POR=0x02d5
404         tfa2_i2c_write_reg(tfa->i2c, 0x70, 0x26f8); // POR=0x06e0
405         tfa2_i2c_write_reg(tfa->i2c, 0x71, 0x3074); // POR=0x2074
406         tfa2_i2c_write_reg(tfa->i2c, 0x75, 0x4484); // POR=0x4585
407         tfa2_i2c_write_reg(tfa->i2c, 0x76, 0x72ea); // POR=0x54a2
408         tfa2_i2c_write_reg(tfa->i2c, 0x83, 0x0716); // POR=0x0617
409         tfa2_i2c_write_reg(tfa->i2c, 0x89, 0x0013); // POR=0x0014
410         tfa2_i2c_write_reg(tfa->i2c, 0xb0, 0x4c08); // POR=0x4c00
411         tfa2_i2c_write_reg(tfa->i2c, 0xc6, 0x004e); // POR=0x000e /* PLMA5539: Please make sure bit 6 is always on! */
412         /* ----- generated code end   ----- */
413 
414         /* PLMA5505: default MTP key open makes vulnerable to MTP corruption */
415         tfa2_i2c_write_bf(tfa->i2c, tfa->bf_openmtp, 0);
416     }
417     else
418     {
419         pr_info("Warning: Optimal settings not found for device with revid = 0x%x \n", tfa->rev);
420         return -EINVAL;
421     }
422 
423     return 0;
424 }
425 
426 #define TFA9912_BF_DCMCCAPI 0xf020
427 #define TFA9912_BF_DCMCC    0x7033
428 #define TFA9912_BF_DCMCCCL  0xf042
429 #define TFA9912_BF_DCMCCSB  0xf030
430 
tfa9912_factory_trimmer(struct tfa2_device * tfa)431 static int tfa9912_factory_trimmer(struct tfa2_device *tfa)
432 {
433     int currentValue, delta;
434     int rc = 0;
435 
436     /* Factory trimming for the Boost converter */
437     /* check if there is a correction needed */
438     rc = tfa2_i2c_read_bf(tfa->i2c, TFA9912_BF_DCMCCAPI);
439     if (rc < 0)
440         return rc;
441 
442     if (rc)
443     {
444         /* Get currentvalue of DCMCC and the Delta value */
445         rc = tfa2_i2c_read_bf(tfa->i2c, TFA9912_BF_DCMCC);
446         if (rc < 0)
447             return rc;
448         currentValue = rc;
449         rc           = tfa2_i2c_read_bf(tfa->i2c, TFA9912_BF_DCMCCCL);
450         if (rc < 0)
451             return rc;
452         delta = rc;
453 
454         /* check the sign bit (+/-) */
455         rc = tfa2_i2c_read_bf(tfa->i2c, TFA9912_BF_DCMCCSB);
456         if (rc < 0)
457             return rc;
458         if (rc == 0)
459         {
460             /* Do not exceed the maximum value of 15 */
461             if (currentValue + delta < 15)
462             {
463                 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9912_BF_DCMCC, currentValue + delta);
464                 if (tfa->verbose)
465                     pr_debug("Max coil current is set to: %d \n", currentValue + delta);
466             }
467             else
468             {
469                 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9912_BF_DCMCC, 15);
470                 if (tfa->verbose)
471                     pr_debug("Max coil current is set to: 15 \n");
472             }
473         }
474         else if (rc == 1)
475         {
476             /* Do not exceed the minimum value of 0 */
477             if (currentValue - delta > 0)
478             {
479                 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9912_BF_DCMCC, currentValue - delta);
480                 if (tfa->verbose)
481                     pr_debug("Max coil current is set to: %d \n", currentValue - delta);
482             }
483             else
484             {
485                 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9912_BF_DCMCC, 0);
486                 if (tfa->verbose)
487                     pr_debug("Max coil current is set to: 0 \n");
488             }
489         }
490     }
491 
492     return rc;
493 }
494 
495 /* Maksimum value for combination of boost_voltage and vout calibration offset (see PLMA5322, PLMA5528). */
496 #define TFA9912_BF_DCVOF         0x7635
497 #define TFA9912_BF_DCVOS         0x7695
498 #define TFA9912_VBOOST_MAX       57
499 #define TFA9912_CALIBR_BOOST_MAX 63
500 #define TFA9912_DCDCCNT6_REG     (TFA9912_BF_DCVOF >> 8)
501 #define TFA9912_CALIBR_REG       0xf1
502 
tfa9912_vboost_fixup(struct tfa2_device * tfa)503 static int tfa9912_vboost_fixup(struct tfa2_device *tfa)
504 {
505     int rc;
506     int cal_offset;
507     int dcvof, dcvos;
508 
509     /* Get current calibr_vout_offset, this register is not supported by bitfields */
510     rc = tfa2_i2c_read_reg(tfa->i2c, TFA9912_CALIBR_REG);
511     if (rc < 0)
512         return rc;
513     cal_offset = (rc & 0x001f);
514 
515     /* Get current boost_volatage values */
516     rc = tfa2_i2c_read_bf(tfa->i2c, TFA9912_BF_DCVOF);
517     if (rc < 0)
518         return rc;
519     dcvof = rc;
520     rc    = tfa2_i2c_read_bf(tfa->i2c, TFA9912_BF_DCVOS);
521     if (rc < 0)
522         return rc;
523     dcvos = rc;
524 
525     /* Check boost voltages, limit them to TFA9912_VBOOST_MAX */
526     if (dcvof > TFA9912_VBOOST_MAX)
527     {
528         dev_warn(&tfa->i2c->dev, "DCVOF exceeding maximum (57), adjusting it to maximum.\n");
529         dcvof = TFA9912_VBOOST_MAX;
530     }
531 
532     if (dcvos > TFA9912_VBOOST_MAX)
533     {
534         dev_warn(&tfa->i2c->dev, "DCVOS exceeding maximum (57), adjusting it to maximum.\n");
535         dcvos = TFA9912_VBOOST_MAX;
536     }
537 
538     /* Recalculate values, max for the sum is TFA9912_CALIBR_BOOST_MAX */
539     if (dcvof + cal_offset > TFA9912_CALIBR_BOOST_MAX)
540     {
541         dev_dbg(&tfa->i2c->dev, "Recalculate DCVOF based on calibr_vout_offset.\n");
542         dcvof = TFA9912_CALIBR_BOOST_MAX - cal_offset;
543     }
544 
545     if (dcvos + cal_offset > TFA9912_CALIBR_BOOST_MAX)
546     {
547         dev_dbg(&tfa->i2c->dev, "Recalculate DCVOS based on calibr_vout_offset.\n");
548         dcvos = TFA9912_CALIBR_BOOST_MAX - cal_offset;
549     }
550 
551     rc = tfa2_i2c_write_bf(tfa->i2c, TFA9912_BF_DCVOF, dcvof);
552     if (rc < 0)
553         return rc;
554     rc = tfa2_i2c_write_bf(tfa->i2c, TFA9912_BF_DCVOS, dcvos);
555     return rc;
556 }
557 
tfa2_init_mtp_write_wrapper(struct tfa2_device * tfa,uint16_t addr,uint16_t mtp_new,int (* mtp_write)(struct tfa2_device *,uint16_t,uint16_t))558 int tfa2_init_mtp_write_wrapper(struct tfa2_device *tfa,
559                                 uint16_t addr,
560                                 uint16_t mtp_new,
561                                 int (*mtp_write)(struct tfa2_device *, uint16_t, uint16_t))
562 {
563     int rc;
564     int lpm1mode, faimvbgovrrl, bf_faimvbgovrrl = 0;
565 
566     /********************** mtp setup ************************************/
567 
568     /*
569      * FAIMVBGOVRRL needs to be set to allow MTP writes in init_cf state.
570      *  (Overrule the enabling of VBG for faim erase/write access)
571      */
572     if ((tfa->rev & 0xff) == 0x13)
573     {
574         bf_faimvbgovrrl = 0x5f0;
575     }
576     else if ((tfa->rev & 0xff) == 0x94)
577     {
578         bf_faimvbgovrrl = 0x1f0;
579     }
580 
581     if (bf_faimvbgovrrl)
582         faimvbgovrrl = tfa2_i2c_read_bf(tfa->i2c, bf_faimvbgovrrl);
583 
584     lpm1mode = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_lpm1mode);
585 
586     /* disable low power mode */
587     tfa2_i2c_write_bf(tfa->i2c, tfa->bf_lpm1mode, 1);
588 
589     tfa2_i2c_unlock(tfa->i2c); /* key1 */
590 
591     if (bf_faimvbgovrrl)
592         tfa2_i2c_write_bf(tfa->i2c, bf_faimvbgovrrl, 1);
593 
594     /* do the write */
595     rc = (*mtp_write)(tfa, addr, mtp_new);
596     if (rc < 0)
597     {
598         dev_err(&tfa->i2c->dev, "error writing MTP: 0x%02x 0x%04x\n", addr, mtp_new);
599     }
600 
601     /* unlock can't be done anymore tfa2_i2c_lock() open key1 */
602     /* restore */
603     if (bf_faimvbgovrrl)
604         tfa2_i2c_write_bf(tfa->i2c, bf_faimvbgovrrl, faimvbgovrrl);
605 
606     tfa2_i2c_write_bf(tfa->i2c, tfa->bf_lpm1mode, lpm1mode);
607 
608     return rc;
609 }
610 
611 /* called during cold start before powering up the device */
tfa2_init_fix_powerup(struct tfa2_device * tfa)612 int tfa2_init_fix_powerup(struct tfa2_device *tfa)
613 {
614     int rc = 0;
615 
616     /* only for tfa9912 */
617     if ((tfa->rev & 0xff) == 0x13)
618     {
619         /* overwrite DCMCC if needed */
620         rc = tfa9912_factory_trimmer(tfa);
621         if (rc < 0)
622             return rc;
623 
624         /* overwrite DCVOS and DCVOF if needed */
625         rc = tfa9912_vboost_fixup(tfa);
626     }
627 
628     return rc;
629 }
630 
631 /* called during warm profile switch */
tfa2_init_fix_initcf(struct tfa2_device * tfa)632 int tfa2_init_fix_initcf(struct tfa2_device *tfa)
633 {
634     int rc = 0;
635 
636     /* only for tfa9912 */
637     if ((tfa->rev & 0xff) == 0x13)
638     {
639         /* The status register from which the CF_ACK bits are read is having a
640          * reset signal which is synchronized with the clock which is used by
641          * FaIM SS.
642          * When the FaIM subsystem is disabled, its clock is gated and hence
643          * reset is not released for the status register thereby blocking the
644          * CF ack signal from reading correctly. I2C read is blocked.
645          * Workaround is to toggle enabling FAIM SS just after entering the
646          * INITCF state.
647          * Manager keeps the DSP sub-system in RESET state until it reaches
648          * INITCF state. We need few clock edges after to release the CFSS reset.
649          */
650         tfa2_i2c_write_bf_volatile(tfa->i2c, 0x05c0, 1); /* TFA9912_BF_SSFAIME */
651         tfa2_i2c_write_bf_volatile(tfa->i2c, 0x05c0, 0); /* TFA9912_BF_SSFAIME */
652     }
653 
654     return rc;
655 }
656 
657 /* called before powering down the device */
tfa2_init_fix_powerdown(struct tfa2_device * tfa,int manstate)658 int tfa2_init_fix_powerdown(struct tfa2_device *tfa, int manstate)
659 {
660     int rc = 0;
661 
662     /* only for tfa9912 */
663     if (tfa->rev == 0x1a13 && manstate == 1)
664     {
665         rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 0);
666         if (rc < 0)
667             return rc;
668         rc = tfa2_i2c_write_bf_volatile(tfa->i2c, 0x0691, 2); // TFA9912_BF_STARTUPMODE
669         if (rc < 0)
670             return rc;
671         rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 1);
672         if (rc < 0)
673             return rc;
674         rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 1);
675         if (rc < 0)
676             return rc;
677         rc = tfa2_i2c_write_bf_volatile(tfa->i2c, 0x0691, 0); // TFA9912_BF_STARTUPMODE
678     }
679 
680     return rc;
681 }
682 
683 /* TODO use the getfeatures() for retrieving the features [artf103523]
684 tfa->supportDrc = supportNotSet;*/
tfa2_dev_specific(struct tfa2_device * tfa)685 int tfa2_dev_specific(struct tfa2_device *tfa)
686 {
687     switch (tfa->rev & 0xff)
688     {
689         case 0x94:
690             if ((tfa->rev == 0x2a94) || (tfa->rev == 0x3a94))
691             {
692                 /* bit field overloads */
693                 tfa->bf_manstate = 0x1333;
694             }
695 
696             /* tfa9894 */
697             tfa->tfa_init = tfa9894_init;
698             break;
699         case 0x13:
700             /* tfa9912 */
701             tfa->tfa_init = tfa9912_init;
702             /* bit field overloads */
703             tfa->bf_clks     = 0x1050;
704             tfa->bf_manaoosc = 0x0140;
705             tfa->bf_noclk    = 0x1070;
706             tfa->bf_mtpb     = 0x1060; /* TFA9912_BF_MTPB */
707             tfa->bf_openmtp  = 0x05c0; /* TFA9912_BF_SSFAIME */
708             tfa->bf_swprofil = 0xee0f;
709             tfa->bf_swvstep  = 0xef0f;
710             tfa->bf_lpm1mode = 0x65c0; /* TFA9912_BF_LPM1DIS */
711             tfa->bf_r25c     = 0xf40f;
712 
713             tfa->status_mask[0] = 0x0014; /* UVDS, OTDS */
714             tfa->status_mask[1] = 0x2180; /* SWS, TDMLUTER, CLKS */
715             tfa->status_mask[2] = 0x0000;
716             tfa->status_mask[3] = 0x0100; /* OVDS */
717 
718             tfa->status_err[0] = 0x00e1;
719             tfa->status_err[1] = 0x1f05;
720             tfa->status_err[2] = 0;
721             tfa->status_err[3] = 0x5200;
722             break;
723         case 0x72:
724             /* bit field overloads */
725             tfa->bf_clks     = 0x1050;
726             tfa->bf_manaoosc = 0x0140;
727             tfa->bf_noclk    = 0x1070;
728             tfa->bf_mtpb     = 0x1060;
729             tfa->bf_swprofil = 0xee0f;
730             tfa->bf_swvstep  = 0xef0f;
731             tfa->bf_openmtp  = 0x05c0; /* TFA9872_BF_SSFAIME */
732             tfa->bf_lpm1mode = 0x65c0; /* TFA9872_BF_LPM1DIS */
733 
734             tfa->status_mask[0] = 0x043c; /* SWS, CLKS, UVDS, OVDS, OTDS */
735             tfa->status_mask[1] = 0x0100; /* TDMLUTER */
736             tfa->status_mask[2] = 0x0000;
737             tfa->status_mask[3] = 0x0000;
738 
739             tfa->status_err[0] = 0x8bc1;
740             tfa->status_err[1] = 0x3f8b;
741             tfa->status_err[2] = 0;
742             tfa->status_err[3] = 0;
743 
744             /* tfa9872 */
745             tfa->tfa_init         = tfa9872_init;
746             tfa->is_probus_device = 1;
747             break;
748         case 0x74:
749             /* bit field overloads */
750             tfa->bf_clks     = 0x1170;
751             tfa->bf_manaoosc = 0x0140;
752             tfa->bf_noclk    = 0x1070;
753             tfa->bf_mtpb     = 0x11c0;
754             tfa->bf_swprofil = 0xee0f;
755             tfa->bf_swvstep  = 0xef0f;
756             tfa->bf_lpm1mode = 0x64e1;
757 
758             tfa->status_mask[0] = 0x0014; /* UVDS, OTDS */
759             tfa->status_mask[1] = 0x2180; /* SWS, TDMLUTER, CLKS */
760             tfa->status_mask[2] = 0x0000;
761             tfa->status_mask[3] = 0x0100; /* OVDS */
762 
763             tfa->status_err[0] = 0x00e1;
764             tfa->status_err[1] = 0x1f05;
765             tfa->status_err[2] = 0;
766             tfa->status_err[3] = 0x5200;
767 
768             /* tfa9874 */
769             tfa->tfa_init         = tfa9874_init;
770             tfa->is_probus_device = 1;
771             break;
772         case 0x78:
773             /* bit field overloads */
774             tfa->bf_lpm1mode = 0x64e1;
775 
776             tfa->status_mask[0] = 0x0054; /* CLKS, UVDS, OTDS */
777             tfa->status_mask[1] = 0x2100; /* SWS, TDMLUTER */
778             tfa->status_mask[2] = 0x0000;
779             tfa->status_mask[3] = 0x0100; /* OVDS */
780 
781             tfa->status_err[0] = 0x00a1;
782             tfa->status_err[1] = 0x1f05;
783             tfa->status_err[2] = 0;
784             tfa->status_err[3] = 0x5200;
785 
786             /* tfa9878 */
787             tfa->tfa_init         = tfa9878_init;
788             tfa->is_probus_device = 1;
789             break;
790         case 0x73:
791             /* bit field overloads */
792             tfa->bf_lpm1mode = 0x64e1;
793 
794             tfa->status_mask[0] = 0x0054; /* CLKS, UVDS, OTDS */
795             tfa->status_mask[1] = 0x2100; /* SWS, TDMLUTER */
796             tfa->status_mask[2] = 0x0000;
797             tfa->status_mask[3] = 0x0100; /* OVDS */
798 
799             tfa->status_err[0] = 0x00a1;
800             tfa->status_err[1] = 0x1f05;
801             tfa->status_err[2] = 0;
802             tfa->status_err[3] = 0x5200;
803 
804             /* tfa9873 */
805             tfa->tfa_init         = tfa9873_init;
806             tfa->is_probus_device = 1;
807             break;
808         case 0x00:
809             /* external DSP */
810             tfa->is_extern_dsp_device = 1;
811             break;
812         default:
813             dev_err(&tfa->i2c->dev, "%s: unknown device type : 0x%02x\n", __FUNCTION__, tfa->rev);
814             return -EINVAL;
815             break;
816     }
817 
818     return 0;
819 }
820