1 /*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #define pr_fmt(fmt) "%s(): " fmt, __FUNCTION__
9
10 #include "tfa2_dev.h"
11 #include "tfa2_haptic.h"
12 #include "tfa2_container.h"
13 #include "tfa_haptic_fw_defs.h"
14 #include "tfa2_dsp_fw.h"
15
16 static int mtp_open(struct tfa2_device *tfa, int state);
17
18 /* enum tfa9xxx_Status_ID */
19 static const char *tfa2_status_id_string[] = {
20 "No response from DSP",
21 "Ok",
22 "Request is being processed",
23 "Provided M-ID does not fit in valid rang [0..2]",
24 "Provided P-ID is not valid in the given M-ID context",
25 "Invalid channel configuration bits (SC|DS|DP|DC) combination",
26 "Invalid sequence of commands, in case the DSP expects some commands in a specific order",
27 "Generic error, invalid parameter",
28 "I2C buffer has overflowed: host has sent too many parameters, memory integrity is not guaranteed",
29 "Calibration not completed",
30 "Calibration failed",
31 "Unspecified error"};
32
tfa2_get_i2c_status_id_string(int status)33 const char *tfa2_get_i2c_status_id_string(int status)
34 {
35 if ((status < tfa9xxx_no_dsp_response) || (status > tfa9xxx_I2C_Req_Calib_Failed))
36 status = tfa9xxx_I2C_Req_Calib_Failed + 1; /* Unspecified error */
37
38 /* enum tfa9xxx_Status_ID starts at -1 */
39 return tfa2_status_id_string[status + 1];
40 }
41
42 static const char *tfa2_manstate_string[] = {"power_down_state",
43 "wait_for_source_settings_state",
44 "connnect_pll_input_state",
45 "disconnect_pll_input_state",
46 "enable_pll_state",
47 "enable_cgu_state",
48 "init_cf_state",
49 "enable_amplifier_state",
50 "alarm_state",
51 "operating_state",
52 "mute_audio_state",
53 "disable_cgu_pll_state",
54 "Unable to find current state"};
55
56 /* align with enum tfa_state */
57 static const char *tfa2_state_enum_string[] = {
58 "", /**< none or unknown or invalid */
59 "TFA_STATE_POWERDOWN", /**< PLL in powerdown, Algo is up/warm */
60 "TFA_STATE_POWERUP", /**< PLL to powerup, Algo can be up/warm */
61 "TFA_STATE_OPERATING", /**< Amp and Algo running */
62 "TFA_STATE_RESET", /**< I2C reset and ACS set */
63 "TFA_STATE_INIT_CF", /**< coolflux HW access possible (~initcf) */
64 "TFA_STATE_OSC", /**< internal oscillator */
65 "TFA_STATE_CLOCK", /**< always return with clock, use OSC if no external clock */
66 "TFA_STATE_POWERDOWN_HAPTIC" /**< PLL in powerdown, skip mute sequence */
67 };
68 /* align with enum tfa_state modifiers */
69 static const char *tfa2_state_mod_enum_string[] = {
70 "", "MUTE", /**< Algo & Amp mute */
71 "UNMUTE", /**< Algo & Amp unmute */
72 };
73
74 /*
75 * Print the current state of the hardware manager
76 * Device manager status information, man_state from TFA9888_N1B_I2C_regmap_V12
77 */
tfa2_show_current_state(struct tfa2_device * tfa)78 void tfa2_show_current_state(struct tfa2_device *tfa)
79 {
80 int manstate = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate);
81 if (manstate < 0)
82 {
83 dev_err(&tfa->i2c->dev, "can't read MANSTATE\n");
84 return;
85 }
86
87 if (manstate > 12)
88 manstate = 12; /* Unable to find current state */
89
90 dev_dbg(&tfa->i2c->dev, "Current HW manager state: %s \n", tfa2_manstate_string[manstate]);
91 }
92
tfa2_dev_get_revid(struct tfa2_device * tfa)93 int tfa2_dev_get_revid(struct tfa2_device *tfa) // TODO remove
94 {
95 return tfa2_i2c_get_revid(tfa->i2c);
96 }
97
tfa2_i2c_get_revid(struct i2c_client * i2c)98 int tfa2_i2c_get_revid(struct i2c_client *i2c)
99 {
100 int rc;
101
102 rc = tfa2_i2c_read_bf(i2c, TFA9XXX_BF_REV);
103 if (rc < 0)
104 return rc;
105
106 dev_dbg(&i2c->dev, "HW rev: 0x%04x\n", (uint16_t)rc);
107
108 return rc;
109 }
110
111 /* fill context info */
tfa2_dev_probe(struct tfa2_device * tfa)112 int tfa2_dev_probe(struct tfa2_device *tfa)
113 {
114 int rc = 0;
115
116 tfa->slave_address = tfa->i2c->addr; /* used by HostSDK */
117
118 if (tfa->i2c->addr > 0)
119 {
120 /* read revid via low level hal */
121 rc = tfa2_i2c_get_revid(tfa->i2c);
122 if (rc < 0)
123 {
124 dev_err(&tfa->i2c->dev, "error reading revid from slave 0x%02x\n", tfa->i2c->addr);
125 return rc;
126 }
127 }
128
129 tfa->rev = (uint16_t)rc;
130 // TODO needed ? tfa->state = TFA_STATE_UNKNOWN;
131
132 tfa2_set_query_info(tfa);
133
134 tfa->in_use = 1;
135
136 return 0;
137 }
138 /*
139 * set device info and register device ops
140 */
tfa2_set_query_info(struct tfa2_device * tfa)141 int tfa2_set_query_info(struct tfa2_device *tfa)
142 {
143 /* invalidate device struct cached values */
144 tfa->hw_feature_bits = -1;
145 tfa->sw_feature_bits[0] = -1;
146 tfa->sw_feature_bits[1] = -1;
147 tfa->profile = -1;
148 tfa->vstep = -1;
149 tfa->need_hw_init = -1;
150 tfa->need_sb_config = -1;
151 tfa->need_hb_config = tfa_hb_undetermined;
152 /* defaults */
153 // tfa->supportDrc = supportNotSet;
154 // tfa->support_saam = supportNotSet;
155 tfa->daimap = Tfa9xxx_DAI_NONE;
156 tfa->bus = 0;
157 tfa->partial_enable = 0;
158 tfa->convert_dsp32 = 0;
159 tfa->is_probus_device = 0;
160 tfa->is_extern_dsp_device = 0;
161 /* bit fields per variant if needed */
162 tfa->bf_clks = TFA9XXX_BF_CLKS; /* default 94N1A */
163 tfa->bf_manstate = TFA9XXX_BF_MANSTATE; /* default 94N1A */
164 tfa->bf_manaoosc = TFA9XXX_BF_MANAOOSC; /* default 94N1A */
165 tfa->bf_noclk = TFA9XXX_BF_NOCLK; /* default 94N1A */
166 tfa->bf_mtpb = TFA9XXX_BF_MTPB; /* default 94N1A */
167 tfa->bf_swprofil = TFA9XXX_BF_SWPROFIL; /* default 94N1A */
168 tfa->bf_swvstep = TFA9XXX_BF_SWVSTEP; /* default 94N1A */
169 tfa->bf_openmtp = TFA9XXX_BF_OPENMTP; /* default 94N1A */
170 tfa->bf_lpm1mode = TFA9XXX_BF_LPM1MODE; /* default 94N1A */
171 tfa->bf_r25c = TFA9XXX_BF_R25C; /* default 94N1A */
172
173 tfa->status_mask[0] = 0x085c; /* SWS, CLKS, UVDS, OVDS, OTDS */
174 tfa->status_mask[1] = 0x0c00; /* TDMLUTER, TDMERR */
175 tfa->status_mask[2] = 0x0000;
176 tfa->status_mask[3] = 0x0000;
177
178 tfa->status_err[0] = 0x87A1;
179 tfa->status_err[1] = 0x0F89;
180 tfa->status_err[2] = 0;
181 tfa->status_err[3] = 0;
182
183 tfa->dsp_init = tfa2_i2c_dsp_init; /* default */
184 tfa->dsp_execute = tfa2_i2c_dsp_execute; /* default */
185
186 /* per- device specific overload functions and/or values */
187 return tfa2_dev_specific(tfa);
188 }
189
190 /*
191 * start the clocks and wait until the PLL is running
192 * on return state is INIT_CF :
193 * the DSP sub system will be ready for loading
194 *
195 * former: tfaRunStartup
196 */
tfa2_dev_start_hw(struct tfa2_device * tfa,int profile)197 int tfa2_dev_start_hw(struct tfa2_device *tfa, int profile)
198 {
199 int rc = 0;
200
201 dev_dbg(&tfa->i2c->dev, "%s\n", __FUNCTION__);
202
203 /* load the optimal TFA98XX in HW settings */
204 rc = tfa2_dev_init(tfa);
205 if (rc < 0)
206 return (rc);
207
208 /* I2S settings to define the audio input properties
209 * these must be set before the subsys is up */
210 /* this will run the list until a clock dependent item is encountered */
211 rc = tfa2_cnt_write_regs_dev(tfa); // write device register settings
212 if (rc < 0)
213 return rc;
214
215 /* also write register settings from the default profile
216 * NOTE PLL is still off, we set switch sample rate here */
217 rc = tfa2_cnt_write_regs_profile(tfa, profile);
218 if (rc < 0)
219 return rc;
220
221 /* device specific fixes */
222 tfa2_init_fix_powerup(tfa);
223
224 /* Go to the initCF state in mute */
225 rc = tfa2_dev_set_state(tfa, (enum tfa_state)(TFA_STATE_POWERUP | TFA_STATE_MUTE));
226 if (rc < 0)
227 return rc;
228
229 rc = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate);
230 if (rc < 0)
231 return rc;
232 dev_dbg(&tfa->i2c->dev, "HW manager state: %d=%s (%s)\n", rc, tfa2_manstate_string[rc], __func__);
233
234 if (rc == 4 || rc == 5)
235 msleep_interruptible(2); /* wait for transition states */
236
237 tfa->need_hw_init = 0; /* hw init has been done now */
238
239 return rc;
240 }
241
242 /*
243 * start DSP firmware
244 * former: tfaRunSpeakerStartup
245 */
tfa2_dev_load_config(struct tfa2_device * tfa,int profile)246 int tfa2_dev_load_config(struct tfa2_device *tfa, int profile)
247 {
248 int rc;
249
250 dev_dbg(&tfa->i2c->dev, "%s\n", __FUNCTION__);
251
252 /* write all the files from the device list */
253 rc = tfa2_cnt_write_files(tfa);
254 if (rc < 0)
255 {
256 dev_dbg(&tfa->i2c->dev, "[%s] tfa2_cnt_write_files error = %d \n", __FUNCTION__, rc);
257 return rc;
258 }
259
260 /* write all the files from the profile list (use volumstep 0) */
261 rc = tfa2_cnt_write_files_profile(tfa, profile, 0);
262 if (rc < 0)
263 {
264 dev_dbg(&tfa->i2c->dev, "[%s] tfaContWriteFilesProf error = %d \n", __FUNCTION__, rc);
265 return rc;
266 }
267
268 return rc;
269 }
270 /*
271 * start CoolFlux DSP subsystem
272 * this will load patch witch may implicitly start the DSP
273 * if no patch is available the DSP is started immediately
274 * former: tfaRunStartDSP
275 */
tfa2_dev_start_cf(struct tfa2_device * tfa)276 int tfa2_dev_start_cf(struct tfa2_device *tfa)
277 {
278 int rc, clock_ok;
279 int data = 0;
280 int control = 1; /* ACS set*/
281
282 dev_dbg(&tfa->i2c->dev, "%s\n", __FUNCTION__);
283
284 /* clock is needed */
285 clock_ok = rc = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_clks);
286 if (rc < 0)
287 return rc;
288 if (!clock_ok) /* if clock is not running, go back */
289 return -EPERM; /* not permitted without clock */
290
291 /* DSP in reset while initializing */
292 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_RST, 1);
293
294 /* ACS must be set to cold start firmware, keep in reset */
295 rc = tfa2_i2c_write_cf_mem32_dsp_reset(tfa->i2c, 0x8100, (int32_t *)&control, 1, TFA2_CF_MEM_IOMEM);
296 if (rc < 0)
297 return rc;
298
299 /* first handle hapticboost if needed */
300 /* this will load the haptic data and and run recalculation if needed */
301 /* check for hb and not ready */
302 if (tfa->need_hb_config && !(tfa->need_hb_config & tfa_hb_ready))
303 {
304 rc = tfa2_dev_start_hapticboost(tfa);
305 if (rc < 0)
306 return rc;
307 tfa->need_hb_config |= tfa_hb_ready; /* ready, don't do it again */
308 }
309
310 /* Clear count_boot, reset to 0
311 * the DSP reset is released later */
312 /* Only for counting firmware soft restarts*/
313 rc = tfa2_i2c_write_cf_mem32_dsp_reset(tfa->i2c, 512, (int32_t *)&data, 1, TFA2_CF_MEM_XMEM);
314 if (rc < 0)
315 { /* any error is fatal so return immediately*/
316 return rc;
317 }
318
319 /* load all patches from dev list, including main patch */
320 rc = tfa2_cnt_write_patches(tfa);
321
322 if (rc < 0)
323 { /* patch load is fatal so return immediately*/
324 dev_dbg(&tfa->i2c->dev, "patch load failed (%d)\n", rc);
325 return rc;
326 }
327
328 /* release DSP reset (patch may have done this as well) */
329 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_RST, 0);
330
331 /* the framework should be running now */
332 tfa->need_cf_init = 0;
333
334 return rc;
335 }
336
337 /*
338 * load and activate a speakerboost profile
339 * former : tfaRunSpeakerBoost
340 */
tfa2_dev_start_speakerboost(struct tfa2_device * tfa,int profile)341 int tfa2_dev_start_speakerboost(struct tfa2_device *tfa, int profile)
342 {
343 int rc = 0;
344
345 tfa2_dev_mtp_set(tfa, TFA_MTP_OPEN, 1);
346
347 /* always a reload when this is called */
348
349 /* Run startup and write all files/messages */
350 rc = tfa2_dev_load_config(tfa, profile);
351 if (rc < 0)
352 return rc;
353
354 /* Save the current profile and set the vstep to 0 */
355 /* This needs to be overwriten even in CF bypass */
356 tfa2_dev_set_swprofile(tfa, (uint16_t)profile);
357 tfa2_dev_set_swvstep(tfa, 0);
358
359 /* load done
360 * tfa->need_sb_config will be cleared when SBSL is cleared to go to operating mode
361 */
362 tfa->need_sb_config = 0;
363
364 return rc;
365 }
366 /*
367 * tfa_dev_start : start the audio profile
368 */
tfa2_dev_start(struct tfa2_device * tfa,int next_profile,int vstep)369 int tfa2_dev_start(struct tfa2_device *tfa, int next_profile, int vstep)
370 {
371 int rc = 0;
372 int active_profile = -1;
373 int have_dsp;
374 char *active_profile_name;
375
376 /* Update init state */
377 tfa2_dev_update_config_init(tfa);
378
379 dev_dbg(&tfa->i2c->dev, "%s ", __FUNCTION__);
380
381 dev_dbg(&tfa->i2c->dev, "HW:%s ", tfa->need_hw_init ? "cold" : "warm");
382 dev_dbg(&tfa->i2c->dev, "SB:%s ", tfa->need_sb_config ? "cold" : "warm");
383 if (tfa->need_hb_config)
384 {
385 dev_dbg(&tfa->i2c->dev, "HB:%s %s\n", (tfa->need_hb_config & TFA_HB_ROLE_MASK) == tfa_hb_lra ? "lra" : "ls",
386 (tfa->need_hb_config & tfa_hb_ready) ? "warm" : "cold"); /* ready is warm */
387 }
388 else
389 {
390 dev_dbg(&tfa->i2c->dev, "HB:none\n");
391 }
392
393 /* Get currentprofile */
394 active_profile = tfa2_dev_get_swprofile(tfa);
395 if (active_profile == 0xff)
396 active_profile = -1;
397
398 active_profile_name = tfa2_cnt_profile_name(tfa->cnt, tfa->dev_idx, active_profile);
399
400 dev_info(&tfa->i2c->dev, " [SB] active profile:%s, next profile:%s\n",
401 active_profile_name ? active_profile_name : "none",
402 tfa2_cnt_profile_name(tfa->cnt, tfa->dev_idx, next_profile));
403
404 /* start hardware: init tfa registers and start PLL */
405 if (tfa->need_hw_init)
406 {
407 rc = tfa2_dev_start_hw(tfa, next_profile); /* return muted in initcf state */
408 if (rc < 0)
409 {
410 dev_dbg(&tfa->i2c->dev, "%s : error when starting hardware\n", __FUNCTION__);
411 return rc;
412 }
413 }
414 else
415 {
416 /* start the clocks */
417 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERUP);
418 if (rc < 0)
419 return rc;
420 }
421
422 /* if started without DSP */
423 have_dsp = tfa2_dev_cf_enabled(tfa);
424 /* start coolflux if needed : not in bypass or any firmware config needed */
425 if (tfa->need_cf_init && have_dsp)
426 {
427 /* start CoolFlux DSP subsystem, will check if clock is there */
428 rc = tfa2_dev_start_cf(tfa);
429 if (rc < 0)
430 return rc;
431 }
432 /* the framework should be running now */
433 /* speakerboost parameters can be loaded */
434 if (tfa->need_sb_config && have_dsp)
435 {
436 rc = tfa2_dev_start_speakerboost(tfa, next_profile);
437 if (rc < 0)
438 return rc;
439 }
440
441 /* Should be operating state if audio clock is present
442 * or in powerdown if there is no audio clock
443 */
444 dev_dbg(&tfa->i2c->dev, "HW manager state: %d (%s 1)\n", tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate), __func__);
445
446 active_profile = tfa2_dev_get_swprofile(tfa);
447
448 /* Profile switching */
449 if ((next_profile != active_profile && active_profile >= 0))
450 {
451 rc = tfa2_cnt_write_profile(tfa, next_profile, vstep);
452 if (rc < 0)
453 {
454 dev_err(&tfa->i2c->dev, "%s : error %d returned by write profile\n", __FUNCTION__, rc);
455 goto error_exit;
456 }
457 }
458
459 /* Go to the Operating state */
460 rc = tfa2_dev_set_state(tfa, (enum tfa_state)(TFA_STATE_OPERATING | TFA_STATE_MUTE));
461 if (rc < 0)
462 return rc;
463
464 /* If the profile contains the .standby suffix go to powerdown
465 * else we should be in operating state
466 */
467 if (strstr(tfa2_cnt_profile_name(tfa->cnt, tfa->dev_idx, next_profile), ".standby") != NULL)
468 {
469 tfa2_dev_set_swprofile(tfa, (unsigned short)next_profile);
470 tfa2_dev_set_swvstep(tfa, (unsigned short)tfa->vstep);
471 goto error_exit;
472 }
473
474 tfa2_dev_set_swprofile(tfa, (unsigned short)next_profile);
475 tfa2_dev_set_swvstep(tfa, (unsigned short)tfa->vstep);
476
477 error_exit:
478
479 /* close MTP access */
480 tfa2_dev_mtp_set(tfa, TFA_MTP_OPEN, 0);
481
482 dev_dbg(&tfa->i2c->dev, "HW manager state: %d (%s 2)\n", tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate), __func__);
483
484 return rc;
485 }
486
tfa2_dev_stop(struct tfa2_device * tfa)487 int tfa2_dev_stop(struct tfa2_device *tfa)
488 {
489 return tfa2_dev_set_state(tfa, (enum tfa_state)(TFA_STATE_POWERDOWN | TFA_STATE_MUTE));
490 }
491
492 /*
493 * set ISTVDDS
494 * clear SBSL and ACS (need clock for ACS)
495 */
tfa2_dev_force_cold(struct tfa2_device * tfa)496 int tfa2_dev_force_cold(struct tfa2_device *tfa)
497 {
498 int rc;
499 int cf_control = 1; /* ACS set*/
500
501 dev_dbg(&tfa->i2c->dev, "%s\n", __FUNCTION__);
502
503 tfa->need_hw_init = -1;
504 tfa->need_cf_init = -1;
505 tfa->need_sb_config = -1;
506 tfa->need_hb_config = tfa_hb_undetermined;
507
508 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 0);
509 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERDOWN);
510 // if ( rc < 0 )
511
512 rc = tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_RST, 1);
513 if (rc < 0)
514 return rc;
515 rc = tfa2_dev_set_state(tfa, TFA_STATE_OSC);
516 if (rc < 0)
517 return rc;
518
519 if (!tfa->is_probus_device)
520 {
521 /* set ACS */
522 tfa2_i2c_write_cf_mem32_dsp_reset(tfa->i2c, 0x8100, (int32_t *)&cf_control, 1, TFA2_CF_MEM_IOMEM);
523 }
524
525 /* Powerdown */
526 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 0);
527 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERDOWN);
528 /* set I2CR */
529 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_I2CR, 1); /*this will also stop the PLL */
530
531 /* toggle IPOVDDS (polarity) to set ISTVDDS */
532 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_IPOVDDS, 0); /* low */
533 rc = tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_IPOVDDS, 1); /* high */
534
535 tfa2_dev_update_config_init(tfa);
536
537 return rc;
538 }
539 /* small get state functions */
tfa2_dev_is_fw_cold(struct tfa2_device * tfa)540 int tfa2_dev_is_fw_cold(struct tfa2_device *tfa)
541 {
542 return tfa->need_sb_config; /* SBSL is not set if config not done */
543 // TODO confirm/test return tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_ACS);
544 }
545
tfa2_cf_enabled(struct tfa2_device * tfa)546 int tfa2_cf_enabled(struct tfa2_device *tfa)
547 {
548 return tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_CFE);
549 }
tfa2_dev_set_configured(struct tfa2_device * tfa)550 int tfa2_dev_set_configured(struct tfa2_device *tfa)
551 {
552 return tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_SBSL, 1);
553 }
554
555 /**
556 * central function to control manager and clock states relevant to driver.
557 *
558 * TFA_STATE_NONE not requested, unknown or invalid
559 * TFA_STATE_POWERDOWN PLL in powerdown, Algo is up/warm
560 * TFA_STATE_POWERUP PLL to powerup, Algo can be up/warm
561 * TFA_STATE_OPERATING Amp and Algo running
562 * --helper states for MTP and control--
563 * TFA_STATE_RESET I2C reset and ACS set
564 * TFA_STATE_INIT_CF coolflux HW access possible (~initcf)
565 * TFA_STATE_OSC internal oscillator
566 * --sticky state modifiers--
567 * TFA_STATE_MUTE=0x10 Algo & Amp mute
568 * TFA_STATE_UNMUTE=0x20 Algo & Amp unmute
569 *
570 */
571 // TODO determine max poll tims
572 #define TFA_STATE_INIT_CF_POLL 100
573 #define TFA_STATE_POWERDOWN_POLL 2000
574 #define TFA_STATE_OPERATING_POLL 50
575 #define TFA_STATE_POWERDOWN_HAPTIC_POLL 50
576
tfa2_dev_set_state(struct tfa2_device * tfa,enum tfa_state state)577 int tfa2_dev_set_state(struct tfa2_device *tfa, enum tfa_state state)
578 {
579 int rc = 0;
580 int manstate;
581 int ext_clock_wait;
582
583 dev_dbg(&tfa->i2c->dev, "set logical state: %s %s\n", tfa2_state_enum_string[state & 0x0f],
584 tfa2_state_mod_enum_string[(state & 0x30) >> 4]);
585
586 /* state modifiers pre */
587 if (state & TFA_STATE_MUTE)
588 {
589 rc = tfa2_dev_mute(tfa, 1);
590 if (rc < 0)
591 return rc;
592 }
593
594 /* Base states */
595 rc = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate);
596 if (rc < 0)
597 return rc;
598 manstate = rc;
599 rc = 0;
600
601 dev_dbg(&tfa->i2c->dev, "Current HW manager state: %s \n", tfa2_manstate_string[manstate]);
602
603 switch (state & 0x0f)
604 {
605 case TFA_STATE_POWERDOWN: /* PLL in powerdown, Algo up */
606 if (manstate == 0) /* done if already there */
607 {
608 rc = 0;
609 break;
610 }
611
612 /* device specific fixes */
613 rc = tfa2_init_fix_powerdown(tfa, manstate);
614 if (rc < 0)
615 break;
616
617 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 1);
618 if (rc < 0)
619 break;
620 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 0);
621
622 /* wait for powerdown state */
623 rc = tfa2_i2c_bf_poll(tfa->i2c, tfa->bf_manstate, 0, TFA_STATE_POWERDOWN_POLL);
624
625 if (rc == 0)
626 tfa2_i2c_write_bf(tfa->i2c, tfa->bf_manaoosc, 0 /*1*/); /* 1 = off */
627 else
628 dev_err(&tfa->i2c->dev, "Powerdown wait timedout.\n");
629
630 break;
631 case TFA_STATE_POWERDOWN_HAPTIC:
632 if (manstate == 0) /* done if already there */
633 {
634 rc = 0;
635 break;
636 }
637 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_AMPC, 0);
638 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_AMPE, 0);
639 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 0);
640 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 1);
641 if (rc < 0)
642 break;
643
644 /* wait for powerdown state */
645 rc = tfa2_i2c_bf_poll(tfa->i2c, tfa->bf_manstate, 0, TFA_STATE_POWERDOWN_HAPTIC_POLL);
646 if (rc == 0)
647 tfa2_i2c_write_bf(tfa->i2c, tfa->bf_manaoosc, 0 /*1*/); /* 1 = off */
648 else
649 dev_err(&tfa->i2c->dev, "Powerdown wait timedout.\n");
650
651 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_AMPC, 1);
652 break;
653 case TFA_STATE_POWERUP: /**< PLL to powerup, Algo can be up/warm */
654 /* power on the sub system */
655 if (manstate == 9 || manstate == 6) /* done if already there */
656 {
657 rc = 0;
658 break;
659 }
660 /* powerup osc */
661 tfa2_i2c_write_bf(tfa->i2c, tfa->bf_manaoosc, 0); /* 0 = on */
662 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 1);
663 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 0);
664 if (rc < 0)
665 return rc;
666
667 if (tfa2_dev_cf_enabled(tfa))
668 /* if not on internal osc then we wait for external clock */
669 ext_clock_wait = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MANCOLD) == 0;
670 else
671 ext_clock_wait = 1;
672 if (ext_clock_wait)
673 {
674 dev_dbg(&tfa->i2c->dev, "Waiting for external clock ...\n");
675 }
676 else
677 {
678 dev_dbg(&tfa->i2c->dev, "Waiting for clock stable...\n");
679 rc = tfa2_dev_clock_stable_wait(tfa);
680 }
681 break;
682 case TFA_STATE_CLOCK: /**< always return with clock, use OSC if no external clock */
683 /* power on the sub system */
684 if (tfa2_i2c_read_bf(tfa->i2c, tfa->bf_clks) == 1) /* done if already there */
685 {
686 rc = 0;
687 break;
688 }
689
690 /* no immediate clock needed if no DSP, just powerup */
691 if (!tfa2_dev_cf_enabled(tfa))
692 {
693 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERUP);
694 break;
695 }
696 /* go the wait_for_source_settings_state for checking NOCLK
697 * this will tell if the external clock is active or not
698 */
699 tfa2_i2c_write_bf(tfa->i2c, tfa->bf_manaoosc, 0); /* 0 = on */
700 /* stay in wait_for_source_settings */
701 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_MANSCONF, 0);
702 /* goto wait_for_source_settings */
703 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 0);
704
705 /* if NOCLK then we wait for external clock */
706 if (tfa2_i2c_read_bf(tfa->i2c, tfa->bf_noclk) == 1)
707 { /* use the oscillator */
708 rc = tfa2_dev_set_state(tfa, TFA_STATE_OSC);
709 if (rc < 0)
710 break;
711 }
712 else
713 { /* normal power up on external clock */
714 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERUP);
715 if (rc < 0)
716 break;
717 }
718 /* in this case we always need a clock, fail if not ready */
719 rc = tfa2_dev_clock_stable_wait(tfa);
720 break;
721 case TFA_STATE_OPERATING: /* Amp and Algo running */
722 if (manstate == 9) /* done if already there */
723 {
724 rc = 0;
725 break;
726 }
727
728 ext_clock_wait = 0;
729 /* restart if on internal clock */
730 if (manstate == 6)
731 {
732 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 1);
733 tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_PWDN, 0);
734 ext_clock_wait = 1;
735 }
736 /* powerup first if off or coming from initcf */
737 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERUP);
738 if (rc < 0)
739 break;
740
741 /* if in wait2srcsetting and mansconf is done then we wait for external clock */
742 if (manstate == 1)
743 {
744 ext_clock_wait =
745 tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MANSCONF) && tfa2_i2c_read_bf(tfa->i2c, tfa->bf_noclk);
746 }
747
748 if (tfa2_dev_cf_enabled(tfa))
749 {
750 /* set SBSL to go to operating */
751 rc = tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_SBSL, 1);
752
753 /* if calibration once is in progress wait to allow CF to write MTP */
754 if (tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_ACS) == 0 && /* warm */
755 tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MTPOTC) == 1)
756 { /* once */
757 int count = 50 * 4; /* Calibration takes ~500mS */
758 while ((tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MTPEX) != 1) && count)
759 {
760 msleep_interruptible(10);
761 count--;
762 }
763 if (!count)
764 {
765 pr_err("Calibration once timed out\n");
766 rc = -ETIME;
767 }
768 }
769 /* only wait for operating if we are not on internal clock
770 * and not waiting for external clock
771 * external clock may not be running yet */
772 if (ext_clock_wait == 0)
773 rc = tfa2_i2c_bf_poll(tfa->i2c, tfa->bf_manstate, 9, TFA_STATE_OPERATING_POLL);
774 }
775 break;
776 case TFA_STATE_RESET: /* I2C reset and sbls set */
777 /* goes to powerdown first */
778 rc = tfa2_dev_force_cold(tfa);
779 break;
780 case TFA_STATE_INIT_CF: /**< coolflux HW access possible (~initcf) */
781 /* init_cf is mainly used for MTP manual copy */
782 if (manstate == 6) /* done if already there */
783 {
784 rc = 0;
785 break;
786 }
787 /* if SBSL is 0, we'll be in init_cf after powerup */
788 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERDOWN);
789 if (rc < 0)
790 break;
791 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_SBSL, 0);
792 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERUP);
793 if (rc < 0)
794 { /* restore SBSL back to 1 on failure here */
795 if (tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_ACS) == 0)
796 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_SBSL, 1);
797 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERDOWN);
798 break;
799 }
800 rc = tfa2_i2c_bf_poll(tfa->i2c, tfa->bf_manstate, 6, TFA_STATE_INIT_CF_POLL);
801 break;
802 case TFA_STATE_OSC: /* run on internal oscillator, in init_cf */
803 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERDOWN);
804 if (rc < 0)
805 break;
806 if (tfa2_dev_cf_enabled(tfa))
807 {
808 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MANCOLD, 1);
809 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_SBSL, 0);
810 }
811 /* will poll until clock ready */
812 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERUP);
813 break;
814 case TFA_STATE_NONE: /* nothing */
815 break;
816 default:
817 if (state & 0x0f)
818 rc = -EINVAL;
819 break;
820 }
821
822 /* state modifiers post */
823 if (state & TFA_STATE_UNMUTE)
824 {
825 /* only update return code in case rc was 0 */
826 rc = (rc == 0) ? tfa2_dev_mute(tfa, 0) : rc;
827 }
828
829 if (rc == 0 && state != TFA_STATE_NONE)
830 tfa->state = state;
831
832 // dev_dbg(&tfa->i2c->dev, "done logical state: %s\n",
833 // tfa2_state_enum_string[tfa->state & 0x0f]);
834
835 return rc;
836 }
837
838 /*
839 * bring the device into a state similar to reset
840 */
tfa2_dev_init(struct tfa2_device * tfa)841 int tfa2_dev_init(struct tfa2_device *tfa)
842 {
843 int error;
844 uint16_t value = 0;
845
846 /* reset all i2C registers to default
847 * Write the register directly to avoid the read in the bitfield function.
848 * The I2CR bit may overwrite the full register because it is reset anyway.
849 */
850 tfa2_i2c_set_bf_value(TFA9XXX_BF_I2CR, 1, &value); /* This will save an i2c reg read */
851 error = tfa2_i2c_write_reg(tfa->i2c, TFA9XXX_BF_I2CR, value);
852 if (error)
853 return error;
854 /* Put DSP in reset */
855 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_RST, 1); // TODO remove?
856
857 /* some other registers must be set for optimal amplifier behaviour
858 * This is implemented in a file specific for the type number
859 */
860 if (tfa->tfa_init)
861 error = (tfa->tfa_init)(tfa);
862 else
863 return -ENODEV;
864
865 /* clear so next time no init */
866 error = tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_ICLVDDS, 1);
867 if (error)
868 return error;
869
870 return error;
871 }
872
tfa2_dev_mute(struct tfa2_device * tfa,int state)873 int tfa2_dev_mute(struct tfa2_device *tfa, int state)
874 {
875 if (tfa->is_probus_device == 1)
876 {
877 dev_dbg(&tfa->i2c->dev, "no DSP %smute for Probus device\n", state ? "" : "un");
878 return 0;
879 }
880
881 dev_dbg(&tfa->i2c->dev, "DSP %smute\n", state ? "" : "un");
882 return tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_CFSM, state);
883 }
884
885 /*
886 * the register will always start counting @1 because the reset value==0
887 */
tfa2_dev_set_swprofile(struct tfa2_device * tfa,unsigned short new_value)888 int tfa2_dev_set_swprofile(struct tfa2_device *tfa, unsigned short new_value)
889 {
890 int active_value = tfa2_dev_get_swprofile(tfa);
891
892 /* Set the new value in the struct */
893 tfa->profile = new_value;
894
895 /* Set the new value in the hw register */
896 tfa2_i2c_write_bf_volatile(tfa->i2c, tfa->bf_swprofil, new_value + 1);
897
898 return active_value;
899 }
900
tfa2_dev_get_swprofile(struct tfa2_device * tfa)901 int tfa2_dev_get_swprofile(struct tfa2_device *tfa)
902 {
903 return tfa2_i2c_read_bf(tfa->i2c, tfa->bf_swprofil) - 1;
904 }
905
906 /*
907 * the register will always start counting @1 because the reset value==0
908 */
tfa2_dev_set_swvstep(struct tfa2_device * tfa,unsigned short new_value)909 int tfa2_dev_set_swvstep(struct tfa2_device *tfa, unsigned short new_value)
910 {
911 /* Set the new value in the struct */
912 tfa->vstep = new_value;
913
914 /* Set the new value in the hw register */
915 tfa2_i2c_write_bf_volatile(tfa->i2c, tfa->bf_swvstep, new_value + 1);
916
917 return new_value;
918 }
tfa2_dev_get_swvstep(struct tfa2_device * tfa)919 int tfa2_dev_get_swvstep(struct tfa2_device *tfa)
920 {
921 return tfa2_i2c_read_bf(tfa->i2c, tfa->bf_swvstep) - 1;
922 }
923
924 /*
925 * update the struct for hw and fw init fields
926 * if no DSP need_sb_config can be skipped
927 */
tfa2_dev_update_config_init(struct tfa2_device * tfa)928 int tfa2_dev_update_config_init(struct tfa2_device *tfa)
929 {
930 int rc = 0;
931 int cf_enabled;
932
933 rc = tfa2_dev_cf_enabled(tfa);
934 if (rc < 0)
935 return rc;
936 cf_enabled = rc;
937
938 /* tfa->need_hw_init :returns 1 when tfa is "cold" and 0 when device is warm */
939 if (cf_enabled)
940 {
941 tfa->need_hw_init = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_ACS);
942 tfa->need_cf_init = tfa->need_hw_init;
943 tfa->need_sb_config = tfa->need_hw_init;
944 }
945 else
946 {
947 tfa->need_hw_init = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_ISTVDDS);
948 tfa->need_cf_init = 0;
949 tfa->need_sb_config = 0; // this may be needed in case of in-kernel messaging
950 }
951
952 /* haptic boost configs relies on profile names: LRA, speaker or none */
953 if (tfa->need_hb_config == tfa_hb_undetermined)
954 {
955 /* if we have lra_ profile prefixes we have the lra */
956 if (tfa2_cnt_grep_profile_name(tfa->cnt, tfa->dev_idx, "lra_") >= 0)
957 tfa->need_hb_config = tfa_hb_lra;
958 else if (tfa2_cnt_grep_profile_name(tfa->cnt, tfa->dev_idx, "ls_") >= 0)
959 tfa->need_hb_config = tfa_hb_ls;
960 else
961 tfa->need_hb_config = tfa_hb_none;
962 }
963
964 return 0;
965 }
966
tfa2_dev_faim_protect(struct tfa2_device * tfa,int state)967 int tfa2_dev_faim_protect(struct tfa2_device *tfa, int state)
968 {
969 /* 0b = FAIM protection enabled:default 1b = FAIM protection disabled */
970 return tfa2_i2c_write_bf_volatile(tfa->i2c, tfa->bf_openmtp, (uint16_t)(state));
971 }
972
tfa2_dev_dsp_system_stable(struct tfa2_device * tfa,int * ready)973 int tfa2_dev_dsp_system_stable(struct tfa2_device *tfa, int *ready)
974 {
975 int rc;
976
977 if (tfa->reg_time)
978 {
979 /* extra wait delay */
980 int loop = tfa->reg_time;
981 do
982 {
983 tfa2_i2c_read_bf(tfa->i2c, tfa->bf_clks); /* dummy read */
984 } while (loop--);
985 }
986 /* read CLKS: ready if set */
987 rc = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_clks);
988 if (rc < 0)
989 {
990 dev_err(&tfa->i2c->dev, "I2C fails when read clks!\n");
991 }
992 else
993 {
994 *ready = rc;
995 }
996
997 return rc;
998 }
999
1000 #define TFA_CLKS_POLL 50
tfa2_dev_clock_stable_wait(struct tfa2_device * tfa)1001 int tfa2_dev_clock_stable_wait(struct tfa2_device *tfa)
1002 {
1003 return tfa2_i2c_bf_poll(tfa->i2c, tfa->bf_clks, 1, TFA_CLKS_POLL);
1004 }
1005
tfa2_dev_cf_enabled(struct tfa2_device * tfa)1006 int tfa2_dev_cf_enabled(struct tfa2_device *tfa)
1007 {
1008 int value;
1009
1010 if (tfa->is_probus_device)
1011 { /* probus has no CFE bit */
1012 value = 0;
1013 }
1014 else
1015 {
1016 value = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_CFE);
1017 }
1018
1019 return value;
1020 }
1021
1022 #define FW_PATCH_HEADER_LENGTH 6
tfa2_dev_dsp_patch(struct tfa2_device * tfa,int patchLength,const uint8_t * patchBytes)1023 int tfa2_dev_dsp_patch(struct tfa2_device *tfa, int patchLength, const uint8_t *patchBytes)
1024 {
1025 int rc;
1026
1027 if (tfa->in_use == 0)
1028 return -EPERM;
1029
1030 // TODO add low level test?
1031 // rc = tfa2_check_patch(patchBytes+6,patchLength-6, tfa->rev );
1032 // if ( rc < 0 )
1033 // return rc;
1034
1035 rc = tfa2_process_patch_file(tfa->i2c, patchLength - FW_PATCH_HEADER_LENGTH, patchBytes + FW_PATCH_HEADER_LENGTH);
1036
1037 return rc;
1038 }
1039 /****************************** DSP RPC ************************************/
1040 #define TFA98XX_WAITRESULT_NTRIES 40
1041 #define TFA98XX_WAITRESULT_NTRIES_LONG 2000
1042 /** Value used by tfa_dsp_msg_status() to determine busy-wait time for DSP message acknowledgement*/
1043 #define CF_RPC_RETRY_NUM 16 /* wait loop count */
1044 #define CF_STATUS_I2C_CMD_ACK 0x01
1045
1046 /* dsp RPC message for I2C */
tfa2_i2c_rpc_write(struct i2c_client * i2c,int length,const char * buffer)1047 int tfa2_i2c_rpc_write(struct i2c_client *i2c, int length, const char *buffer)
1048 {
1049 int rc;
1050 uint16_t cfctl;
1051 int cfctl_reg = (TFA9XXX_BF_DMEM >> 8) & 0xff; /* where DMEM is */
1052
1053 /* write the RPC message to the i2c buffer @xmem[1] */
1054 rc = tfa2_i2c_write_cf_mem24(i2c, 1, (uint8_t *)buffer, length, TFA2_CF_MEM_XMEM);
1055
1056 rc = tfa2_i2c_read_reg(i2c, cfctl_reg); /* will report error */
1057 if (rc < 0)
1058 return rc;
1059 cfctl = (uint16_t)rc;
1060
1061 /* notify the DSP */
1062
1063 /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */
1064 /* set the cf_req1 and cf_int bit */
1065 tfa2_i2c_set_bf_value(TFA9XXX_BF_REQCMD, 0x01, &cfctl); /* REQ bit 0 */
1066 tfa2_i2c_set_bf_value(TFA9XXX_BF_CFINT, 1, &cfctl);
1067 rc = tfa2_i2c_write_reg(i2c, cfctl_reg, cfctl);
1068
1069 return rc;
1070 }
1071
tfa2_i2c_rpc_status(struct i2c_client * i2c,int * pRpcStatus)1072 int tfa2_i2c_rpc_status(struct i2c_client *i2c, int *pRpcStatus)
1073 {
1074 int rc; /* return value */
1075 unsigned retry_cnt = 0; /* Retry counter for ACK busy-wait */
1076 uint16_t cf_status = 0;
1077 uint8_t xmem0[4];
1078
1079 /* Set RPC result initially to tfa9xxx_no_dsp_response. In case we have comm. problems */
1080
1081 /* Start waiting for DSP response */
1082 while (retry_cnt < CF_RPC_RETRY_NUM)
1083 {
1084 rc = tfa2_i2c_read_bf(i2c, TFA9XXX_BF_ACKCMD);
1085 if (rc < 0)
1086 return rc;
1087 cf_status = (uint16_t)rc; /* ret contains flags, when no error */
1088
1089 if ((cf_status & CF_STATUS_I2C_CMD_ACK))
1090 break; /* There is no error and DSP already ACK-ed message */
1091 retry_cnt++;
1092 }
1093 // TODO check more status ACK
1094 /* If DSP timed out on giving response */
1095 if ((retry_cnt >= CF_RPC_RETRY_NUM) && !(cf_status & CF_STATUS_I2C_CMD_ACK))
1096 {
1097 /* Set RPC result initially to tfa9xxx_no_dsp_response. In case we have comm. problems */
1098 *pRpcStatus = tfa9xxx_no_dsp_response; // TODO no_dsp_response is misleading, should be error response
1099 rc = -ENXIO;
1100 }
1101 else
1102 {
1103 /* Get DSP status (could be busy, RPC error or OK) */
1104 rc = tfa2_i2c_read_cf_mem24(i2c, 0, xmem0, 3, TFA2_CF_MEM_XMEM);
1105 *pRpcStatus = xmem0[2]; /* result is high byte in big endian */
1106 }
1107
1108 return rc;
1109 }
1110
1111 /*****************************************************************************
1112 *
1113 * I2C level functions
1114 */
1115
1116 /*
1117 * poll for the bf until value or loopcount exhaust return timeout
1118 */
tfa2_i2c_bf_poll(struct i2c_client * client,uint16_t bf,uint16_t wait_value,int loop)1119 int tfa2_i2c_bf_poll(struct i2c_client *client, uint16_t bf, uint16_t wait_value, int loop)
1120 {
1121 // TODO use tfa->reg_time;
1122 int value, rc;
1123 int loop_arg = loop;
1124
1125 /* @400k take 500uS/cycle : wait 500ms first */
1126 if (loop > 1000)
1127 {
1128 loop -= 1000;
1129 msleep_interruptible(500);
1130 }
1131 do
1132 value = tfa2_i2c_read_bf(client, bf); /* read */
1133 while (value != wait_value && --loop);
1134
1135 rc = loop ? 0 : -ETIME;
1136
1137 if (rc == -ETIME)
1138 dev_err(&client->dev, "timeout waiting for bitfield:0x%04x, value:%d, %d times\n", bf, wait_value, loop_arg);
1139
1140 return rc;
1141 }
1142
tfa2_i2c_dsp_init(struct tfa2_device * tfa,const char * cmd_buf,size_t cmd_len)1143 int tfa2_i2c_dsp_init(struct tfa2_device *tfa, const char *cmd_buf, size_t cmd_len)
1144 {
1145 (void)tfa;
1146 (void)cmd_buf;
1147 (void)cmd_len;
1148
1149 return 0;
1150 }
1151
tfa2_i2c_dsp_execute(struct tfa2_device * tfa,const char * cmd_buf,size_t cmd_len,char * res_buf,size_t res_len)1152 int tfa2_i2c_dsp_execute(struct tfa2_device *tfa, const char *cmd_buf, size_t cmd_len, char *res_buf, size_t res_len)
1153 {
1154 struct i2c_client *i2c = tfa->i2c;
1155 int rc;
1156 int tries, rpc_status = -1;
1157
1158 if (cmd_len)
1159 {
1160 /* Write the message and notify the DSP */
1161 rc = tfa2_i2c_rpc_write(i2c, cmd_len, cmd_buf);
1162 if (rc)
1163 return rc;
1164 }
1165
1166 /* Get the result from the DSP (polling) */
1167 for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--)
1168 {
1169 rc = tfa2_i2c_rpc_status(i2c, &rpc_status);
1170 if (rc || rpc_status != tfa9xxx_I2C_Req_Busy)
1171 break; /* Return on I/O error or error status from DSP */
1172
1173 msleep_interruptible(1); /* Add non-busy wait to give DSP processing time */
1174 }
1175
1176 if (rpc_status != tfa9xxx_I2C_Req_Done)
1177 {
1178 /* DSP RPC call returned an error */
1179 dev_dbg(&i2c->dev, "DSP msg status: %d (%s)\n", rpc_status, tfa2_get_i2c_status_id_string(rpc_status));
1180 /* return rc; */
1181 }
1182
1183 /* if a result is requested get it now */
1184 if (res_len > 0)
1185 {
1186 /* put the result from xmem[0] at the beginning */
1187 *res_buf++ = rpc_status >> 16;
1188 *res_buf++ = rpc_status >> 8;
1189 *res_buf++ = rpc_status;
1190 res_len -= 3;
1191
1192 /* get the rest */
1193 if (res_len > 0)
1194 rc = tfa2_i2c_read_cf_mem24(i2c, 1, (uint8_t *)res_buf, res_len, TFA2_CF_MEM_XMEM);
1195 else
1196 rc = 0;
1197 }
1198
1199 return rc;
1200 }
1201
tfa2_dsp_init(struct tfa2_device * tfa,const char * cmd_buf,size_t cmd_len)1202 int tfa2_dsp_init(struct tfa2_device *tfa, const char *cmd_buf, size_t cmd_len)
1203 {
1204 return tfa->dsp_init(tfa, cmd_buf, cmd_len);
1205 }
1206
1207 /*
1208 * the dsp execute funtion will execute the RPC message in the cmd_buf and return the result
1209 */
tfa2_dsp_execute(struct tfa2_device * tfa,const char * cmd_buf,size_t cmd_len,char * res_buf,size_t res_len)1210 int tfa2_dsp_execute(struct tfa2_device *tfa, const char *cmd_buf, size_t cmd_len, char *res_buf, size_t res_len)
1211 {
1212 return tfa->dsp_execute(tfa, cmd_buf, cmd_len, res_buf, res_len);
1213 }
1214
tfa2_get_noclk(struct tfa2_device * tfa)1215 int tfa2_get_noclk(struct tfa2_device *tfa)
1216 {
1217 return tfa2_i2c_read_bf(tfa->i2c, tfa->bf_noclk);
1218 }
1219
1220 /******************************************************************************
1221 * i2c and register functions
1222 */
1223 /*
1224 * tfa_ functions copied from tfa_dsp.c
1225 */
tfa2_i2c_get_bf_value(const uint16_t bf,const uint16_t reg_value)1226 uint16_t tfa2_i2c_get_bf_value(const uint16_t bf, const uint16_t reg_value)
1227 {
1228 uint16_t msk, value;
1229
1230 /*
1231 * bitfield enum:
1232 * - 0..3 : len
1233 * - 4..7 : pos
1234 * - 8..15 : address
1235 */
1236 uint8_t len = bf & 0x0f;
1237 uint8_t pos = (bf >> 4) & 0x0f;
1238
1239 msk = ((1 << (len + 1)) - 1) << pos;
1240 value = (reg_value & msk) >> pos;
1241
1242 return value;
1243 }
1244
tfa2_i2c_set_bf_value(const uint16_t bf,const uint16_t bf_value,uint16_t * p_reg_value)1245 int tfa2_i2c_set_bf_value(const uint16_t bf, const uint16_t bf_value, uint16_t *p_reg_value)
1246 {
1247 uint16_t value, regvalue, msk;
1248
1249 /*
1250 * bitfield enum:
1251 * - 0..3 : len
1252 * - 4..7 : pos
1253 * - 8..15 : address
1254 */
1255 uint8_t len = bf & 0x0f;
1256 uint8_t pos = (bf >> 4) & 0x0f;
1257
1258 regvalue = *p_reg_value;
1259
1260 msk = ((1 << (len + 1)) - 1) << pos;
1261 value = bf_value << pos;
1262 value &= msk;
1263 regvalue &= ~msk;
1264 regvalue |= value;
1265
1266 *p_reg_value = regvalue;
1267
1268 return 0;
1269 }
1270
tfa2_i2c_read_reg(struct i2c_client * client,uint8_t reg)1271 int tfa2_i2c_read_reg(struct i2c_client *client, uint8_t reg)
1272 {
1273 int rc;
1274 uint16_t value;
1275 uint8_t buffer[2];
1276
1277 rc = tfa2_i2c_write_read_raw(client, 1, ®, 2, buffer);
1278 if (rc < 0)
1279 {
1280 dev_err(&client->dev, "i2c reg read for 0x%x failed\n", reg);
1281 return rc;
1282 }
1283 else
1284 {
1285 value = (buffer[0] << 8) | buffer[1];
1286 }
1287
1288 return value;
1289 }
1290
tfa2_i2c_write_reg(struct i2c_client * client,uint8_t reg,uint16_t val)1291 int tfa2_i2c_write_reg(struct i2c_client *client, uint8_t reg, uint16_t val)
1292 {
1293 int rc;
1294 uint8_t buffer[3];
1295
1296 buffer[0] = reg;
1297 buffer[1] = val >> 8;
1298 buffer[2] = val;
1299
1300 rc = tfa2_i2c_write_raw(client, 3, buffer);
1301
1302 if (rc < 0)
1303 {
1304 dev_err(&client->dev, "i2c reg write for 0x%x failed\n", reg);
1305 }
1306
1307 return rc;
1308 }
1309
tfa2_i2c_read_regs(struct i2c_client * i2c,uint8_t addr,int nr,uint16_t * regs)1310 int tfa2_i2c_read_regs(struct i2c_client *i2c, uint8_t addr, int nr, uint16_t *regs)
1311 {
1312 int rc, i;
1313 uint8_t *buffer;
1314
1315 buffer = kmalloc(2 * nr, GFP_KERNEL);
1316 if (!buffer)
1317 return -ENOMEM;
1318
1319 rc = tfa2_i2c_write_read_raw(i2c, 1, &addr, 2 * nr, buffer);
1320 if (rc < 0)
1321 {
1322 dev_err(&i2c->dev, "i2c reg read for 0x%x failed\n", addr);
1323 goto error;
1324 }
1325
1326 for (i = 0; i < nr; i++)
1327 {
1328 regs[i] = (buffer[i * 2] << 8) | buffer[i * 2 + 1];
1329 }
1330
1331 error:
1332 kfree(buffer);
1333
1334 return rc;
1335 }
1336
tfa2_i2c_read_bf(struct i2c_client * client,uint16_t bitfield)1337 int tfa2_i2c_read_bf(struct i2c_client *client, uint16_t bitfield)
1338 {
1339 uint8_t reg = (bitfield >> 8) & 0xff; /* extract register addess */
1340 uint16_t value;
1341 int rc;
1342
1343 rc = tfa2_i2c_read_reg(client, reg);
1344 if (rc < 0)
1345 return rc;
1346 value = (uint16_t)rc;
1347
1348 return tfa2_i2c_get_bf_value(bitfield, value); /* extract the value */
1349 }
1350
tfa2_i2c_write_bf_internal(struct i2c_client * client,uint16_t bitfield,uint16_t value,int write_always)1351 static int tfa2_i2c_write_bf_internal(struct i2c_client *client, uint16_t bitfield, uint16_t value, int write_always)
1352 {
1353 int rc;
1354 uint16_t newvalue, oldvalue;
1355 uint8_t address;
1356
1357 /*
1358 * bitfield enum:
1359 * - 0..3 : len-1
1360 * - 4..7 : pos
1361 * - 8..15 : address
1362 */
1363 address = (bitfield >> 8) & 0xff;
1364
1365 rc = tfa2_i2c_read_reg(client, address); /* will report error */
1366 if (rc < 0)
1367 return rc;
1368 oldvalue = (uint16_t)rc;
1369 newvalue = oldvalue;
1370 tfa2_i2c_set_bf_value(bitfield, value, &newvalue);
1371
1372 /* Only write when the current register value is not the same as the new value */
1373 if (write_always || (oldvalue != newvalue))
1374 return tfa2_i2c_write_reg(client, (bitfield >> 8) & 0xff, newvalue);
1375 return 0;
1376 }
1377
tfa2_i2c_unlock(struct i2c_client * client)1378 void tfa2_i2c_unlock(struct i2c_client *client)
1379 {
1380 uint16_t value, xor;
1381
1382 /* Unlock keys */
1383 tfa2_i2c_write_reg(client, 0x0F, 0x5A6B);
1384 value = tfa2_i2c_read_reg(client, 0xFB);
1385 xor = value ^ 0x005A;
1386 tfa2_i2c_write_reg(client, 0xA0, xor);
1387 }
1388
tfa2_i2c_write_bf(struct i2c_client * client,uint16_t bitfield,uint16_t value)1389 int tfa2_i2c_write_bf(struct i2c_client *client, uint16_t bitfield, uint16_t value)
1390 {
1391 return tfa2_i2c_write_bf_internal(client, bitfield, value, 0);
1392 }
1393
tfa2_i2c_write_bf_volatile(struct i2c_client * client,uint16_t bitfield,uint16_t value)1394 int tfa2_i2c_write_bf_volatile(struct i2c_client *client, uint16_t bitfield, uint16_t value)
1395 {
1396 return tfa2_i2c_write_bf_internal(client, bitfield, value, 1);
1397 }
1398
1399 /******************************************************************************
1400 * DSP related functions
1401 */
1402 /**
1403 * @brief convert 24 bit BE DSP messages to a 32 bit signed LE integer
1404 *
1405 * The input is sign extended to 32-bit from 24-bit.
1406 *
1407 * @param data32 output 32 bit signed LE integer buffer
1408 * @param data24 input 24 bit BE buffer
1409 * @param length_bytes24 bytes in 24 bit BE buffer
1410 * @return total nr of bytes in the result
1411 */
tfa2_24_to_32(int32_t * data32,uint8_t * data24,int length_bytes24)1412 int tfa2_24_to_32(int32_t *data32, uint8_t *data24, int length_bytes24)
1413 {
1414 int i, idx = 0;
1415
1416 for (i = 0; i < length_bytes24; i += 3)
1417 {
1418 int tmp = ((uint8_t)data24[i] << 16) + ((uint8_t)data24[i + 1] << 8) + (uint8_t)data24[i + 2];
1419 /* Sign extend to 32-bit from 24-bit */
1420 data32[idx++] = ((int32_t)tmp << 8) >> 8;
1421 }
1422 return idx;
1423 }
1424
1425 /**
1426 * @brief truncate 32 bit integer buffer to 24 bit BE
1427 *
1428 * The input is truncated by chopping the highest byte.
1429 * @param data24 output 24 bit BE buffer
1430 * @param data32 input 32 bit signed LE integer buffer
1431 * @param length_words32 number of words in 32bit buffer
1432 * @return total nr of bytes in the result
1433 */
tfa2_32_to_24(uint8_t * data24,int32_t * data32,int length_words32)1434 int tfa2_32_to_24(uint8_t *data24, int32_t *data32, int length_words32)
1435 {
1436 int i, idx = 0;
1437
1438 for (i = 0; i < length_words32; i++)
1439 {
1440 uint8_t *buf8 = (uint8_t *)&data32[i];
1441 data24[idx++] = buf8[2];
1442 data24[idx++] = buf8[1];
1443 data24[idx++] = buf8[0];
1444 }
1445 return idx;
1446 }
1447
1448 enum tfa2_cf_flags
1449 {
1450 convert = 1,
1451 dsp_reset = 2,
1452 };
1453
1454 /* implement functionality for tfa2_i2c_write_cf_mem24() and tfa2_i2c_write_cf_mem32() */
write_cf_mem(struct i2c_client * client,uint16_t address,int32_t * input,int size,enum tfa2_cf_mem type,enum tfa2_cf_flags flags)1455 static int write_cf_mem(struct i2c_client *client,
1456 uint16_t address,
1457 int32_t *input,
1458 int size,
1459 enum tfa2_cf_mem type,
1460 enum tfa2_cf_flags flags)
1461 {
1462 int idx = 0;
1463 uint8_t *output;
1464 int rc;
1465
1466 output = kmalloc(5 + size * 3, GFP_KERNEL);
1467 if (!output)
1468 return -ENOMEM;
1469
1470 output[idx++] = 0x90; /* CF_CONTROLS */
1471 output[idx++] = 0x00;
1472 if (flags & dsp_reset)
1473 {
1474 output[idx++] = (type << 1) | 1; /* AIF:0 (ON) DMEM:1 (xmem) RST:1 */
1475 }
1476 else
1477 {
1478 output[idx++] = (type << 1); /* AIF:0 (ON) DMEM:1 (xmem) RST:0 */
1479 }
1480 output[idx++] = (address >> 8) & 0xff;
1481 output[idx++] = address & 0xff;
1482
1483 if (flags & convert)
1484 {
1485 idx += tfa2_32_to_24(&output[idx], input, size);
1486 }
1487 else
1488 {
1489 memcpy(&output[idx], input, size * 3);
1490 idx += size * 3;
1491 }
1492
1493 rc = tfa2_i2c_write_raw(client, idx, output);
1494 if (rc < 0)
1495 {
1496 dev_err(&client->dev, "%s failed\n", __FUNCTION__);
1497 }
1498
1499 kfree(output);
1500
1501 return rc;
1502 }
1503
tfa2_i2c_write_cf_mem24(struct i2c_client * client,uint16_t address,uint8_t * input,int size,enum tfa2_cf_mem type)1504 int tfa2_i2c_write_cf_mem24(
1505 struct i2c_client *client, uint16_t address, uint8_t *input, int size, enum tfa2_cf_mem type)
1506 {
1507 return write_cf_mem(client, address, (int32_t *)input, size / 3, type, (enum tfa2_cf_flags)0);
1508 }
1509
tfa2_i2c_write_cf_mem32(struct i2c_client * client,uint16_t address,int32_t * input,int size,enum tfa2_cf_mem type)1510 int tfa2_i2c_write_cf_mem32(
1511 struct i2c_client *client, uint16_t address, int32_t *input, int size, enum tfa2_cf_mem type)
1512 {
1513 return write_cf_mem(client, address, input, size, type, convert);
1514 }
1515
tfa2_i2c_write_cf_mem32_dsp_reset(struct i2c_client * client,uint16_t address,int32_t * data,int size,enum tfa2_cf_mem type)1516 int tfa2_i2c_write_cf_mem32_dsp_reset(
1517 struct i2c_client *client, uint16_t address, int32_t *data, int size, enum tfa2_cf_mem type)
1518 {
1519 return write_cf_mem(client, address, data, size, type, (enum tfa2_cf_flags)(convert | dsp_reset));
1520 }
1521
1522 /* implement functionality for tfa2_i2c_read_cf_mem24() and tfa2_i2c_read_cf_mem32() */
read_cf_mem(struct i2c_client * client,uint16_t address,int * data,int size,enum tfa2_cf_mem type,enum tfa2_cf_flags flags)1523 static int read_cf_mem(
1524 struct i2c_client *client, uint16_t address, int *data, int size, enum tfa2_cf_mem type, enum tfa2_cf_flags flags)
1525 {
1526 int rc;
1527 uint8_t output[5];
1528 uint8_t *data24;
1529
1530 data24 = kmalloc(size * 3, GFP_KERNEL);
1531 if (!data24)
1532 return -ENOMEM;
1533
1534 output[0] = 0x90; /* CF_CONTROLS */
1535 output[1] = 0x00;
1536 if (flags & dsp_reset)
1537 {
1538 output[2] = (type << 1) | 1; /* AIF:0 (ON) DMEM:1 (xmem) RST:1 */
1539 }
1540 else
1541 {
1542 output[2] = (type << 1); /* AIF:0 (ON) DMEM:1 (xmem) RST:0 */
1543 }
1544 output[3] = (address >> 8) & 0xff;
1545 output[4] = address & 0xff;
1546 rc = tfa2_i2c_write_read_raw(client, 5, output, size * 3, data24);
1547 if (rc < 0)
1548 goto error;
1549
1550 if (flags & convert)
1551 {
1552 tfa2_24_to_32((int32_t *)data, data24, size * 3);
1553 }
1554 else
1555 {
1556 memcpy(data, data24, size * 3);
1557 }
1558 error:
1559 kfree(data24);
1560
1561 if (rc < 0)
1562 {
1563 dev_err(&client->dev, "%s failed\n", __FUNCTION__);
1564 }
1565
1566 return rc;
1567 }
1568
tfa2_i2c_read_cf_mem24(struct i2c_client * client,uint16_t address,uint8_t * data,int size,enum tfa2_cf_mem type)1569 int tfa2_i2c_read_cf_mem24(struct i2c_client *client, uint16_t address, uint8_t *data, int size, enum tfa2_cf_mem type)
1570 {
1571 return read_cf_mem(client, address, (int *)data, size / 3, type, (enum tfa2_cf_flags)0);
1572 }
1573
tfa2_i2c_read_cf_mem32(struct i2c_client * client,uint16_t address,int * data,int size,enum tfa2_cf_mem type)1574 int tfa2_i2c_read_cf_mem32(struct i2c_client *client, uint16_t address, int *data, int size, enum tfa2_cf_mem type)
1575 {
1576 return read_cf_mem(client, address, data, size, type, convert);
1577 }
1578
tfa2_i2c_read_cf_mem32_dsp_reset(struct i2c_client * client,uint16_t address,int * data,int size,enum tfa2_cf_mem type)1579 int tfa2_i2c_read_cf_mem32_dsp_reset(
1580 struct i2c_client *client, uint16_t address, int *data, int size, enum tfa2_cf_mem type)
1581 {
1582 return read_cf_mem(client, address, data, size, type, (enum tfa2_cf_flags)(convert | dsp_reset));
1583 }
1584
1585 /****************************** calibration support **************************/
1586
1587 /***** mtp manual write/auto read *************/
tfa2_dev_mtp_busy(struct tfa2_device * tfa)1588 int tfa2_dev_mtp_busy(struct tfa2_device *tfa)
1589 {
1590 int rc;
1591 int count = 0;
1592 msleep_interruptible(20); // TODO address sleeptime
1593 while (count < 10)
1594 {
1595 msleep_interruptible(10);
1596 rc = tfa2_i2c_bf_poll(tfa->i2c, tfa->bf_mtpb, 0, 100); // TODO mtpbusy max poll time
1597 count++;
1598 }
1599
1600 if (rc < 0)
1601 dev_err(&tfa->i2c->dev, "MTP busy poll timed out\n");
1602 else
1603 dev_dbg(&tfa->i2c->dev, "MTP not busy eventually\n");
1604
1605 return rc;
1606 }
1607 /************************************************************************/
1608 /**
1609 * Function MTP_UpdateI2C.
1610 *
1611 * Read all the I2C 'volatile' registers from MTP bank.
1612 *
1613 * @param [in] wait : .
1614 * @return .
1615 */
1616 /************************************************************************/
1617
tfa2_dev_mtp_to_i2c(struct tfa2_device * tfa)1618 int tfa2_dev_mtp_to_i2c(struct tfa2_device *tfa)
1619 {
1620 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_CMTPI, 1);
1621 return tfa2_dev_mtp_busy(tfa);
1622 }
1623
1624 /************************************************************************/
1625 /**
1626 * Function MTP_ReadPair.
1627 *
1628 * Read a pair of words from MTP.
1629 *
1630 * @param [in] mtp_address : MTP address where to read from 0
1631 * ( range from to 15 ).
1632 * @param [out] mtp_data : Content of the MTP's at requested address.
1633 * @return
1634 */
1635 /************************************************************************/
1636
tfa2_dev_mtp_readpair(struct tfa2_device * tfa,uint16_t mtp_address,uint16_t mtp_data[2])1637 int tfa2_dev_mtp_readpair(struct tfa2_device *tfa, uint16_t mtp_address, uint16_t mtp_data[2])
1638 {
1639 int rc;
1640
1641 /* Program the address */
1642 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MTPADDR, mtp_address >> 1);
1643 // msleep_interruptible(50);
1644 /* Launch the copy from MTP */
1645 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MANCMTPI, 1);
1646 rc = tfa2_dev_mtp_busy(tfa);
1647 if (rc < 0)
1648 return rc;
1649 mtp_data[0] = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MTPRDLSB);
1650 mtp_data[1] = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MTPRDMSB);
1651 dev_dbg(&tfa->i2c->dev, "%s MTP[%d]: 0x%04x 0x%04x\n", __func__, mtp_address & 0x0f, mtp_data[1], mtp_data[0]);
1652
1653 return 0;
1654 }
1655
1656 /************************************************************************/
1657 /**
1658 * Function MTP_Read.
1659 *
1660 * Read one word from MTP.
1661 *
1662 * @param [in] mtp_address : MTP address where to read from
1663 * ( range from 0 to 15 ).
1664 * @return Content of the MTP at requested address.
1665 */
1666 /************************************************************************/
1667
tfa2_dev_mtp_read(struct tfa2_device * tfa,uint16_t mtp_address)1668 int tfa2_dev_mtp_read(struct tfa2_device *tfa, uint16_t mtp_address)
1669 {
1670 uint16_t mtp_data[2];
1671
1672 tfa2_dev_mtp_readpair(tfa, mtp_address, mtp_data);
1673 return mtp_data[mtp_address & 0x1];
1674 }
1675
1676 /************************************************************************/
1677 /**
1678 * Function MTP_WritePair.
1679 *
1680 * Write a pair of words to MTP.
1681 *
1682 * @param [in] mtp_address : MTP Address where to write to
1683 * ( range from 0 to 15 ).
1684 * @param [in] mtp_data : Data to be written.
1685 * @return .
1686 */
1687 /************************************************************************/
1688
tfa2_dev_mtp_writepair(struct tfa2_device * tfa,uint16_t mtp_address,uint16_t mtp_data[2])1689 int tfa2_dev_mtp_writepair(struct tfa2_device *tfa, uint16_t mtp_address, uint16_t mtp_data[2])
1690 {
1691 int rc;
1692
1693 /* Program the address */
1694 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MTPADDR, mtp_address >> 1);
1695 /* Program the data */
1696 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MTPWRLSB, mtp_data[0]);
1697 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MTPWRMSB, mtp_data[1]);
1698 // msleep_interruptible(50);
1699 /* Launch the copy to MTP */
1700 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_MANCIMTP, 1);
1701 rc = tfa2_dev_mtp_busy(tfa);
1702 if (rc < 0)
1703 return rc;
1704
1705 dev_dbg(&tfa->i2c->dev, "%s MTP[%d]: 0x%04x 0x%04x\n", __func__, mtp_address & 0x0f, mtp_data[1], mtp_data[0]);
1706
1707 return tfa2_dev_mtp_to_i2c(tfa);
1708 }
1709
1710 /************************************************************************/
1711 /**
1712 * Function MTP_Write.
1713 *
1714 * Write one word to MTP.
1715 *
1716 * @param [in] mtp_address : MTP Address where to write to
1717 * ( range from 0 to 15 ).
1718 * @param [in] mtp_value : Data to be written.
1719 * @return .
1720 */
1721 /************************************************************************/
1722
tfa2_dev_mtp_write(struct tfa2_device * tfa,uint16_t mtp_address,uint16_t mtp_value)1723 int tfa2_dev_mtp_write(struct tfa2_device *tfa, uint16_t mtp_address, uint16_t mtp_value)
1724 {
1725 uint16_t mtp_data[2];
1726 int rc;
1727
1728 /* Program the address */
1729 rc = tfa2_dev_mtp_readpair(tfa, mtp_address, mtp_data);
1730 if (rc < 0)
1731 return rc; /* Program the data */
1732 mtp_data[mtp_address & 0x1] = mtp_value;
1733 /* Launch the copy to MTP */
1734 return tfa2_dev_mtp_writepair(tfa, mtp_address, mtp_data);
1735 }
1736
1737 /************************************************************************/
1738
1739 /*
1740 * get/set the mtp with user controllable values
1741 *
1742 * check if the relevant clocks are available
1743 */
get_mtp(struct tfa2_device * tfa,uint16_t addr,uint16_t * value)1744 static int get_mtp(struct tfa2_device *tfa, uint16_t addr, uint16_t *value)
1745 {
1746 int rc;
1747 struct i2c_client *i2c = tfa->i2c;
1748
1749 rc = tfa2_dev_clock_stable_wait(tfa);
1750 if (rc < 0)
1751 {
1752 dev_err(&i2c->dev, "no clock\n");
1753 return rc;
1754 }
1755
1756 rc = tfa2_i2c_read_reg(i2c, addr);
1757 if (rc < 0)
1758 {
1759 dev_err(&i2c->dev, "error reading MTP (0x%x)\n", addr);
1760 return rc;
1761 }
1762 *value = (uint16_t)rc;
1763
1764 return rc;
1765 }
1766
1767 /*
1768 * lock or unlock KEY2
1769 * lock = 1 will lock
1770 * lock = 0 will unlock
1771 *
1772 * note that on return all the hidden key will be off
1773 */
tfa2_i2c_hap_key2(struct i2c_client * i2c,int lock)1774 int tfa2_i2c_hap_key2(struct i2c_client *i2c, int lock)
1775 {
1776 int rc;
1777 uint16_t addr = (TFA9XXX_BF_MTPK >> 8) & 0xff;
1778
1779 /* unhide lock registers */
1780 rc = tfa2_i2c_write_reg(i2c, 0x0F, 0x5A6B);
1781 if (rc < 0)
1782 return -EIO;
1783 /* lock/unlock key2 MTPK */
1784 if (lock)
1785 {
1786 rc = tfa2_i2c_write_reg(i2c, addr, 0); /* lock */
1787 if (rc < 0)
1788 return -EIO;
1789 /* hide lock registers */
1790 rc = tfa2_i2c_write_reg(i2c, 0x0F, 0);
1791 if (rc < 0)
1792 return -EIO;
1793 }
1794 else
1795 {
1796 rc = tfa2_i2c_write_reg(i2c, addr, 0x5A); /* unlock */
1797 if (rc < 0)
1798 return -EIO;
1799 }
1800
1801 return 0;
1802 }
1803
mtp_open(struct tfa2_device * tfa,int state)1804 static int mtp_open(struct tfa2_device *tfa, int state)
1805 {
1806 /* FAIM protection */
1807 dev_dbg(&tfa->i2c->dev, "MTP %s\n", state ? "enabled" : "disabled");
1808 return tfa2_i2c_write_bf(tfa->i2c, tfa->bf_openmtp, state);
1809 }
1810
set_mtp(struct tfa2_device * tfa,uint16_t bf,uint16_t value)1811 static int set_mtp(struct tfa2_device *tfa, uint16_t bf, uint16_t value)
1812 {
1813 uint16_t mtp_old, mtp_new, mtp_value;
1814 int rc;
1815 int save_state;
1816
1817 /*
1818 * bitfield enum:
1819 * - 0..3 : len
1820 * - 4..7 : pos
1821 * - 8..15 : address
1822 */
1823 uint8_t len = bf & 0x0f;
1824 uint8_t pos = (bf >> 4) & 0x0f;
1825 uint8_t addr = (bf >> 8) & 0xff;
1826 uint16_t msk = ((1 << (len + 1)) - 1) << pos;
1827
1828 /* execute the MTP writes in init_cf state */
1829 save_state = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate);
1830
1831 /* Go to the initCF state in mute */
1832 rc = tfa2_dev_set_state(tfa, TFA_STATE_INIT_CF);
1833 if (rc < 0)
1834 return rc;
1835
1836 /* open mtp */
1837 rc = mtp_open(tfa, 1);
1838 if (rc < 0)
1839 {
1840 return rc;
1841 }
1842
1843 rc = get_mtp(tfa, addr, &mtp_old);
1844 if (rc < 0)
1845 return rc;
1846
1847 mtp_value = value << pos;
1848 mtp_new = (mtp_value & msk) | (mtp_old & ~msk);
1849
1850 if (mtp_old == mtp_new)
1851 { /* no change */
1852 dev_dbg(&tfa->i2c->dev, "MTP 0x%02x: no change\n", addr);
1853 goto restore_state;
1854 }
1855
1856 dev_dbg(&tfa->i2c->dev, "MTP 0x%02x: writing 0x%x\n", addr, mtp_new);
1857
1858 /* do the write */
1859 rc = tfa2_init_mtp_write_wrapper(tfa, addr, mtp_new, tfa2_dev_mtp_write);
1860 if (rc < 0)
1861 {
1862 dev_err(&tfa->i2c->dev, "error writing MTP: 0x%02x 0x%04x\n", addr, mtp_new);
1863 }
1864
1865 restore_state:
1866 /* close mtp */
1867 rc = mtp_open(tfa, 0);
1868 if (rc < 0)
1869 {
1870 dev_err(&tfa->i2c->dev, "not able to enable protection\n");
1871 return rc;
1872 }
1873
1874 /* restore state */
1875 rc = tfa2_dev_set_state(tfa, (save_state == 6) ? TFA_STATE_INIT_CF : TFA_STATE_POWERDOWN);
1876 if (rc < 0)
1877 return rc;
1878 return 0;
1879 }
1880
1881 /* will return EIO error if no clock */
tfa2_dev_mtp_get(struct tfa2_device * tfa,enum tfa_mtp item)1882 int tfa2_dev_mtp_get(struct tfa2_device *tfa, enum tfa_mtp item)
1883 {
1884 int rc, clock;
1885
1886 clock = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_clks);
1887 if (!clock)
1888 {
1889 rc = tfa2_dev_set_state(tfa, TFA_STATE_OSC);
1890 if (rc < 0)
1891 return rc;
1892 }
1893
1894 /* copy MTP to I2C shadow regs */
1895 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_CMTPI, 1);
1896
1897 /* return error if there is no clock */
1898 if (tfa2_i2c_read_bf(tfa->i2c, tfa->bf_clks) == 0)
1899 return -EIO;
1900
1901 rc = tfa2_dev_mtp_busy(tfa);
1902 if (rc < 0)
1903 goto restore;
1904
1905 switch (item)
1906 {
1907 case TFA_MTP_OTC:
1908 rc = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MTPOTC);
1909 break;
1910 case TFA_MTP_EX:
1911 rc = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_MTPEX);
1912 break;
1913 case TFA_MTP_R25C:
1914 rc = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_r25c);
1915 break;
1916 case TFA_MTP_F0:
1917 rc = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_CUSTINFO);
1918 break;
1919 case TFA_MTP_OPEN:
1920 rc = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_openmtp);
1921 break;
1922 default:
1923 rc = -EINVAL;
1924 break;
1925 }
1926
1927 restore:
1928 /* restore state */
1929 if (!clock)
1930 {
1931 rc = tfa2_dev_set_state(tfa, TFA_STATE_POWERDOWN);
1932 }
1933
1934 return rc;
1935 }
1936 #ifdef MTP_READ_MANCOPY
tfa2_dev_mtp_get(struct tfa2_device * tfa,enum tfa_mtp item)1937 int tfa2_dev_mtp_get(struct tfa2_device *tfa, enum tfa_mtp item)
1938 {
1939 int rc = -EINVAL;
1940 int mtp_addr, value;
1941
1942 switch (item)
1943 {
1944 case TFA_MTP_OTC:
1945 mtp_addr = (TFA9XXX_BF_MTPOTC >> 8) & 0x0f;
1946 value = tfa2_i2c_mtp_read(tfa->i2c, mtp_addr);
1947 rc = tfa2_i2c_get_bf_value(TFA9XXX_BF_MTPOTC, value);
1948 break;
1949 case TFA_MTP_EX:
1950 mtp_addr = (TFA9XXX_BF_MTPEX >> 8) & 0x0f;
1951 value = tfa2_i2c_mtp_read(tfa->i2c, mtp_addr);
1952 rc = tfa2_i2c_get_bf_value(TFA9XXX_BF_MTPEX, value);
1953 break;
1954 case TFA_MTP_R25C:
1955 mtp_addr = (tfa->bf_r25c >> 8) & 0x0f;
1956 value = tfa2_i2c_mtp_read(tfa->i2c, mtp_addr);
1957 rc = tfa2_i2c_get_bf_value(tfa->bf_r25c, value);
1958 break;
1959 case TFA_MTP_F0:
1960 mtp_addr = (TFA9XXX_BF_CUSTINFO >> 8) & 0x0f;
1961 value = tfa2_i2c_mtp_read(tfa->i2c, mtp_addr);
1962 rc = tfa2_i2c_get_bf_value(TFA9XXX_BF_CUSTINFO, value);
1963 break;
1964 case TFA_MTP_OPEN:
1965 break;
1966 }
1967
1968 return rc;
1969 }
1970 #endif
tfa2_dev_mtp_set(struct tfa2_device * tfa,enum tfa_mtp item,uint16_t value)1971 int tfa2_dev_mtp_set(struct tfa2_device *tfa, enum tfa_mtp item, uint16_t value)
1972 {
1973 int rc;
1974
1975 switch (item)
1976 {
1977 case TFA_MTP_OTC:
1978 rc = set_mtp(tfa, TFA9XXX_BF_MTPOTC, value);
1979 break;
1980 case TFA_MTP_EX:
1981 rc = set_mtp(tfa, TFA9XXX_BF_MTPEX, value);
1982 break;
1983 case TFA_MTP_R25C:
1984 rc = set_mtp(tfa, tfa->bf_r25c, value);
1985 break;
1986 case TFA_MTP_F0:
1987 rc = set_mtp(tfa, TFA9XXX_BF_CUSTINFO, value);
1988 break;
1989 case TFA_MTP_OPEN:
1990 rc = mtp_open(tfa, value);
1991 break;
1992 default:
1993 rc = -EINVAL;
1994 break;
1995 }
1996
1997 return rc;
1998 }
1999
2000 /* return twos complement */
twos(short x)2001 static inline short twos(short x)
2002 {
2003 return (x < 0) ? x + 512 : x;
2004 }
2005
tfa2_set_exttemp(struct tfa2_device * tfa,short ext_temp)2006 void tfa2_set_exttemp(struct tfa2_device *tfa, short ext_temp)
2007 {
2008 if ((-256 <= ext_temp) && (ext_temp <= 255))
2009 {
2010 /* make twos complement */
2011 dev_dbg(&tfa->i2c->dev, "Using ext temp %d C\n", twos(ext_temp));
2012 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_TROS, 1);
2013 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_EXTTS, twos(ext_temp));
2014 }
2015 else
2016 {
2017 dev_dbg(&tfa->i2c->dev, "Clearing ext temp settings\n");
2018 tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_TROS, 0);
2019 }
2020 }
2021
tfa2_get_exttemp(struct tfa2_device * tfa)2022 short tfa2_get_exttemp(struct tfa2_device *tfa)
2023 {
2024 short ext_temp = (short)tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_EXTTS);
2025 return (twos(ext_temp));
2026 }
2027
2028 /****************** patching **************************************************/
tfa2_process_patch_file(struct i2c_client * client,int length,const uint8_t * bytes)2029 int tfa2_process_patch_file(struct i2c_client *client, int length, const uint8_t *bytes)
2030 {
2031 uint16_t size;
2032 int index = 0;
2033 int error = 0;
2034
2035 dev_dbg(&client->dev, "patch length is %d bytes\n", length);
2036
2037 while (index + 1 < length)
2038 {
2039 size = bytes[index] + bytes[index + 1] * 256;
2040 index += 2;
2041 if ((index + size) > length)
2042 {
2043 /* outside the buffer, error in the input data */
2044 return -EINVAL;
2045 }
2046
2047 error = tfa2_i2c_write_raw(client, size, &bytes[index]);
2048 if (error != 0)
2049 break;
2050 index += size;
2051 }
2052
2053 return error;
2054 }
2055
tfa2_check_patch(const uint8_t * data,const int length,const uint16_t revid)2056 int tfa2_check_patch(const uint8_t *data, const int length, const uint16_t revid)
2057 {
2058 struct tfa_patch_header *hdr = (struct tfa_patch_header *)data;
2059 uint32_t crc;
2060 uint8_t *ptr;
2061 size_t size;
2062
2063 if (data == NULL)
2064 {
2065 pr_err("NULL pointer\n");
2066 return -EINVAL;
2067 }
2068
2069 if (length < sizeof(struct tfa_patch_header))
2070 {
2071 pr_err("Invalid patch file length: %d\n", length);
2072 return -EINVAL;
2073 }
2074
2075 if (hdr->size < sizeof(struct tfa_patch_header))
2076 {
2077 pr_err("Invalid patch size (header): %d\n", hdr->size);
2078 return -EINVAL;
2079 }
2080
2081 if (hdr->size > length)
2082 {
2083 pr_err("Invalid patch size (length): %d\n", hdr->size);
2084 return -EINVAL;
2085 }
2086
2087 if (hdr->id != le16_to_cpu('A' << 8 | 'P'))
2088 {
2089 pr_err("Invalid id\n");
2090 return -EINVAL;
2091 }
2092
2093 if (strncmp(hdr->version, "1_", 2))
2094 {
2095 pr_err("Invalid version\n");
2096 return -EINVAL;
2097 }
2098
2099 if (strncmp(hdr->subversion, "00", 2))
2100 {
2101 pr_err("Invalid subversion\n");
2102 return -EINVAL;
2103 }
2104
2105 /* crc is calulated over the data following the crc field */
2106 ptr = (uint8_t *)hdr + offsetof(struct tfa_patch_header, crc) + sizeof(hdr->crc);
2107 size = hdr->size - (ptr - data);
2108 crc = ~crc32_le(~0u, ptr, size);
2109 if (crc != hdr->crc)
2110 {
2111 pr_err("Invalid crc\n");
2112 return -EINVAL;
2113 }
2114
2115 if (hdr->rev != (revid & 0xff))
2116 {
2117 pr_err("patch file revision check failed: expected: 0x%02x, actual: 0x%02x\n", revid & 0xff, hdr->rev);
2118 return -EINVAL;
2119 }
2120
2121 /* indicate if more data is available */
2122 return (int)(hdr->size < length);
2123 }
2124
2125 /*
2126 * cold start the calibration profile
2127 */
tfa2_calibrate_profile_start(struct tfa2_device * tfa)2128 int tfa2_calibrate_profile_start(struct tfa2_device *tfa)
2129 {
2130 int rc;
2131 int cal_profile;
2132 int count, manstate;
2133
2134 /* force a cold start */
2135 rc = tfa2_dev_force_cold(tfa);
2136 if (rc < 0)
2137 return rc;
2138
2139 /* get SB calibration profile: with .cal extension */
2140 cal_profile = tfa2_cnt_grep_profile_name(tfa->cnt, tfa->dev_idx, ".cal");
2141 if (cal_profile < 0)
2142 {
2143 dev_err(&tfa->i2c->dev, "No [*.cal] profile found for calibration\n");
2144 return -EINVAL;
2145 }
2146
2147 rc = tfa2_dev_start(tfa, cal_profile, 0);
2148 if (rc < 0)
2149 {
2150 dev_dbg(&tfa->i2c->dev, "%s : error when starting device\n", __FUNCTION__);
2151 return rc;
2152 }
2153
2154 /* wait until we are in operating state */
2155 manstate = 0;
2156 count = 20;
2157 while ((manstate != 9) && (count > 0))
2158 {
2159 msleep_interruptible(1);
2160 manstate = tfa2_i2c_read_bf(tfa->i2c, tfa->bf_manstate);
2161 if (manstate < 0)
2162 return manstate; /* error */
2163 count--;
2164 }
2165 if (count == 0)
2166 {
2167 dev_dbg(&tfa->i2c->dev, "Device is not in operating state, can't calibrate!\n");
2168 return -EIO;
2169 }
2170
2171 return 0;
2172 }
2173 // CalibrateDone = xmem[516]
2174 /****************************** speakerboost calibration **************************/
tfa2_sb_calibrate_ackwait(struct tfa2_device * tfa)2175 static int tfa2_sb_calibrate_ackwait(struct tfa2_device *tfa)
2176 {
2177 int loop = 50, ready = 0;
2178
2179 do
2180 {
2181 ready = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_ACKCAL);
2182 if (ready == 1)
2183 break;
2184 else if (ready < 0)
2185 return -EIO;
2186 msleep_interruptible(50); /* wait to avoid busload */
2187 } while (loop--);
2188
2189 return 0;
2190 }
2191
tfa2_sb_calibrate(struct tfa2_device * tfa)2192 int tfa2_sb_calibrate(struct tfa2_device *tfa)
2193 {
2194 int rc;
2195 int sbcal_profile, current_profile, always;
2196 int current_mute = 0;
2197 int cf_enabled;
2198
2199 /* get SB calibration profile: with .cal extension */
2200 sbcal_profile = tfa2_cnt_grep_profile_name(tfa->cnt, tfa->dev_idx, ".cal");
2201 if (sbcal_profile < 0)
2202 {
2203 dev_err(&tfa->i2c->dev, "No [*.cal] profile found for calibration\n");
2204 return -EINVAL;
2205 }
2206
2207 rc = tfa2_dev_mtp_get(tfa, TFA_MTP_OTC);
2208 if (rc < 0)
2209 return rc;
2210
2211 always = !rc; /* OTC==1 if once */
2212
2213 current_profile = tfa2_dev_get_swprofile(tfa);
2214 if (current_profile < 0)
2215 {
2216 /* no current profile, take the 1st profile */
2217 current_profile = 0;
2218 }
2219
2220 cf_enabled = tfa2_dev_cf_enabled(tfa);
2221 if (cf_enabled)
2222 {
2223 rc = tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_CFSM);
2224 if (rc < 0)
2225 return rc;
2226 current_mute = rc;
2227 }
2228
2229 /* force a cold start */
2230 rc = tfa2_dev_force_cold(tfa);
2231 if (rc < 0)
2232 return rc;
2233
2234 /* start hw & fw, no speakerboost */
2235
2236 /* start hardware: init tfa registers and start PLL */
2237 rc = tfa2_dev_start_hw(tfa, sbcal_profile); /* return muted in initcf state */
2238 if (rc < 0)
2239 {
2240 dev_dbg(&tfa->i2c->dev, "%s : error when starting hardware\n", __FUNCTION__);
2241 return rc;
2242 }
2243
2244 /* start CoolFlux DSP subsystem, will check if clock is there */
2245 rc = tfa2_dev_start_cf(tfa);
2246 if (rc < 0)
2247 return rc;
2248
2249 if (!always)
2250 {
2251 /* open key2 */
2252 tfa2_i2c_hap_key2(tfa->i2c, 0);
2253
2254 /* open mtp */
2255 tfa2_dev_mtp_set(tfa, TFA_MTP_OPEN, 1);
2256 }
2257
2258 /* start with speakerboost only */
2259 rc = tfa2_dev_start(tfa, sbcal_profile, 0);
2260
2261 if (rc == 0 && tfa2_sb_calibrate_ackwait(tfa))
2262 {
2263 dev_err(&tfa->i2c->dev, "Eror: calibration timed out\n");
2264 rc = -EIO; // TODO get proper timeout errno
2265 }
2266
2267 if (!always)
2268 {
2269 /* close key2 */
2270 tfa2_i2c_hap_key2(tfa->i2c, 1);
2271
2272 /* close mtp */
2273 tfa2_dev_mtp_set(tfa, TFA_MTP_OPEN, 0);
2274 }
2275
2276 if (rc >= 0)
2277 {
2278 dev_dbg(&tfa->i2c->dev, "%s : RE25 = %d mohm\n", __FUNCTION__, tfa2_get_calibration_impedance(tfa));
2279
2280 /* re-load current profile and restore CF mute */
2281 rc = tfa2_dev_start(tfa, current_profile, 0);
2282 if ((rc >= 0) && cf_enabled)
2283 {
2284 rc = tfa2_i2c_write_bf(tfa->i2c, TFA9XXX_BF_CFSM, current_mute);
2285 }
2286 }
2287
2288 return rc;
2289 }
2290
tfa2_get_calibration_impedance(struct tfa2_device * tfa)2291 int tfa2_get_calibration_impedance(struct tfa2_device *tfa)
2292 {
2293 int mohm, fixed, ret;
2294 uint8_t buf[9];
2295
2296 memset(buf, 0, 9);
2297
2298 ret = tfa2dsp_fw_get_re25(tfa, buf);
2299 if (ret < 0)
2300 {
2301 dev_err(&tfa->i2c->dev, "%s: error when trying to read Re25\n", __func__);
2302 return ret;
2303 }
2304
2305 fixed = buf[6] << 16 | buf[7] << 8 | buf[8];
2306 mohm = 1000 * fixed / TFA2_FW_ReZ_SCALE;
2307
2308 return mohm;
2309 }
2310
2311 /********************** firmware info get ************************************/
tfa2dsp_fw_get_re25(struct tfa2_device * tfa,uint8_t * buffer)2312 int tfa2dsp_fw_get_re25(struct tfa2_device *tfa, uint8_t *buffer)
2313 {
2314 int command_length = 3;
2315 int result_length = 9;
2316 char *pbuf = (char *)buffer;
2317 int rc;
2318
2319 *pbuf++ = 4; // channel configuration bits (SC|DS|DP|DC)
2320 *pbuf++ = MODULE_SPEAKERBOOST + 0x80;
2321 *pbuf++ = SB_PARAM_GET_RE25C;
2322
2323 // hal_error = tfadsp_writeread(tfa, command_length, buffer, result_length);
2324 rc = tfa->dsp_execute(tfa, (const char *)buffer, command_length, (char *)buffer, result_length);
2325
2326 return rc;
2327 }
2328 #if 0 // TODO fix tfadsp_writeread
2329 int tfa2dsp_fw_get_api_version(struct tfa2_device *tfa, uint8_t *buffer) {
2330
2331 int command_length = 3;
2332 int result_length = 6;
2333 uint8_t *pbuf = buffer;
2334 int hal_error;
2335
2336 *pbuf++ = 0;
2337 *pbuf++ = MODULE_FRAMEWORK + 0x80;
2338 *pbuf++ = FW_PAR_ID_GET_API_VERSION;
2339
2340 hal_error = tfadsp_writeread(tfa, command_length, buffer, result_length);
2341
2342 if ( hal_error != 0)
2343 return hal_error * -1;
2344
2345 return 6;
2346 }
2347 int tfa2dsp_fw_get_status_change(struct tfa2_device *tfa, uint8_t *buffer) {
2348
2349 int command_length = 3;
2350 int result_length = 9;
2351 uint8_t *pbuf = buffer;
2352 int hal_error;
2353
2354 *pbuf++ = 0;
2355 *pbuf++ = MODULE_FRAMEWORK + 0x80;
2356 *pbuf++ = FW_PAR_ID_GET_STATUS_CHANGE;
2357
2358 hal_error = tfadsp_writeread(tfa, command_length, buffer, result_length);
2359
2360 if ( hal_error != 0)
2361 return hal_error * -1;
2362
2363 return result_length;
2364 }
2365 int tfa2dsp_fw_get_tag(struct tfa2_device *tfa, uint8_t *buffer) {
2366
2367 int command_length = 3;
2368 int result_length = FW_MAXTAG+3;
2369 uint8_t *pbuf = buffer;
2370 int hal_error;
2371
2372 *pbuf++ = 0;
2373 *pbuf++ = MODULE_FRAMEWORK + 0x80;
2374 *pbuf++ = FW_PAR_ID_GET_TAG;
2375
2376 hal_error = tfadsp_writeread(tfa, command_length, buffer, result_length);
2377
2378 if ( hal_error != 0)
2379 return hal_error * -1;
2380
2381 return 6;
2382 }
2383 #endif
2384
2385 #define BF_REG(bitfield) ((bitfield >> 8) & 0xff)
2386
tfa2_dev_status(struct tfa2_device * tfa)2387 int tfa2_dev_status(struct tfa2_device *tfa)
2388 {
2389 const int status0 = BF_REG(TFA9XXX_BF_VDDS);
2390 int rc, err, i;
2391 uint16_t status[4];
2392
2393 /* read status registers */
2394 rc = tfa2_i2c_read_regs(tfa->i2c, status0, 4, &status[0]);
2395 if (rc < 0)
2396 return rc;
2397
2398 /*
2399 * check IC status bits: cold start
2400 * and DSP watch dog bit to re init
2401 */
2402 err = 0;
2403 if (tfa2_dev_cf_enabled(tfa))
2404 {
2405 if (tfa2_i2c_get_bf_value(TFA9XXX_BF_ACS, status[0]))
2406 {
2407 dev_err(&tfa->i2c->dev, "ERROR: ACS\n");
2408 err = -ERANGE;
2409 }
2410 if (tfa2_i2c_get_bf_value(TFA9XXX_BF_WDS, status[0]))
2411 {
2412 dev_err(&tfa->i2c->dev, "ERROR: WDS\n");
2413 err = -ERANGE;
2414 }
2415 if (err < 0)
2416 return err;
2417
2418 if (tfa2_i2c_get_bf_value(TFA9XXX_BF_SPKS, status[0]))
2419 dev_err(&tfa->i2c->dev, "ERROR: SPKS\n");
2420 }
2421
2422 for (i = 0; i < 4; i++)
2423 {
2424 err = (status[i] ^ ~tfa->status_err[i]) & tfa->status_mask[i];
2425 if (err)
2426 {
2427 dev_err(&tfa->i2c->dev, "error(s) detected: 0x%x = 0x%x (0x%x)\n", status0 + i, status[i], err);
2428 }
2429 }
2430
2431 return 0;
2432 }
2433
tfa2_dev_set_volume(struct tfa2_device * tfa,uint8_t volume)2434 int tfa2_dev_set_volume(struct tfa2_device *tfa, uint8_t volume)
2435 {
2436 /* Set the new value in the hw register */
2437 return tfa2_i2c_write_bf_volatile(tfa->i2c, TFA9XXX_BF_VOL, volume);
2438 }
2439
tfa2_dev_get_volume(struct tfa2_device * tfa)2440 int tfa2_dev_get_volume(struct tfa2_device *tfa)
2441 {
2442 return tfa2_i2c_read_bf(tfa->i2c, TFA9XXX_BF_VOL);
2443 }
2444
