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Searched defs:sysctrl_t (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-m-3.7.0/platform/ext/target/arm/musca_s1/Device/Include/
Dplatform_regs.h44 struct sysctrl_t { struct
46 volatile uint32_t secdbgstat;
48 volatile uint32_t secdbgset;
50 volatile uint32_t secdbgclr;
52 volatile uint32_t scsecctrl;
54 volatile uint32_t fclk_div;
56 volatile uint32_t sysclk_div;
58 volatile uint32_t clockforce;
60 volatile uint32_t reserved0[57];
62 volatile uint32_t resetsyndrome;
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/arm/musca_b1/Device/Include/
Dplatform_regs.h44 struct sysctrl_t { struct
45 volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
47 volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
49 volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
51 volatile uint32_t scsecctrl; /* (R/W) System Control Security
53 volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
55 volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
57 volatile uint32_t clockforce; /* (R/W) Clock Forces */
58 volatile uint32_t reserved1[57];
59 volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/arm/mps3/an524/device/include/
Dplatform_regs.h40 struct sysctrl_t { struct
41 volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
44 volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
47 volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
50 volatile uint32_t scsecctrl; /* (R/W) System Control Security
53 volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
56 volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
59 volatile uint32_t clockforce; /* (R/W) Clock Forces */
60 volatile uint32_t reserved0[57];
61 volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/arm/mps2/an521/cmsis_core/
Dplatform_regs.h47 struct sysctrl_t { struct
48 volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
50 volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
52 volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
54 volatile uint32_t scsecctrl; /* (R/W) System Control Security
56 volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
58 volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
60 volatile uint32_t clockforce; /* (R/W) Clock Forces */
61 volatile uint32_t reserved0[57];
62 volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
[all …]
/trusted-firmware-m-3.7.0/platform/ext/target/arm/mps2/an519/cmsis_core/
Dplatform_regs.h47 struct sysctrl_t { struct
48 volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
50 volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
52 volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
54 volatile uint32_t reserved0[61];
55 volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
56 volatile uint32_t resetmask; /* (R/W) Reset MASK */
57 volatile uint32_t swreset; /* ( /W) Software Reset */
58 volatile uint32_t gretreg; /* (R/W) General Purpose Retention
60 volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector
[all …]