1 /*
2 * Copyright (c) 2016 BayLibre, SAS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4, STM32WB and
8 * STM32WL
9 *
10 */
11
12 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/kernel.h>
16 #include <soc.h>
17 #include <stm32_ll_i2c.h>
18 #include <errno.h>
19 #include <zephyr/drivers/i2c.h>
20 #include <zephyr/pm/device.h>
21 #include <zephyr/pm/device_runtime.h>
22 #include "i2c_ll_stm32.h"
23
24 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
25 #include <zephyr/logging/log.h>
26 LOG_MODULE_REGISTER(i2c_ll_stm32_v2);
27
28 #include "i2c-priv.h"
29
30 #define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
31
32 #ifdef CONFIG_I2C_STM32_V2_TIMING
33 /* Use the algorithm to calcuate the I2C timing */
34 #ifndef STM32_I2C_VALID_TIMING_NBR
35 #define STM32_I2C_VALID_TIMING_NBR 128U
36 #endif
37 #define STM32_I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */
38 #define STM32_I2C_SPEED_FREQ_FAST 1U /* 400 kHz */
39 #define STM32_I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */
40 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */
41 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */
42 #define STM32_I2C_USE_ANALOG_FILTER 1U
43 #define STM32_I2C_DIGITAL_FILTER_COEF 0U
44 #define STM32_I2C_PRESC_MAX 16U
45 #define STM32_I2C_SCLDEL_MAX 16U
46 #define STM32_I2C_SDADEL_MAX 16U
47 #define STM32_I2C_SCLH_MAX 256U
48 #define STM32_I2C_SCLL_MAX 256U
49
50 /* I2C_DEVICE_Private_Types */
51 struct stm32_i2c_charac_t {
52 uint32_t freq; /* Frequency in Hz */
53 uint32_t freq_min; /* Minimum frequency in Hz */
54 uint32_t freq_max; /* Maximum frequency in Hz */
55 uint32_t hddat_min; /* Minimum data hold time in ns */
56 uint32_t vddat_max; /* Maximum data valid time in ns */
57 uint32_t sudat_min; /* Minimum data setup time in ns */
58 uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */
59 uint32_t hscl_min; /* Minimum high period of SCL clock in ns */
60 uint32_t trise; /* Rise time in ns */
61 uint32_t tfall; /* Fall time in ns */
62 uint32_t dnf; /* Digital noise filter coefficient */
63 };
64
65 struct stm32_i2c_timings_t {
66 uint32_t presc; /* Timing prescaler */
67 uint32_t tscldel; /* SCL delay */
68 uint32_t tsdadel; /* SDA delay */
69 uint32_t sclh; /* SCL high period */
70 uint32_t scll; /* SCL low period */
71 };
72
73 /* I2C_DEVICE Private Constants */
74 static const struct stm32_i2c_charac_t stm32_i2c_charac[] = {
75 [STM32_I2C_SPEED_FREQ_STANDARD] = {
76 .freq = 100000,
77 .freq_min = 80000,
78 .freq_max = 120000,
79 .hddat_min = 0,
80 .vddat_max = 3450,
81 .sudat_min = 250,
82 .lscl_min = 4700,
83 .hscl_min = 4000,
84 .trise = 640,
85 .tfall = 20,
86 .dnf = STM32_I2C_DIGITAL_FILTER_COEF,
87 },
88 [STM32_I2C_SPEED_FREQ_FAST] = {
89 .freq = 400000,
90 .freq_min = 320000,
91 .freq_max = 480000,
92 .hddat_min = 0,
93 .vddat_max = 900,
94 .sudat_min = 100,
95 .lscl_min = 1300,
96 .hscl_min = 600,
97 .trise = 250,
98 .tfall = 100,
99 .dnf = STM32_I2C_DIGITAL_FILTER_COEF,
100 },
101 [STM32_I2C_SPEED_FREQ_FAST_PLUS] = {
102 .freq = 1000000,
103 .freq_min = 800000,
104 .freq_max = 1200000,
105 .hddat_min = 0,
106 .vddat_max = 450,
107 .sudat_min = 50,
108 .lscl_min = 500,
109 .hscl_min = 260,
110 .trise = 60,
111 .tfall = 100,
112 .dnf = STM32_I2C_DIGITAL_FILTER_COEF,
113 },
114 };
115
116 static struct stm32_i2c_timings_t i2c_valid_timing[STM32_I2C_VALID_TIMING_NBR];
117 static uint32_t i2c_valid_timing_nbr;
118 #endif /* CONFIG_I2C_STM32_V2_TIMING */
119
msg_init(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave,uint32_t transfer)120 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
121 uint8_t *next_msg_flags, uint16_t slave,
122 uint32_t transfer)
123 {
124 const struct i2c_stm32_config *cfg = dev->config;
125 struct i2c_stm32_data *data = dev->data;
126 I2C_TypeDef *i2c = cfg->i2c;
127
128 if (LL_I2C_IsEnabledReloadMode(i2c)) {
129 LL_I2C_SetTransferSize(i2c, msg->len);
130 } else {
131 if (I2C_ADDR_10_BITS & data->dev_config) {
132 LL_I2C_SetMasterAddressingMode(i2c,
133 LL_I2C_ADDRESSING_MODE_10BIT);
134 LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave);
135 } else {
136 LL_I2C_SetMasterAddressingMode(i2c,
137 LL_I2C_ADDRESSING_MODE_7BIT);
138 LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave << 1);
139 }
140
141 if (!(msg->flags & I2C_MSG_STOP) && next_msg_flags &&
142 !(*next_msg_flags & I2C_MSG_RESTART)) {
143 LL_I2C_EnableReloadMode(i2c);
144 } else {
145 LL_I2C_DisableReloadMode(i2c);
146 }
147 LL_I2C_DisableAutoEndMode(i2c);
148 LL_I2C_SetTransferRequest(i2c, transfer);
149 LL_I2C_SetTransferSize(i2c, msg->len);
150
151 #if defined(CONFIG_I2C_TARGET)
152 data->master_active = true;
153 #endif
154 LL_I2C_Enable(i2c);
155
156 LL_I2C_GenerateStartCondition(i2c);
157 }
158 }
159
160 #ifdef CONFIG_I2C_STM32_INTERRUPT
161
stm32_i2c_disable_transfer_interrupts(const struct device * dev)162 static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
163 {
164 const struct i2c_stm32_config *cfg = dev->config;
165 struct i2c_stm32_data *data = dev->data;
166 I2C_TypeDef *i2c = cfg->i2c;
167
168 LL_I2C_DisableIT_TX(i2c);
169 LL_I2C_DisableIT_RX(i2c);
170 LL_I2C_DisableIT_STOP(i2c);
171 LL_I2C_DisableIT_NACK(i2c);
172 LL_I2C_DisableIT_TC(i2c);
173
174 if (!data->smbalert_active) {
175 LL_I2C_DisableIT_ERR(i2c);
176 }
177 }
178
stm32_i2c_enable_transfer_interrupts(const struct device * dev)179 static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
180 {
181 const struct i2c_stm32_config *cfg = dev->config;
182 I2C_TypeDef *i2c = cfg->i2c;
183
184 LL_I2C_EnableIT_STOP(i2c);
185 LL_I2C_EnableIT_NACK(i2c);
186 LL_I2C_EnableIT_TC(i2c);
187 LL_I2C_EnableIT_ERR(i2c);
188 }
189
stm32_i2c_master_mode_end(const struct device * dev)190 static void stm32_i2c_master_mode_end(const struct device *dev)
191 {
192 const struct i2c_stm32_config *cfg = dev->config;
193 struct i2c_stm32_data *data = dev->data;
194 I2C_TypeDef *i2c = cfg->i2c;
195
196 stm32_i2c_disable_transfer_interrupts(dev);
197
198 if (LL_I2C_IsEnabledReloadMode(i2c)) {
199 LL_I2C_DisableReloadMode(i2c);
200 }
201
202 #if defined(CONFIG_I2C_TARGET)
203 data->master_active = false;
204 if (!data->slave_attached && !data->smbalert_active) {
205 LL_I2C_Disable(i2c);
206 }
207 #else
208 if (!data->smbalert_active) {
209 LL_I2C_Disable(i2c);
210 }
211 #endif
212 k_sem_give(&data->device_sync_sem);
213 }
214
215 #if defined(CONFIG_I2C_TARGET)
stm32_i2c_slave_event(const struct device * dev)216 static void stm32_i2c_slave_event(const struct device *dev)
217 {
218 const struct i2c_stm32_config *cfg = dev->config;
219 struct i2c_stm32_data *data = dev->data;
220 I2C_TypeDef *i2c = cfg->i2c;
221 const struct i2c_target_callbacks *slave_cb;
222 struct i2c_target_config *slave_cfg;
223
224 if (data->slave_cfg->flags != I2C_TARGET_FLAGS_ADDR_10_BITS) {
225 uint8_t slave_address;
226
227 /* Choose the right slave from the address match code */
228 slave_address = LL_I2C_GetAddressMatchCode(i2c) >> 1;
229 if (data->slave_cfg != NULL &&
230 slave_address == data->slave_cfg->address) {
231 slave_cfg = data->slave_cfg;
232 } else if (data->slave2_cfg != NULL &&
233 slave_address == data->slave2_cfg->address) {
234 slave_cfg = data->slave2_cfg;
235 } else {
236 __ASSERT_NO_MSG(0);
237 return;
238 }
239 } else {
240 /* On STM32 the LL_I2C_GetAddressMatchCode & (ISR register) returns
241 * only 7bits of address match so 10 bit dual addressing is broken.
242 * Revert to assuming single address match.
243 */
244 if (data->slave_cfg != NULL) {
245 slave_cfg = data->slave_cfg;
246 } else {
247 __ASSERT_NO_MSG(0);
248 return;
249 }
250 }
251
252 slave_cb = slave_cfg->callbacks;
253
254 if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
255 uint8_t val;
256
257 if (slave_cb->read_processed(slave_cfg, &val) < 0) {
258 LOG_ERR("Error continuing reading");
259 } else {
260 LL_I2C_TransmitData8(i2c, val);
261 }
262 return;
263 }
264
265 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
266 uint8_t val = LL_I2C_ReceiveData8(i2c);
267
268 if (slave_cb->write_received(slave_cfg, val)) {
269 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
270 }
271 return;
272 }
273
274 if (LL_I2C_IsActiveFlag_NACK(i2c)) {
275 LL_I2C_ClearFlag_NACK(i2c);
276 }
277
278 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
279 stm32_i2c_disable_transfer_interrupts(dev);
280
281 /* Flush remaining TX byte before clearing Stop Flag */
282 LL_I2C_ClearFlag_TXE(i2c);
283
284 LL_I2C_ClearFlag_STOP(i2c);
285
286 slave_cb->stop(slave_cfg);
287
288 /* Prepare to ACK next transmissions address byte */
289 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
290 }
291
292 if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
293 uint32_t dir;
294
295 LL_I2C_ClearFlag_ADDR(i2c);
296
297 dir = LL_I2C_GetTransferDirection(i2c);
298 if (dir == LL_I2C_DIRECTION_WRITE) {
299 if (slave_cb->write_requested(slave_cfg) < 0) {
300 LOG_ERR("Error initiating writing");
301 } else {
302 LL_I2C_EnableIT_RX(i2c);
303 }
304 } else {
305 uint8_t val;
306
307 if (slave_cb->read_requested(slave_cfg, &val) < 0) {
308 LOG_ERR("Error initiating reading");
309 } else {
310 LL_I2C_TransmitData8(i2c, val);
311 LL_I2C_EnableIT_TX(i2c);
312 }
313 }
314
315 stm32_i2c_enable_transfer_interrupts(dev);
316 }
317 }
318
319 /* Attach and start I2C as target */
i2c_stm32_target_register(const struct device * dev,struct i2c_target_config * config)320 int i2c_stm32_target_register(const struct device *dev,
321 struct i2c_target_config *config)
322 {
323 const struct i2c_stm32_config *cfg = dev->config;
324 struct i2c_stm32_data *data = dev->data;
325 I2C_TypeDef *i2c = cfg->i2c;
326 uint32_t bitrate_cfg;
327 int ret;
328
329 if (!config) {
330 return -EINVAL;
331 }
332
333 if (data->slave_cfg && data->slave2_cfg) {
334 return -EBUSY;
335 }
336
337 if (data->master_active) {
338 return -EBUSY;
339 }
340
341 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
342
343 ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
344 if (ret < 0) {
345 LOG_ERR("i2c: failure initializing");
346 return ret;
347 }
348
349 #if defined(CONFIG_PM_DEVICE_RUNTIME)
350 if (pm_device_wakeup_is_capable(dev)) {
351 /* Mark device as active */
352 (void)pm_device_runtime_get(dev);
353 /* Enable wake-up from stop */
354 LOG_DBG("i2c: enabling wakeup from stop");
355 LL_I2C_EnableWakeUpFromStop(cfg->i2c);
356 }
357 #endif /* defined(CONFIG_PM_DEVICE_RUNTIME) */
358
359 LL_I2C_Enable(i2c);
360
361 if (!data->slave_cfg) {
362 data->slave_cfg = config;
363 if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
364 LL_I2C_SetOwnAddress1(i2c, config->address, LL_I2C_OWNADDRESS1_10BIT);
365 LOG_DBG("i2c: target #1 registered with 10-bit address");
366 } else {
367 LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT);
368 LOG_DBG("i2c: target #1 registered with 7-bit address");
369 }
370
371 LL_I2C_EnableOwnAddress1(i2c);
372
373 LOG_DBG("i2c: target #1 registered");
374 } else {
375 data->slave2_cfg = config;
376
377 if (data->slave2_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
378 return -EINVAL;
379 }
380 LL_I2C_SetOwnAddress2(i2c, config->address << 1U,
381 LL_I2C_OWNADDRESS2_NOMASK);
382 LL_I2C_EnableOwnAddress2(i2c);
383 LOG_DBG("i2c: target #2 registered");
384 }
385
386 data->slave_attached = true;
387
388 LL_I2C_EnableIT_ADDR(i2c);
389
390 return 0;
391 }
392
i2c_stm32_target_unregister(const struct device * dev,struct i2c_target_config * config)393 int i2c_stm32_target_unregister(const struct device *dev,
394 struct i2c_target_config *config)
395 {
396 const struct i2c_stm32_config *cfg = dev->config;
397 struct i2c_stm32_data *data = dev->data;
398 I2C_TypeDef *i2c = cfg->i2c;
399
400 if (!data->slave_attached) {
401 return -EINVAL;
402 }
403
404 if (data->master_active) {
405 return -EBUSY;
406 }
407
408 if (config == data->slave_cfg) {
409 LL_I2C_DisableOwnAddress1(i2c);
410 data->slave_cfg = NULL;
411
412 LOG_DBG("i2c: slave #1 unregistered");
413 } else if (config == data->slave2_cfg) {
414 LL_I2C_DisableOwnAddress2(i2c);
415 data->slave2_cfg = NULL;
416
417 LOG_DBG("i2c: slave #2 unregistered");
418 } else {
419 return -EINVAL;
420 }
421
422 /* Return if there is a slave remaining */
423 if (data->slave_cfg || data->slave2_cfg) {
424 LOG_DBG("i2c: target#%c still registered", data->slave_cfg?'1':'2');
425 return 0;
426 }
427
428 /* Otherwise disable I2C */
429 LL_I2C_DisableIT_ADDR(i2c);
430 stm32_i2c_disable_transfer_interrupts(dev);
431
432 LL_I2C_ClearFlag_NACK(i2c);
433 LL_I2C_ClearFlag_STOP(i2c);
434 LL_I2C_ClearFlag_ADDR(i2c);
435
436 if (!data->smbalert_active) {
437 LL_I2C_Disable(i2c);
438 }
439
440 #if defined(CONFIG_PM_DEVICE_RUNTIME)
441 if (pm_device_wakeup_is_capable(dev)) {
442 /* Disable wake-up from STOP */
443 LOG_DBG("i2c: disabling wakeup from stop");
444 LL_I2C_DisableWakeUpFromStop(i2c);
445 /* Release the device */
446 (void)pm_device_runtime_put(dev);
447 }
448 #endif /* defined(CONFIG_PM_DEVICE_RUNTIME) */
449
450 data->slave_attached = false;
451
452 return 0;
453 }
454
455 #endif /* defined(CONFIG_I2C_TARGET) */
456
stm32_i2c_event(const struct device * dev)457 static void stm32_i2c_event(const struct device *dev)
458 {
459 const struct i2c_stm32_config *cfg = dev->config;
460 struct i2c_stm32_data *data = dev->data;
461 I2C_TypeDef *i2c = cfg->i2c;
462
463 #if defined(CONFIG_I2C_TARGET)
464 if (data->slave_attached && !data->master_active) {
465 stm32_i2c_slave_event(dev);
466 return;
467 }
468 #endif
469 if (data->current.len) {
470 /* Send next byte */
471 if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
472 LL_I2C_TransmitData8(i2c, *data->current.buf);
473 }
474
475 /* Receive next byte */
476 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
477 *data->current.buf = LL_I2C_ReceiveData8(i2c);
478 }
479
480 data->current.buf++;
481 data->current.len--;
482 }
483
484 /* NACK received */
485 if (LL_I2C_IsActiveFlag_NACK(i2c)) {
486 LL_I2C_ClearFlag_NACK(i2c);
487 data->current.is_nack = 1U;
488 /*
489 * AutoEndMode is always disabled in master mode,
490 * so send a stop condition manually
491 */
492 LL_I2C_GenerateStopCondition(i2c);
493 return;
494 }
495
496 /* STOP received */
497 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
498 LL_I2C_ClearFlag_STOP(i2c);
499 LL_I2C_DisableReloadMode(i2c);
500 goto end;
501 }
502
503 /* Transfer Complete or Transfer Complete Reload */
504 if (LL_I2C_IsActiveFlag_TC(i2c) ||
505 LL_I2C_IsActiveFlag_TCR(i2c)) {
506 /* Issue stop condition if necessary */
507 if (data->current.msg->flags & I2C_MSG_STOP) {
508 LL_I2C_GenerateStopCondition(i2c);
509 } else {
510 stm32_i2c_disable_transfer_interrupts(dev);
511 k_sem_give(&data->device_sync_sem);
512 }
513 }
514
515 return;
516 end:
517 stm32_i2c_master_mode_end(dev);
518 }
519
stm32_i2c_error(const struct device * dev)520 static int stm32_i2c_error(const struct device *dev)
521 {
522 const struct i2c_stm32_config *cfg = dev->config;
523 struct i2c_stm32_data *data = dev->data;
524 I2C_TypeDef *i2c = cfg->i2c;
525
526 #if defined(CONFIG_I2C_TARGET)
527 if (data->slave_attached && !data->master_active) {
528 /* No need for a slave error function right now. */
529 return 0;
530 }
531 #endif
532
533 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
534 LL_I2C_ClearFlag_ARLO(i2c);
535 data->current.is_arlo = 1U;
536 goto end;
537 }
538
539 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
540 LL_I2C_ClearFlag_BERR(i2c);
541 data->current.is_err = 1U;
542 goto end;
543 }
544
545 #if defined(CONFIG_SMBUS_STM32_SMBALERT)
546 if (LL_I2C_IsActiveSMBusFlag_ALERT(i2c)) {
547 LL_I2C_ClearSMBusFlag_ALERT(i2c);
548 if (data->smbalert_cb_func != NULL) {
549 data->smbalert_cb_func(data->smbalert_cb_dev);
550 }
551 goto end;
552 }
553 #endif
554
555 return 0;
556 end:
557 stm32_i2c_master_mode_end(dev);
558 return -EIO;
559 }
560
561 #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
stm32_i2c_combined_isr(void * arg)562 void stm32_i2c_combined_isr(void *arg)
563 {
564 const struct device *dev = (const struct device *) arg;
565
566 if (stm32_i2c_error(dev)) {
567 return;
568 }
569 stm32_i2c_event(dev);
570 }
571 #else
572
stm32_i2c_event_isr(void * arg)573 void stm32_i2c_event_isr(void *arg)
574 {
575 const struct device *dev = (const struct device *) arg;
576
577 stm32_i2c_event(dev);
578 }
579
stm32_i2c_error_isr(void * arg)580 void stm32_i2c_error_isr(void *arg)
581 {
582 const struct device *dev = (const struct device *) arg;
583
584 stm32_i2c_error(dev);
585 }
586 #endif
587
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)588 static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
589 uint8_t *next_msg_flags, uint16_t slave)
590 {
591 const struct i2c_stm32_config *cfg = dev->config;
592 struct i2c_stm32_data *data = dev->data;
593 I2C_TypeDef *i2c = cfg->i2c;
594 bool is_timeout = false;
595
596 data->current.len = msg->len;
597 data->current.buf = msg->buf;
598 data->current.is_write = 1U;
599 data->current.is_nack = 0U;
600 data->current.is_err = 0U;
601 data->current.msg = msg;
602
603 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
604
605 stm32_i2c_enable_transfer_interrupts(dev);
606 LL_I2C_EnableIT_TX(i2c);
607
608 if (k_sem_take(&data->device_sync_sem,
609 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
610 stm32_i2c_master_mode_end(dev);
611 k_sem_take(&data->device_sync_sem, K_FOREVER);
612 is_timeout = true;
613 }
614
615 if (data->current.is_nack || data->current.is_err ||
616 data->current.is_arlo || is_timeout) {
617 goto error;
618 }
619
620 return 0;
621 error:
622 if (data->current.is_arlo) {
623 LOG_DBG("%s: ARLO %d", __func__,
624 data->current.is_arlo);
625 data->current.is_arlo = 0U;
626 }
627
628 if (data->current.is_nack) {
629 LOG_DBG("%s: NACK", __func__);
630 data->current.is_nack = 0U;
631 }
632
633 if (data->current.is_err) {
634 LOG_DBG("%s: ERR %d", __func__,
635 data->current.is_err);
636 data->current.is_err = 0U;
637 }
638
639 if (is_timeout) {
640 LOG_DBG("%s: TIMEOUT", __func__);
641 }
642
643 return -EIO;
644 }
645
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)646 static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
647 uint8_t *next_msg_flags, uint16_t slave)
648 {
649 const struct i2c_stm32_config *cfg = dev->config;
650 struct i2c_stm32_data *data = dev->data;
651 I2C_TypeDef *i2c = cfg->i2c;
652 bool is_timeout = false;
653
654 data->current.len = msg->len;
655 data->current.buf = msg->buf;
656 data->current.is_write = 0U;
657 data->current.is_arlo = 0U;
658 data->current.is_err = 0U;
659 data->current.is_nack = 0U;
660 data->current.msg = msg;
661
662 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
663
664 stm32_i2c_enable_transfer_interrupts(dev);
665 LL_I2C_EnableIT_RX(i2c);
666
667 if (k_sem_take(&data->device_sync_sem,
668 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
669 stm32_i2c_master_mode_end(dev);
670 k_sem_take(&data->device_sync_sem, K_FOREVER);
671 is_timeout = true;
672 }
673
674 if (data->current.is_nack || data->current.is_err ||
675 data->current.is_arlo || is_timeout) {
676 goto error;
677 }
678
679 return 0;
680 error:
681 if (data->current.is_arlo) {
682 LOG_DBG("%s: ARLO %d", __func__,
683 data->current.is_arlo);
684 data->current.is_arlo = 0U;
685 }
686
687 if (data->current.is_nack) {
688 LOG_DBG("%s: NACK", __func__);
689 data->current.is_nack = 0U;
690 }
691
692 if (data->current.is_err) {
693 LOG_DBG("%s: ERR %d", __func__,
694 data->current.is_err);
695 data->current.is_err = 0U;
696 }
697
698 if (is_timeout) {
699 LOG_DBG("%s: TIMEOUT", __func__);
700 }
701
702 return -EIO;
703 }
704
705 #else /* !CONFIG_I2C_STM32_INTERRUPT */
check_errors(const struct device * dev,const char * funcname)706 static inline int check_errors(const struct device *dev, const char *funcname)
707 {
708 const struct i2c_stm32_config *cfg = dev->config;
709 I2C_TypeDef *i2c = cfg->i2c;
710
711 if (LL_I2C_IsActiveFlag_NACK(i2c)) {
712 LL_I2C_ClearFlag_NACK(i2c);
713 LOG_DBG("%s: NACK", funcname);
714 goto error;
715 }
716
717 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
718 LL_I2C_ClearFlag_ARLO(i2c);
719 LOG_DBG("%s: ARLO", funcname);
720 goto error;
721 }
722
723 if (LL_I2C_IsActiveFlag_OVR(i2c)) {
724 LL_I2C_ClearFlag_OVR(i2c);
725 LOG_DBG("%s: OVR", funcname);
726 goto error;
727 }
728
729 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
730 LL_I2C_ClearFlag_BERR(i2c);
731 LOG_DBG("%s: BERR", funcname);
732 goto error;
733 }
734
735 return 0;
736 error:
737 if (LL_I2C_IsEnabledReloadMode(i2c)) {
738 LL_I2C_DisableReloadMode(i2c);
739 }
740 return -EIO;
741 }
742
msg_done(const struct device * dev,unsigned int current_msg_flags)743 static inline int msg_done(const struct device *dev,
744 unsigned int current_msg_flags)
745 {
746 const struct i2c_stm32_config *cfg = dev->config;
747 I2C_TypeDef *i2c = cfg->i2c;
748
749 /* Wait for transfer to complete */
750 while (!LL_I2C_IsActiveFlag_TC(i2c) && !LL_I2C_IsActiveFlag_TCR(i2c)) {
751 if (check_errors(dev, __func__)) {
752 return -EIO;
753 }
754 }
755 /* Issue stop condition if necessary */
756 if (current_msg_flags & I2C_MSG_STOP) {
757 LL_I2C_GenerateStopCondition(i2c);
758 while (!LL_I2C_IsActiveFlag_STOP(i2c)) {
759 }
760
761 LL_I2C_ClearFlag_STOP(i2c);
762 LL_I2C_DisableReloadMode(i2c);
763 }
764
765 return 0;
766 }
767
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)768 static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
769 uint8_t *next_msg_flags, uint16_t slave)
770 {
771 const struct i2c_stm32_config *cfg = dev->config;
772 I2C_TypeDef *i2c = cfg->i2c;
773 unsigned int len = 0U;
774 uint8_t *buf = msg->buf;
775
776 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
777
778 len = msg->len;
779 while (len) {
780 while (1) {
781 if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
782 break;
783 }
784
785 if (check_errors(dev, __func__)) {
786 return -EIO;
787 }
788 }
789
790 LL_I2C_TransmitData8(i2c, *buf);
791 buf++;
792 len--;
793 }
794
795 return msg_done(dev, msg->flags);
796 }
797
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)798 static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
799 uint8_t *next_msg_flags, uint16_t slave)
800 {
801 const struct i2c_stm32_config *cfg = dev->config;
802 I2C_TypeDef *i2c = cfg->i2c;
803 unsigned int len = 0U;
804 uint8_t *buf = msg->buf;
805
806 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
807
808 len = msg->len;
809 while (len) {
810 while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
811 if (check_errors(dev, __func__)) {
812 return -EIO;
813 }
814 }
815
816 *buf = LL_I2C_ReceiveData8(i2c);
817 buf++;
818 len--;
819 }
820
821 return msg_done(dev, msg->flags);
822 }
823 #endif
824
825 #ifdef CONFIG_I2C_STM32_V2_TIMING
826 /*
827 * Macro used to fix the compliance check warning :
828 * "DEEP_INDENTATION: Too many leading tabs - consider code refactoring
829 * in the i2c_compute_scll_sclh() function below
830 */
831 #define I2C_LOOP_SCLH(); \
832 if ((tscl >= clk_min) && \
833 (tscl <= clk_max) && \
834 (tscl_h >= stm32_i2c_charac[i2c_speed].hscl_min) && \
835 (ti2cclk < tscl_h)) { \
836 \
837 int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; \
838 \
839 if (error < 0) { \
840 error = -error; \
841 } \
842 \
843 if ((uint32_t)error < prev_error) { \
844 prev_error = (uint32_t)error; \
845 i2c_valid_timing[count].scll = scll; \
846 i2c_valid_timing[count].sclh = sclh; \
847 ret = count; \
848 } \
849 }
850
851 /*
852 * @brief Calculate SCLL and SCLH and find best configuration.
853 * @param clock_src_freq I2C source clock in Hz.
854 * @param i2c_speed I2C frequency (index).
855 * @retval config index (0 to I2C_VALID_TIMING_NBR], 0xFFFFFFFF for no valid config.
856 */
i2c_compute_scll_sclh(uint32_t clock_src_freq,uint32_t i2c_speed)857 uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t i2c_speed)
858 {
859 uint32_t ret = 0xFFFFFFFFU;
860 uint32_t ti2cclk;
861 uint32_t ti2cspeed;
862 uint32_t prev_error;
863 uint32_t dnf_delay;
864 uint32_t clk_min, clk_max;
865 uint32_t scll, sclh;
866 uint32_t tafdel_min;
867
868 ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq;
869 ti2cspeed = (NSEC_PER_SEC + (stm32_i2c_charac[i2c_speed].freq / 2U)) /
870 stm32_i2c_charac[i2c_speed].freq;
871
872 tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ?
873 STM32_I2C_ANALOG_FILTER_DELAY_MIN :
874 0U;
875
876 /* tDNF = DNF x tI2CCLK */
877 dnf_delay = stm32_i2c_charac[i2c_speed].dnf * ti2cclk;
878
879 clk_max = NSEC_PER_SEC / stm32_i2c_charac[i2c_speed].freq_min;
880 clk_min = NSEC_PER_SEC / stm32_i2c_charac[i2c_speed].freq_max;
881
882 prev_error = ti2cspeed;
883
884 for (uint32_t count = 0; count < STM32_I2C_VALID_TIMING_NBR; count++) {
885 /* tPRESC = (PRESC+1) x tI2CCLK*/
886 uint32_t tpresc = (i2c_valid_timing[count].presc + 1U) * ti2cclk;
887
888 for (scll = 0; scll < STM32_I2C_SCLL_MAX; scll++) {
889 /* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL+1) x tPRESC ] */
890 uint32_t tscl_l = tafdel_min + dnf_delay +
891 (2U * ti2cclk) + ((scll + 1U) * tpresc);
892
893 /*
894 * The I2CCLK period tI2CCLK must respect the following conditions:
895 * tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH
896 */
897 if ((tscl_l > stm32_i2c_charac[i2c_speed].lscl_min) &&
898 (ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) {
899 for (sclh = 0; sclh < STM32_I2C_SCLH_MAX; sclh++) {
900 /*
901 * tHIGH(min) <= tAF(min) + tDNF +
902 * 2 x tI2CCLK + [(SCLH+1) x tPRESC]
903 */
904 uint32_t tscl_h = tafdel_min + dnf_delay +
905 (2U * ti2cclk) + ((sclh + 1U) * tpresc);
906
907 /* tSCL = tf + tLOW + tr + tHIGH */
908 uint32_t tscl = tscl_l +
909 tscl_h + stm32_i2c_charac[i2c_speed].trise +
910 stm32_i2c_charac[i2c_speed].tfall;
911
912 /* get timings with the lowest clock error */
913 I2C_LOOP_SCLH();
914 }
915 }
916 }
917 }
918
919 return ret;
920 }
921
922 /*
923 * Macro used to fix the compliance check warning :
924 * "DEEP_INDENTATION: Too many leading tabs - consider code refactoring
925 * in the i2c_compute_presc_scldel_sdadel() function below
926 */
927 #define I2C_LOOP_SDADEL(); \
928 \
929 if ((tsdadel >= (uint32_t)tsdadel_min) && \
930 (tsdadel <= (uint32_t)tsdadel_max)) { \
931 if (presc != prev_presc) { \
932 i2c_valid_timing[i2c_valid_timing_nbr].presc = presc; \
933 i2c_valid_timing[i2c_valid_timing_nbr].tscldel = scldel; \
934 i2c_valid_timing[i2c_valid_timing_nbr].tsdadel = sdadel; \
935 prev_presc = presc; \
936 i2c_valid_timing_nbr++; \
937 \
938 if (i2c_valid_timing_nbr >= STM32_I2C_VALID_TIMING_NBR) { \
939 break; \
940 } \
941 } \
942 }
943
944 /*
945 * @brief Compute PRESC, SCLDEL and SDADEL.
946 * @param clock_src_freq I2C source clock in Hz.
947 * @param i2c_speed I2C frequency (index).
948 * @retval None.
949 */
i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq,uint32_t i2c_speed)950 void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t i2c_speed)
951 {
952 uint32_t prev_presc = STM32_I2C_PRESC_MAX;
953 uint32_t ti2cclk;
954 int32_t tsdadel_min, tsdadel_max;
955 int32_t tscldel_min;
956 uint32_t presc, scldel, sdadel;
957 uint32_t tafdel_min, tafdel_max;
958
959 ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq;
960
961 tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ?
962 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0U;
963 tafdel_max = (STM32_I2C_USE_ANALOG_FILTER == 1U) ?
964 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0U;
965 /*
966 * tDNF = DNF x tI2CCLK
967 * tPRESC = (PRESC+1) x tI2CCLK
968 * SDADEL >= {tf +tHD;DAT(min) - tAF(min) - tDNF - [3 x tI2CCLK]} / {tPRESC}
969 * SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC}
970 */
971 tsdadel_min = (int32_t)stm32_i2c_charac[i2c_speed].tfall +
972 (int32_t)stm32_i2c_charac[i2c_speed].hddat_min -
973 (int32_t)tafdel_min -
974 (int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 3) *
975 (int32_t)ti2cclk);
976
977 tsdadel_max = (int32_t)stm32_i2c_charac[i2c_speed].vddat_max -
978 (int32_t)stm32_i2c_charac[i2c_speed].trise -
979 (int32_t)tafdel_max -
980 (int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 4) *
981 (int32_t)ti2cclk);
982
983 /* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */
984 tscldel_min = (int32_t)stm32_i2c_charac[i2c_speed].trise +
985 (int32_t)stm32_i2c_charac[i2c_speed].sudat_min;
986
987 if (tsdadel_min <= 0) {
988 tsdadel_min = 0;
989 }
990
991 if (tsdadel_max <= 0) {
992 tsdadel_max = 0;
993 }
994
995 for (presc = 0; presc < STM32_I2C_PRESC_MAX; presc++) {
996 for (scldel = 0; scldel < STM32_I2C_SCLDEL_MAX; scldel++) {
997 /* TSCLDEL = (SCLDEL+1) * (PRESC+1) * TI2CCLK */
998 uint32_t tscldel = (scldel + 1U) * (presc + 1U) * ti2cclk;
999
1000 if (tscldel >= (uint32_t)tscldel_min) {
1001 for (sdadel = 0; sdadel < STM32_I2C_SDADEL_MAX; sdadel++) {
1002 /* TSDADEL = SDADEL * (PRESC+1) * TI2CCLK */
1003 uint32_t tsdadel = (sdadel * (presc + 1U)) * ti2cclk;
1004
1005 I2C_LOOP_SDADEL();
1006 }
1007
1008 if (i2c_valid_timing_nbr >= STM32_I2C_VALID_TIMING_NBR) {
1009 return;
1010 }
1011 }
1012 }
1013 }
1014 }
1015
stm32_i2c_configure_timing(const struct device * dev,uint32_t clock)1016 int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
1017 {
1018 const struct i2c_stm32_config *cfg = dev->config;
1019 struct i2c_stm32_data *data = dev->data;
1020 I2C_TypeDef *i2c = cfg->i2c;
1021 uint32_t timing = 0U;
1022 uint32_t idx;
1023 uint32_t speed = 0U;
1024 uint32_t i2c_freq = cfg->bitrate;
1025
1026 /* Reset valid timing count at the beginning of each new computation */
1027 i2c_valid_timing_nbr = 0;
1028
1029 if ((clock != 0U) && (i2c_freq != 0U)) {
1030 for (speed = 0 ; speed <= (uint32_t)STM32_I2C_SPEED_FREQ_FAST_PLUS ; speed++) {
1031 if ((i2c_freq >= stm32_i2c_charac[speed].freq_min) &&
1032 (i2c_freq <= stm32_i2c_charac[speed].freq_max)) {
1033 i2c_compute_presc_scldel_sdadel(clock, speed);
1034 idx = i2c_compute_scll_sclh(clock, speed);
1035 if (idx < STM32_I2C_VALID_TIMING_NBR) {
1036 timing = ((i2c_valid_timing[idx].presc &
1037 0x0FU) << 28) |
1038 ((i2c_valid_timing[idx].tscldel & 0x0FU) << 20) |
1039 ((i2c_valid_timing[idx].tsdadel & 0x0FU) << 16) |
1040 ((i2c_valid_timing[idx].sclh & 0xFFU) << 8) |
1041 ((i2c_valid_timing[idx].scll & 0xFFU) << 0);
1042 }
1043 break;
1044 }
1045 }
1046 }
1047
1048 /* Fill the current timing value in data structure at runtime */
1049 data->current_timing.periph_clock = clock;
1050 data->current_timing.i2c_speed = i2c_freq;
1051 data->current_timing.timing_setting = timing;
1052
1053 LL_I2C_SetTiming(i2c, timing);
1054
1055 return 0;
1056 }
1057 #else/* CONFIG_I2C_STM32_V2_TIMING */
1058
stm32_i2c_configure_timing(const struct device * dev,uint32_t clock)1059 int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
1060 {
1061 const struct i2c_stm32_config *cfg = dev->config;
1062 struct i2c_stm32_data *data = dev->data;
1063 I2C_TypeDef *i2c = cfg->i2c;
1064 uint32_t i2c_hold_time_min, i2c_setup_time_min;
1065 uint32_t i2c_h_min_time, i2c_l_min_time;
1066 uint32_t presc = 1U;
1067 uint32_t timing = 0U;
1068
1069 /* Look for an adequate preset timing value */
1070 for (uint32_t i = 0; i < cfg->n_timings; i++) {
1071 const struct i2c_config_timing *preset = &cfg->timings[i];
1072 uint32_t speed = i2c_map_dt_bitrate(preset->i2c_speed);
1073
1074 if ((I2C_SPEED_GET(speed) == I2C_SPEED_GET(data->dev_config))
1075 && (preset->periph_clock == clock)) {
1076 /* Found a matching periph clock and i2c speed */
1077 LL_I2C_SetTiming(i2c, preset->timing_setting);
1078 return 0;
1079 }
1080 }
1081
1082 /* No preset timing was provided, let's dynamically configure */
1083 switch (I2C_SPEED_GET(data->dev_config)) {
1084 case I2C_SPEED_STANDARD:
1085 i2c_h_min_time = 4000U;
1086 i2c_l_min_time = 4700U;
1087 i2c_hold_time_min = 500U;
1088 i2c_setup_time_min = 1250U;
1089 break;
1090 case I2C_SPEED_FAST:
1091 i2c_h_min_time = 600U;
1092 i2c_l_min_time = 1300U;
1093 i2c_hold_time_min = 375U;
1094 i2c_setup_time_min = 500U;
1095 break;
1096 default:
1097 LOG_ERR("i2c: speed above \"fast\" requires manual timing configuration, "
1098 "see \"timings\" property of st,stm32-i2c-v2 devicetree binding");
1099 return -EINVAL;
1100 }
1101
1102 /* Calculate period until prescaler matches */
1103 do {
1104 uint32_t t_presc = clock / presc;
1105 uint32_t ns_presc = NSEC_PER_SEC / t_presc;
1106 uint32_t sclh = i2c_h_min_time / ns_presc;
1107 uint32_t scll = i2c_l_min_time / ns_presc;
1108 uint32_t sdadel = i2c_hold_time_min / ns_presc;
1109 uint32_t scldel = i2c_setup_time_min / ns_presc;
1110
1111 if ((sclh - 1) > 255 || (scll - 1) > 255) {
1112 ++presc;
1113 continue;
1114 }
1115
1116 if (sdadel > 15 || (scldel - 1) > 15) {
1117 ++presc;
1118 continue;
1119 }
1120
1121 timing = __LL_I2C_CONVERT_TIMINGS(presc - 1,
1122 scldel - 1, sdadel, sclh - 1, scll - 1);
1123 break;
1124 } while (presc < 16);
1125
1126 if (presc >= 16U) {
1127 LOG_ERR("I2C:failed to find prescaler value");
1128 return -EINVAL;
1129 }
1130
1131 LOG_DBG("I2C TIMING = 0x%x", timing);
1132 LL_I2C_SetTiming(i2c, timing);
1133
1134 return 0;
1135 }
1136 #endif /* CONFIG_I2C_STM32_V2_TIMING */
1137
stm32_i2c_transaction(const struct device * dev,struct i2c_msg msg,uint8_t * next_msg_flags,uint16_t periph)1138 int stm32_i2c_transaction(const struct device *dev,
1139 struct i2c_msg msg, uint8_t *next_msg_flags,
1140 uint16_t periph)
1141 {
1142 /*
1143 * Perform a I2C transaction, while taking into account the STM32 I2C V2
1144 * peripheral has a limited maximum chunk size. Take appropriate action
1145 * if the message to send exceeds that limit.
1146 *
1147 * The last chunk of a transmission uses this function's next_msg_flags
1148 * parameter for its backend calls (_write/_read). Any previous chunks
1149 * use a copy of the current message's flags, with the STOP and RESTART
1150 * bits turned off. This will cause the backend to use reload-mode,
1151 * which will make the combination of all chunks to look like one big
1152 * transaction on the wire.
1153 */
1154 const uint32_t i2c_stm32_maxchunk = 255U;
1155 const uint8_t saved_flags = msg.flags;
1156 uint8_t combine_flags =
1157 saved_flags & ~(I2C_MSG_STOP | I2C_MSG_RESTART);
1158 uint8_t *flagsp = NULL;
1159 uint32_t rest = msg.len;
1160 int ret = 0;
1161
1162 do { /* do ... while to allow zero-length transactions */
1163 if (msg.len > i2c_stm32_maxchunk) {
1164 msg.len = i2c_stm32_maxchunk;
1165 msg.flags &= ~I2C_MSG_STOP;
1166 flagsp = &combine_flags;
1167 } else {
1168 msg.flags = saved_flags;
1169 flagsp = next_msg_flags;
1170 }
1171 if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
1172 ret = stm32_i2c_msg_write(dev, &msg, flagsp, periph);
1173 } else {
1174 ret = stm32_i2c_msg_read(dev, &msg, flagsp, periph);
1175 }
1176 if (ret < 0) {
1177 break;
1178 }
1179 rest -= msg.len;
1180 msg.buf += msg.len;
1181 msg.len = rest;
1182 } while (rest > 0U);
1183
1184 return ret;
1185 }
1186
