1 /*
2 * Copyright (c) 2016 BayLibre, SAS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4, STM32WB and
8 * STM32WL
9 *
10 */
11
12 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/kernel.h>
16 #include <soc.h>
17 #include <stm32_ll_i2c.h>
18 #include <errno.h>
19 #include <zephyr/drivers/i2c.h>
20 #include "i2c_ll_stm32.h"
21
22 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
23 #include <zephyr/logging/log.h>
24 LOG_MODULE_REGISTER(i2c_ll_stm32_v2);
25
26 #include "i2c-priv.h"
27
28 #define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
29
msg_init(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave,uint32_t transfer)30 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
31 uint8_t *next_msg_flags, uint16_t slave,
32 uint32_t transfer)
33 {
34 const struct i2c_stm32_config *cfg = dev->config;
35 struct i2c_stm32_data *data = dev->data;
36 I2C_TypeDef *i2c = cfg->i2c;
37
38 if (LL_I2C_IsEnabledReloadMode(i2c)) {
39 LL_I2C_SetTransferSize(i2c, msg->len);
40 } else {
41 if (I2C_ADDR_10_BITS & data->dev_config) {
42 LL_I2C_SetMasterAddressingMode(i2c,
43 LL_I2C_ADDRESSING_MODE_10BIT);
44 LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave);
45 } else {
46 LL_I2C_SetMasterAddressingMode(i2c,
47 LL_I2C_ADDRESSING_MODE_7BIT);
48 LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave << 1);
49 }
50
51 if (!(msg->flags & I2C_MSG_STOP) && next_msg_flags &&
52 !(*next_msg_flags & I2C_MSG_RESTART)) {
53 LL_I2C_EnableReloadMode(i2c);
54 } else {
55 LL_I2C_DisableReloadMode(i2c);
56 }
57 LL_I2C_DisableAutoEndMode(i2c);
58 LL_I2C_SetTransferRequest(i2c, transfer);
59 LL_I2C_SetTransferSize(i2c, msg->len);
60
61 #if defined(CONFIG_I2C_TARGET)
62 data->master_active = true;
63 #endif
64 LL_I2C_Enable(i2c);
65
66 LL_I2C_GenerateStartCondition(i2c);
67 }
68 }
69
70 #ifdef CONFIG_I2C_STM32_INTERRUPT
71
stm32_i2c_disable_transfer_interrupts(const struct device * dev)72 static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
73 {
74 const struct i2c_stm32_config *cfg = dev->config;
75 I2C_TypeDef *i2c = cfg->i2c;
76
77 LL_I2C_DisableIT_TX(i2c);
78 LL_I2C_DisableIT_RX(i2c);
79 LL_I2C_DisableIT_STOP(i2c);
80 LL_I2C_DisableIT_NACK(i2c);
81 LL_I2C_DisableIT_TC(i2c);
82 LL_I2C_DisableIT_ERR(i2c);
83 }
84
stm32_i2c_enable_transfer_interrupts(const struct device * dev)85 static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
86 {
87 const struct i2c_stm32_config *cfg = dev->config;
88 I2C_TypeDef *i2c = cfg->i2c;
89
90 LL_I2C_EnableIT_STOP(i2c);
91 LL_I2C_EnableIT_NACK(i2c);
92 LL_I2C_EnableIT_TC(i2c);
93 LL_I2C_EnableIT_ERR(i2c);
94 }
95
stm32_i2c_master_mode_end(const struct device * dev)96 static void stm32_i2c_master_mode_end(const struct device *dev)
97 {
98 const struct i2c_stm32_config *cfg = dev->config;
99 struct i2c_stm32_data *data = dev->data;
100 I2C_TypeDef *i2c = cfg->i2c;
101
102 stm32_i2c_disable_transfer_interrupts(dev);
103
104 #if defined(CONFIG_I2C_TARGET)
105 data->master_active = false;
106 if (!data->slave_attached) {
107 LL_I2C_Disable(i2c);
108 }
109 #else
110 LL_I2C_Disable(i2c);
111 #endif
112 k_sem_give(&data->device_sync_sem);
113 }
114
115 #if defined(CONFIG_I2C_TARGET)
stm32_i2c_slave_event(const struct device * dev)116 static void stm32_i2c_slave_event(const struct device *dev)
117 {
118 const struct i2c_stm32_config *cfg = dev->config;
119 struct i2c_stm32_data *data = dev->data;
120 I2C_TypeDef *i2c = cfg->i2c;
121 const struct i2c_target_callbacks *slave_cb;
122 struct i2c_target_config *slave_cfg;
123 uint8_t slave_address;
124
125 /* Choose the right slave from the address match code */
126 slave_address = LL_I2C_GetAddressMatchCode(i2c) >> 1;
127 if (data->slave_cfg != NULL && slave_address == data->slave_cfg->address) {
128 slave_cfg = data->slave_cfg;
129 } else if (data->slave2_cfg != NULL && slave_address == data->slave2_cfg->address) {
130 slave_cfg = data->slave2_cfg;
131 } else {
132 __ASSERT_NO_MSG(0);
133 return;
134 }
135 slave_cb = slave_cfg->callbacks;
136
137 if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
138 uint8_t val;
139
140 slave_cb->read_processed(slave_cfg, &val);
141 LL_I2C_TransmitData8(i2c, val);
142 return;
143 }
144
145 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
146 uint8_t val = LL_I2C_ReceiveData8(i2c);
147
148 if (slave_cb->write_received(slave_cfg, val)) {
149 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
150 }
151 return;
152 }
153
154 if (LL_I2C_IsActiveFlag_NACK(i2c)) {
155 LL_I2C_ClearFlag_NACK(i2c);
156 }
157
158 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
159 stm32_i2c_disable_transfer_interrupts(dev);
160
161 /* Flush remaining TX byte before clearing Stop Flag */
162 LL_I2C_ClearFlag_TXE(i2c);
163
164 LL_I2C_ClearFlag_STOP(i2c);
165
166 slave_cb->stop(slave_cfg);
167
168 /* Prepare to ACK next transmissions address byte */
169 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
170 }
171
172 if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
173 uint32_t dir;
174
175 LL_I2C_ClearFlag_ADDR(i2c);
176
177 dir = LL_I2C_GetTransferDirection(i2c);
178 if (dir == LL_I2C_DIRECTION_WRITE) {
179 slave_cb->write_requested(slave_cfg);
180 LL_I2C_EnableIT_RX(i2c);
181 } else {
182 uint8_t val;
183
184 slave_cb->read_requested(slave_cfg, &val);
185 LL_I2C_TransmitData8(i2c, val);
186 LL_I2C_EnableIT_TX(i2c);
187 }
188
189 stm32_i2c_enable_transfer_interrupts(dev);
190 }
191 }
192
193 /* Attach and start I2C as target */
i2c_stm32_target_register(const struct device * dev,struct i2c_target_config * config)194 int i2c_stm32_target_register(const struct device *dev,
195 struct i2c_target_config *config)
196 {
197 const struct i2c_stm32_config *cfg = dev->config;
198 struct i2c_stm32_data *data = dev->data;
199 I2C_TypeDef *i2c = cfg->i2c;
200 uint32_t bitrate_cfg;
201 int ret;
202
203 if (!config) {
204 return -EINVAL;
205 }
206
207 if (data->slave_cfg && data->slave2_cfg) {
208 return -EBUSY;
209 }
210
211 if (data->master_active) {
212 return -EBUSY;
213 }
214
215 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
216
217 ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
218 if (ret < 0) {
219 LOG_ERR("i2c: failure initializing");
220 return ret;
221 }
222
223 LL_I2C_Enable(i2c);
224
225 if (!data->slave_cfg) {
226 data->slave_cfg = config;
227 if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
228 LL_I2C_SetOwnAddress1(i2c, config->address, LL_I2C_OWNADDRESS1_10BIT);
229 LOG_DBG("i2c: target #1 registered with 10-bit address");
230 } else {
231 LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT);
232 LOG_DBG("i2c: target #1 registered with 7-bit address");
233 }
234
235 LL_I2C_EnableOwnAddress1(i2c);
236
237 LOG_DBG("i2c: target #1 registered");
238 } else {
239 data->slave2_cfg = config;
240
241 if (data->slave2_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
242 return -EINVAL;
243 }
244 LL_I2C_SetOwnAddress2(i2c, config->address << 1U,
245 LL_I2C_OWNADDRESS2_NOMASK);
246 LL_I2C_EnableOwnAddress2(i2c);
247 LOG_DBG("i2c: target #2 registered");
248 }
249
250 data->slave_attached = true;
251
252 LL_I2C_EnableIT_ADDR(i2c);
253
254 return 0;
255 }
256
i2c_stm32_target_unregister(const struct device * dev,struct i2c_target_config * config)257 int i2c_stm32_target_unregister(const struct device *dev,
258 struct i2c_target_config *config)
259 {
260 const struct i2c_stm32_config *cfg = dev->config;
261 struct i2c_stm32_data *data = dev->data;
262 I2C_TypeDef *i2c = cfg->i2c;
263
264 if (!data->slave_attached) {
265 return -EINVAL;
266 }
267
268 if (data->master_active) {
269 return -EBUSY;
270 }
271
272 if (config == data->slave_cfg) {
273 LL_I2C_DisableOwnAddress1(i2c);
274 data->slave_cfg = NULL;
275
276 LOG_DBG("i2c: slave #1 unregistered");
277 } else if (config == data->slave2_cfg) {
278 LL_I2C_DisableOwnAddress2(i2c);
279 data->slave2_cfg = NULL;
280
281 LOG_DBG("i2c: slave #2 unregistered");
282 } else {
283 return -EINVAL;
284 }
285
286 /* Return if there is a slave remaining */
287 if (data->slave_cfg || data->slave2_cfg) {
288 LOG_DBG("i2c: target#%c still registered", data->slave_cfg?'1':'2');
289 return 0;
290 }
291
292 /* Otherwise disable I2C */
293 LL_I2C_DisableIT_ADDR(i2c);
294 stm32_i2c_disable_transfer_interrupts(dev);
295
296 LL_I2C_ClearFlag_NACK(i2c);
297 LL_I2C_ClearFlag_STOP(i2c);
298 LL_I2C_ClearFlag_ADDR(i2c);
299
300 LL_I2C_Disable(i2c);
301
302 data->slave_attached = false;
303
304 return 0;
305 }
306
307 #endif /* defined(CONFIG_I2C_TARGET) */
308
stm32_i2c_event(const struct device * dev)309 static void stm32_i2c_event(const struct device *dev)
310 {
311 const struct i2c_stm32_config *cfg = dev->config;
312 struct i2c_stm32_data *data = dev->data;
313 I2C_TypeDef *i2c = cfg->i2c;
314
315 #if defined(CONFIG_I2C_TARGET)
316 if (data->slave_attached && !data->master_active) {
317 stm32_i2c_slave_event(dev);
318 return;
319 }
320 #endif
321 if (data->current.len) {
322 /* Send next byte */
323 if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
324 LL_I2C_TransmitData8(i2c, *data->current.buf);
325 }
326
327 /* Receive next byte */
328 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
329 *data->current.buf = LL_I2C_ReceiveData8(i2c);
330 }
331
332 data->current.buf++;
333 data->current.len--;
334 }
335
336 /* NACK received */
337 if (LL_I2C_IsActiveFlag_NACK(i2c)) {
338 LL_I2C_ClearFlag_NACK(i2c);
339 data->current.is_nack = 1U;
340 /*
341 * AutoEndMode is always disabled in master mode,
342 * so send a stop condition manually
343 */
344 LL_I2C_GenerateStopCondition(i2c);
345 return;
346 }
347
348 /* STOP received */
349 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
350 LL_I2C_ClearFlag_STOP(i2c);
351 LL_I2C_DisableReloadMode(i2c);
352 goto end;
353 }
354
355 /* Transfer Complete or Transfer Complete Reload */
356 if (LL_I2C_IsActiveFlag_TC(i2c) ||
357 LL_I2C_IsActiveFlag_TCR(i2c)) {
358 /* Issue stop condition if necessary */
359 if (data->current.msg->flags & I2C_MSG_STOP) {
360 LL_I2C_GenerateStopCondition(i2c);
361 } else {
362 stm32_i2c_disable_transfer_interrupts(dev);
363 k_sem_give(&data->device_sync_sem);
364 }
365 }
366
367 return;
368 end:
369 stm32_i2c_master_mode_end(dev);
370 }
371
stm32_i2c_error(const struct device * dev)372 static int stm32_i2c_error(const struct device *dev)
373 {
374 const struct i2c_stm32_config *cfg = dev->config;
375 struct i2c_stm32_data *data = dev->data;
376 I2C_TypeDef *i2c = cfg->i2c;
377
378 #if defined(CONFIG_I2C_TARGET)
379 if (data->slave_attached && !data->master_active) {
380 /* No need for a slave error function right now. */
381 return 0;
382 }
383 #endif
384
385 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
386 LL_I2C_ClearFlag_ARLO(i2c);
387 data->current.is_arlo = 1U;
388 goto end;
389 }
390
391 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
392 LL_I2C_ClearFlag_BERR(i2c);
393 data->current.is_err = 1U;
394 goto end;
395 }
396
397 return 0;
398 end:
399 stm32_i2c_master_mode_end(dev);
400 return -EIO;
401 }
402
403 #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
stm32_i2c_combined_isr(void * arg)404 void stm32_i2c_combined_isr(void *arg)
405 {
406 const struct device *dev = (const struct device *) arg;
407
408 if (stm32_i2c_error(dev)) {
409 return;
410 }
411 stm32_i2c_event(dev);
412 }
413 #else
414
stm32_i2c_event_isr(void * arg)415 void stm32_i2c_event_isr(void *arg)
416 {
417 const struct device *dev = (const struct device *) arg;
418
419 stm32_i2c_event(dev);
420 }
421
stm32_i2c_error_isr(void * arg)422 void stm32_i2c_error_isr(void *arg)
423 {
424 const struct device *dev = (const struct device *) arg;
425
426 stm32_i2c_error(dev);
427 }
428 #endif
429
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)430 int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
431 uint8_t *next_msg_flags, uint16_t slave)
432 {
433 const struct i2c_stm32_config *cfg = dev->config;
434 struct i2c_stm32_data *data = dev->data;
435 I2C_TypeDef *i2c = cfg->i2c;
436 bool is_timeout = false;
437
438 data->current.len = msg->len;
439 data->current.buf = msg->buf;
440 data->current.is_write = 1U;
441 data->current.is_nack = 0U;
442 data->current.is_err = 0U;
443 data->current.msg = msg;
444
445 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
446
447 stm32_i2c_enable_transfer_interrupts(dev);
448 LL_I2C_EnableIT_TX(i2c);
449
450 if (k_sem_take(&data->device_sync_sem,
451 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
452 stm32_i2c_master_mode_end(dev);
453 k_sem_take(&data->device_sync_sem, K_FOREVER);
454 is_timeout = true;
455 }
456
457 if (data->current.is_nack || data->current.is_err ||
458 data->current.is_arlo || is_timeout) {
459 goto error;
460 }
461
462 return 0;
463 error:
464 if (data->current.is_arlo) {
465 LOG_DBG("%s: ARLO %d", __func__,
466 data->current.is_arlo);
467 data->current.is_arlo = 0U;
468 }
469
470 if (data->current.is_nack) {
471 LOG_DBG("%s: NACK", __func__);
472 data->current.is_nack = 0U;
473 }
474
475 if (data->current.is_err) {
476 LOG_DBG("%s: ERR %d", __func__,
477 data->current.is_err);
478 data->current.is_err = 0U;
479 }
480
481 if (is_timeout) {
482 LOG_DBG("%s: TIMEOUT", __func__);
483 }
484
485 return -EIO;
486 }
487
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)488 int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
489 uint8_t *next_msg_flags, uint16_t slave)
490 {
491 const struct i2c_stm32_config *cfg = dev->config;
492 struct i2c_stm32_data *data = dev->data;
493 I2C_TypeDef *i2c = cfg->i2c;
494 bool is_timeout = false;
495
496 data->current.len = msg->len;
497 data->current.buf = msg->buf;
498 data->current.is_write = 0U;
499 data->current.is_arlo = 0U;
500 data->current.is_err = 0U;
501 data->current.is_nack = 0U;
502 data->current.msg = msg;
503
504 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
505
506 stm32_i2c_enable_transfer_interrupts(dev);
507 LL_I2C_EnableIT_RX(i2c);
508
509 if (k_sem_take(&data->device_sync_sem,
510 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
511 stm32_i2c_master_mode_end(dev);
512 k_sem_take(&data->device_sync_sem, K_FOREVER);
513 is_timeout = true;
514 }
515
516 if (data->current.is_nack || data->current.is_err ||
517 data->current.is_arlo || is_timeout) {
518 goto error;
519 }
520
521 return 0;
522 error:
523 if (data->current.is_arlo) {
524 LOG_DBG("%s: ARLO %d", __func__,
525 data->current.is_arlo);
526 data->current.is_arlo = 0U;
527 }
528
529 if (data->current.is_nack) {
530 LOG_DBG("%s: NACK", __func__);
531 data->current.is_nack = 0U;
532 }
533
534 if (data->current.is_err) {
535 LOG_DBG("%s: ERR %d", __func__,
536 data->current.is_err);
537 data->current.is_err = 0U;
538 }
539
540 if (is_timeout) {
541 LOG_DBG("%s: TIMEOUT", __func__);
542 }
543
544 return -EIO;
545 }
546
547 #else /* !CONFIG_I2C_STM32_INTERRUPT */
check_errors(const struct device * dev,const char * funcname)548 static inline int check_errors(const struct device *dev, const char *funcname)
549 {
550 const struct i2c_stm32_config *cfg = dev->config;
551 I2C_TypeDef *i2c = cfg->i2c;
552
553 if (LL_I2C_IsActiveFlag_NACK(i2c)) {
554 LL_I2C_ClearFlag_NACK(i2c);
555 LOG_DBG("%s: NACK", funcname);
556 goto error;
557 }
558
559 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
560 LL_I2C_ClearFlag_ARLO(i2c);
561 LOG_DBG("%s: ARLO", funcname);
562 goto error;
563 }
564
565 if (LL_I2C_IsActiveFlag_OVR(i2c)) {
566 LL_I2C_ClearFlag_OVR(i2c);
567 LOG_DBG("%s: OVR", funcname);
568 goto error;
569 }
570
571 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
572 LL_I2C_ClearFlag_BERR(i2c);
573 LOG_DBG("%s: BERR", funcname);
574 goto error;
575 }
576
577 return 0;
578 error:
579 if (LL_I2C_IsEnabledReloadMode(i2c)) {
580 LL_I2C_DisableReloadMode(i2c);
581 }
582 return -EIO;
583 }
584
msg_done(const struct device * dev,unsigned int current_msg_flags)585 static inline int msg_done(const struct device *dev,
586 unsigned int current_msg_flags)
587 {
588 const struct i2c_stm32_config *cfg = dev->config;
589 I2C_TypeDef *i2c = cfg->i2c;
590
591 /* Wait for transfer to complete */
592 while (!LL_I2C_IsActiveFlag_TC(i2c) && !LL_I2C_IsActiveFlag_TCR(i2c)) {
593 if (check_errors(dev, __func__)) {
594 return -EIO;
595 }
596 }
597 /* Issue stop condition if necessary */
598 if (current_msg_flags & I2C_MSG_STOP) {
599 LL_I2C_GenerateStopCondition(i2c);
600 while (!LL_I2C_IsActiveFlag_STOP(i2c)) {
601 }
602
603 LL_I2C_ClearFlag_STOP(i2c);
604 LL_I2C_DisableReloadMode(i2c);
605 }
606
607 return 0;
608 }
609
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)610 int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
611 uint8_t *next_msg_flags, uint16_t slave)
612 {
613 const struct i2c_stm32_config *cfg = dev->config;
614 I2C_TypeDef *i2c = cfg->i2c;
615 unsigned int len = 0U;
616 uint8_t *buf = msg->buf;
617
618 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
619
620 len = msg->len;
621 while (len) {
622 while (1) {
623 if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
624 break;
625 }
626
627 if (check_errors(dev, __func__)) {
628 return -EIO;
629 }
630 }
631
632 LL_I2C_TransmitData8(i2c, *buf);
633 buf++;
634 len--;
635 }
636
637 return msg_done(dev, msg->flags);
638 }
639
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave)640 int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
641 uint8_t *next_msg_flags, uint16_t slave)
642 {
643 const struct i2c_stm32_config *cfg = dev->config;
644 I2C_TypeDef *i2c = cfg->i2c;
645 unsigned int len = 0U;
646 uint8_t *buf = msg->buf;
647
648 msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
649
650 len = msg->len;
651 while (len) {
652 while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
653 if (check_errors(dev, __func__)) {
654 return -EIO;
655 }
656 }
657
658 *buf = LL_I2C_ReceiveData8(i2c);
659 buf++;
660 len--;
661 }
662
663 return msg_done(dev, msg->flags);
664 }
665 #endif
666
stm32_i2c_configure_timing(const struct device * dev,uint32_t clock)667 int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
668 {
669 const struct i2c_stm32_config *cfg = dev->config;
670 struct i2c_stm32_data *data = dev->data;
671 I2C_TypeDef *i2c = cfg->i2c;
672 uint32_t i2c_hold_time_min, i2c_setup_time_min;
673 uint32_t i2c_h_min_time, i2c_l_min_time;
674 uint32_t presc = 1U;
675 uint32_t timing = 0U;
676
677 /* Look for an adequate preset timing value */
678 for (uint32_t i = 0; i < cfg->n_timings; i++) {
679 const struct i2c_config_timing *preset = &cfg->timings[i];
680 uint32_t speed = i2c_map_dt_bitrate(preset->i2c_speed);
681
682 if ((I2C_SPEED_GET(speed) == I2C_SPEED_GET(data->dev_config))
683 && (preset->periph_clock == clock)) {
684 /* Found a matching periph clock and i2c speed */
685 LL_I2C_SetTiming(i2c, preset->timing_setting);
686 return 0;
687 }
688 }
689
690 /* No preset timing was provided, let's dynamically configure */
691 switch (I2C_SPEED_GET(data->dev_config)) {
692 case I2C_SPEED_STANDARD:
693 i2c_h_min_time = 4000U;
694 i2c_l_min_time = 4700U;
695 i2c_hold_time_min = 500U;
696 i2c_setup_time_min = 1250U;
697 break;
698 case I2C_SPEED_FAST:
699 i2c_h_min_time = 600U;
700 i2c_l_min_time = 1300U;
701 i2c_hold_time_min = 375U;
702 i2c_setup_time_min = 500U;
703 break;
704 default:
705 return -EINVAL;
706 }
707
708 /* Calculate period until prescaler matches */
709 do {
710 uint32_t t_presc = clock / presc;
711 uint32_t ns_presc = NSEC_PER_SEC / t_presc;
712 uint32_t sclh = i2c_h_min_time / ns_presc;
713 uint32_t scll = i2c_l_min_time / ns_presc;
714 uint32_t sdadel = i2c_hold_time_min / ns_presc;
715 uint32_t scldel = i2c_setup_time_min / ns_presc;
716
717 if ((sclh - 1) > 255 || (scll - 1) > 255) {
718 ++presc;
719 continue;
720 }
721
722 if (sdadel > 15 || (scldel - 1) > 15) {
723 ++presc;
724 continue;
725 }
726
727 timing = __LL_I2C_CONVERT_TIMINGS(presc - 1,
728 scldel - 1, sdadel, sclh - 1, scll - 1);
729 break;
730 } while (presc < 16);
731
732 if (presc >= 16U) {
733 LOG_DBG("I2C:failed to find prescaler value");
734 return -EINVAL;
735 }
736
737 LL_I2C_SetTiming(i2c, timing);
738
739 return 0;
740 }
741
