1 /**
2 ******************************************************************************
3 * @file sths34pf80_reg.c
4 * @author Sensors Software Solution Team
5 * @brief STHS34PF80 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "sths34pf80_reg.h"
21
22 /*
23 * Prototypes of routines used only throughout this driver and not exported
24 * outside as APIs
25 */
26 typedef struct
27 {
28 uint8_t int_pulsed : 1;
29 uint8_t comp_type : 1;
30 uint8_t sel_abs : 1;
31 } sths34pf80_algo_config_t;
32
33 static int32_t sths34pf80_reset_algo_bit_set(const stmdev_ctx_t *ctx);
34 static int32_t sths34pf80_algo_config_get(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t *val);
35 static int32_t sths34pf80_algo_config_set(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t val);
36 static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ctrl1_t *ctrl1);
37 static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx,
38 sths34pf80_ctrl1_t *ctrl1,
39 uint8_t odr_new);
40
41 /**
42 * @defgroup STHS34PF80
43 * @brief This file provides a set of functions needed to drive the
44 * sths34pf80 enhanced inertial module.
45 * @{
46 *
47 */
48
49 /**
50 * @defgroup Interfaces functions
51 * @brief This section provide a set of functions used to read and
52 * write a generic register of the device.
53 * MANDATORY: return 0 -> no Error.
54 * @{
55 *
56 */
57
58 #ifndef __weak
59 #define __weak __attribute__((weak))
60 #endif /* __weak */
61
62 /**
63 * @brief Read generic device register
64 *
65 * @param ctx communication interface handler.(ptr)
66 * @param reg first register address to read.
67 * @param data buffer for data read.(ptr)
68 * @param len number of consecutive register to read.
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
sths34pf80_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak sths34pf80_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL)
79 {
80 return -1;
81 }
82
83 ret = ctx->read_reg(ctx->handle, reg, data, len);
84
85 return ret;
86 }
87
88 /**
89 * @brief Write generic device register
90 *
91 * @param ctx communication interface handler.(ptr)
92 * @param reg first register address to write.
93 * @param data the buffer contains data to be written.(ptr)
94 * @param len number of consecutive register to write.
95 * @retval interface status (MANDATORY: return 0 -> no Error)
96 *
97 */
sths34pf80_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)98 int32_t __weak sths34pf80_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
99 uint8_t *data,
100 uint16_t len)
101 {
102 int32_t ret;
103
104 if (ctx == NULL)
105 {
106 return -1;
107 }
108
109 ret = ctx->write_reg(ctx->handle, reg, data, len);
110
111 return ret;
112 }
113
114 /**
115 * @}
116 *
117 */
118
119 /**
120 * @defgroup Common
121 * @brief Common
122 * @{/
123 *
124 */
125 /**
126 * @brief Device ID.[get]
127 *
128 * @param ctx read / write interface definitions
129 * @param val Device ID.
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
sths34pf80_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)133 int32_t sths34pf80_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
134 {
135 int32_t ret;
136
137 ret = sths34pf80_read_reg(ctx, STHS34PF80_WHO_AM_I, val, 1);
138
139 return ret;
140 }
141
142 /**
143 * @brief Select number of averages for object temperature.[set]
144 *
145 * @param ctx read / write interface definitions
146 * @param val AVG_TMOS_2, AVG_TMOS_8, AVG_TMOS_32, AVG_TMOS_128, AVG_TMOS_256, AVG_TMOS_512, AVG_TMOS_1024, AVG_TMOS_2048,
147 * @retval interface status (MANDATORY: return 0 -> no Error)
148 *
149 */
sths34pf80_avg_tobject_num_set(const stmdev_ctx_t * ctx,sths34pf80_avg_tobject_num_t val)150 int32_t sths34pf80_avg_tobject_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val)
151 {
152 sths34pf80_avg_trim_t avg_trim;
153 int32_t ret;
154
155 ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
156
157 if (ret == 0)
158 {
159 avg_trim.avg_tmos = ((uint8_t)val & 0x7U);
160 ret = sths34pf80_write_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
161 }
162
163 return ret;
164 }
165
166 /**
167 * @brief Select number of averages for object temperature.[get]
168 *
169 * @param ctx read / write interface definitions
170 * @param val AVG_TMOS_2, AVG_TMOS_8, AVG_TMOS_32, AVG_TMOS_128, AVG_TMOS_256, AVG_TMOS_512, AVG_TMOS_1024, AVG_TMOS_2048,
171 * @retval interface status (MANDATORY: return 0 -> no Error)
172 *
173 */
sths34pf80_avg_tobject_num_get(const stmdev_ctx_t * ctx,sths34pf80_avg_tobject_num_t * val)174 int32_t sths34pf80_avg_tobject_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val)
175 {
176 sths34pf80_avg_trim_t avg_trim;
177 int32_t ret;
178
179 ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
180
181 switch (avg_trim.avg_tmos)
182 {
183 case STHS34PF80_AVG_TMOS_2:
184 *val = STHS34PF80_AVG_TMOS_2;
185 break;
186
187 case STHS34PF80_AVG_TMOS_8:
188 *val = STHS34PF80_AVG_TMOS_8;
189 break;
190
191 case STHS34PF80_AVG_TMOS_32:
192 *val = STHS34PF80_AVG_TMOS_32;
193 break;
194
195 case STHS34PF80_AVG_TMOS_128:
196 *val = STHS34PF80_AVG_TMOS_128;
197 break;
198
199 case STHS34PF80_AVG_TMOS_256:
200 *val = STHS34PF80_AVG_TMOS_256;
201 break;
202
203 case STHS34PF80_AVG_TMOS_512:
204 *val = STHS34PF80_AVG_TMOS_512;
205 break;
206
207 case STHS34PF80_AVG_TMOS_1024:
208 *val = STHS34PF80_AVG_TMOS_1024;
209 break;
210
211 case STHS34PF80_AVG_TMOS_2048:
212 *val = STHS34PF80_AVG_TMOS_2048;
213 break;
214
215 default:
216 *val = STHS34PF80_AVG_TMOS_2;
217 break;
218 }
219 return ret;
220 }
221
222 /**
223 * @brief Select number of averages for ambient temperature.[set]
224 *
225 * @param ctx read / write interface definitions
226 * @param val AVG_T_8, AVG_T_4, AVG_T_2, AVG_T_1,
227 * @retval interface status (MANDATORY: return 0 -> no Error)
228 *
229 */
sths34pf80_avg_tambient_num_set(const stmdev_ctx_t * ctx,sths34pf80_avg_tambient_num_t val)230 int32_t sths34pf80_avg_tambient_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val)
231 {
232 sths34pf80_avg_trim_t avg_trim;
233 int32_t ret;
234
235 ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
236
237 if (ret == 0)
238 {
239 avg_trim.avg_t = ((uint8_t)val & 0x3U);
240 ret = sths34pf80_write_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
241 }
242
243 return ret;
244 }
245
246 /**
247 * @brief Select number of averages for ambient temperature.[get]
248 *
249 * @param ctx read / write interface definitions
250 * @param val AVG_T_8, AVG_T_4, AVG_T_2, AVG_T_1,
251 * @retval interface status (MANDATORY: return 0 -> no Error)
252 *
253 */
sths34pf80_avg_tambient_num_get(const stmdev_ctx_t * ctx,sths34pf80_avg_tambient_num_t * val)254 int32_t sths34pf80_avg_tambient_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t *val)
255 {
256 sths34pf80_avg_trim_t avg_trim;
257 int32_t ret;
258
259 ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
260
261 switch (avg_trim.avg_t)
262 {
263 case STHS34PF80_AVG_T_8:
264 *val = STHS34PF80_AVG_T_8;
265 break;
266
267 case STHS34PF80_AVG_T_4:
268 *val = STHS34PF80_AVG_T_4;
269 break;
270
271 case STHS34PF80_AVG_T_2:
272 *val = STHS34PF80_AVG_T_2;
273 break;
274
275 case STHS34PF80_AVG_T_1:
276 *val = STHS34PF80_AVG_T_1;
277 break;
278
279 default:
280 *val = STHS34PF80_AVG_T_8;
281 break;
282 }
283 return ret;
284 }
285
286 /**
287 * @brief temperature range.[set]
288 *
289 * @param ctx read / write interface definitions
290 * @param val range: GAIN_WIDE_MODE, GAIN_DEFAULT_MODE
291 * @retval interface status (MANDATORY: return 0 -> no Error)
292 *
293 */
sths34pf80_gain_mode_set(const stmdev_ctx_t * ctx,sths34pf80_gain_mode_t val)294 int32_t sths34pf80_gain_mode_set(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val)
295 {
296 sths34pf80_ctrl0_t ctrl0;
297 int32_t ret;
298
299 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1);
300
301 if (ret == 0)
302 {
303 ctrl0.gain = (uint8_t)val;
304 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1);
305 }
306
307 return ret;
308 }
309
310 /**
311 * @brief temperature range.[get]
312 *
313 * @param ctx read / write interface definitions
314 * @param val range: GAIN_WIDE_MODE, GAIN_DEFAULT_MODE
315 * @retval interface status (MANDATORY: return 0 -> no Error)
316 *
317 */
sths34pf80_gain_mode_get(const stmdev_ctx_t * ctx,sths34pf80_gain_mode_t * val)318 int32_t sths34pf80_gain_mode_get(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val)
319 {
320 sths34pf80_ctrl0_t ctrl0;
321 int32_t ret;
322
323 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1);
324
325 switch (ctrl0.gain)
326 {
327 case STHS34PF80_GAIN_WIDE_MODE:
328 *val = STHS34PF80_GAIN_WIDE_MODE;
329 break;
330
331 case STHS34PF80_GAIN_DEFAULT_MODE:
332 *val = STHS34PF80_GAIN_DEFAULT_MODE;
333 break;
334
335 default:
336 *val = STHS34PF80_GAIN_DEFAULT_MODE;
337 break;
338 }
339
340 return ret;
341 }
342
343 /**
344 * @brief sensitivity data.[set]
345 *
346 * @param ctx read / write interface definitions
347 * @param val IN: desired sensitivity value
348 * OUT: rounded sensitivity value
349 * @retval interface status (MANDATORY: return 0 -> no Error)
350 *
351 */
sths34pf80_tobject_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t * val)352 int32_t sths34pf80_tobject_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t *val)
353 {
354 sths34pf80_sens_data_t data;
355 int32_t ret;
356
357 data.sens = (*val >= 2048U) ?
358 (*val - 2048U + 8U) / 16U :
359 (*val - 2048U - 8U) / 16U;
360 ret = sths34pf80_write_reg(ctx, STHS34PF80_SENS_DATA, (uint8_t *)&data, 1);
361 *val = (int8_t)data.sens * 16U + 2048U;
362
363 return ret;
364 }
365
366 /**
367 * @brief sensitivity data.[get]
368 *
369 * @param ctx read / write interface definitions
370 * @param val rounded sensitivity value
371 * @retval interface status (MANDATORY: return 0 -> no Error)
372 *
373 */
sths34pf80_tobject_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)374 int32_t sths34pf80_tobject_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
375 {
376 sths34pf80_sens_data_t data;
377 int32_t ret;
378
379 ret = sths34pf80_read_reg(ctx, STHS34PF80_SENS_DATA, (uint8_t *)&data, 1);
380 *val = (int8_t)data.sens * 16 + 2048;
381
382 return ret;
383 }
384
385 /**
386 * @brief Enter to power-down in a safe way
387 *
388 * @param ctx read / write interface definitions
389 * @param ctrl1 Pointer to CTRL1 register
390 * @retval interface status (MANDATORY: return 0 -> no Error)
391 *
392 */
sths34pf80_safe_power_down(const stmdev_ctx_t * ctx,sths34pf80_ctrl1_t * ctrl1)393 static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ctrl1_t *ctrl1)
394 {
395 sths34pf80_func_status_t func_status;
396 sths34pf80_drdy_status_t status;
397 int32_t ret;
398
399 /* if sensor is already in power-down then do nothing */
400 if (ctrl1->odr == 0U)
401 {
402 return 0;
403 }
404
405 /* reset the DRDY bit */
406 ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1);
407
408 /* wait DRDY bit go to '1'. Maximum wait may be up to 4 sec (0.25 Hz) */
409 uint16_t retry = 0U;
410 do
411 {
412 ret += sths34pf80_drdy_status_get(ctx, &status);
413 ctx->mdelay(1);
414 } while (status.drdy == 0U && retry++ < 4000U);
415
416 if (ret != 0 || retry >= 4000U)
417 {
418 return -1;
419 };
420
421 /* perform power-down */
422 ctrl1->odr = 0U;
423 ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1);
424
425 /* reset the DRDY bit */
426 ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1);
427
428 return ret;
429 }
430
431 /**
432 * @brief Change odr in a safe way
433 *
434 * @param ctx read / write interface definitions
435 * @param ctrl1 Pointer to CTRL1 register
436 * @param odr_new Value of new odr to be set
437 * @retval interface status (MANDATORY: return 0 -> no Error)
438 *
439 */
sths34pf80_odr_safe_set(const stmdev_ctx_t * ctx,sths34pf80_ctrl1_t * ctrl1,uint8_t odr_new)440 static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx,
441 sths34pf80_ctrl1_t *ctrl1,
442 uint8_t odr_new)
443 {
444 int32_t ret;
445
446 /* perform power-down transition in a safe way. */
447 ret = sths34pf80_safe_power_down(ctx, ctrl1);
448
449 if (odr_new > 0U)
450 {
451 /*
452 * Do a clean reset algo procedure everytime odr is changed to an
453 * operative state.
454 */
455 ret += sths34pf80_reset_algo_bit_set(ctx);
456
457 /* set new odr */
458 ctrl1->odr = (odr_new & 0xfU);
459 ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1);
460 }
461
462 return ret;
463 }
464
465 /**
466 * @brief Selects the tmos odr.[set]
467 *
468 * @param ctx read / write interface definitions
469 * @param val ODR_OFF, ODR_AT_0Hz25, ODR_AT_0Hz50, ODR_1Hz, ODR_2Hz, ODR_4Hz, ODR_8Hz, ODR_15Hz, ODR_30Hz,
470 * @retval interface status (MANDATORY: return 0 -> no Error)
471 *
472 */
sths34pf80_odr_set(const stmdev_ctx_t * ctx,sths34pf80_odr_t val)473 int32_t sths34pf80_odr_set(const stmdev_ctx_t *ctx, sths34pf80_odr_t val)
474 {
475 sths34pf80_ctrl1_t ctrl1;
476 sths34pf80_avg_trim_t avg_trim;
477 sths34pf80_odr_t max_odr = STHS34PF80_ODR_AT_30Hz;
478 int32_t ret;
479
480 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
481
482 if (ret == 0)
483 {
484 ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
485
486 switch (avg_trim.avg_tmos)
487 {
488 default:
489 case STHS34PF80_AVG_TMOS_2:
490 case STHS34PF80_AVG_TMOS_8:
491 case STHS34PF80_AVG_TMOS_32:
492 max_odr = STHS34PF80_ODR_AT_30Hz;
493 break;
494 case STHS34PF80_AVG_TMOS_128:
495 max_odr = STHS34PF80_ODR_AT_8Hz;
496 break;
497 case STHS34PF80_AVG_TMOS_256:
498 max_odr = STHS34PF80_ODR_AT_4Hz;
499 break;
500 case STHS34PF80_AVG_TMOS_512:
501 max_odr = STHS34PF80_ODR_AT_2Hz;
502 break;
503 case STHS34PF80_AVG_TMOS_1024:
504 max_odr = STHS34PF80_ODR_AT_1Hz;
505 break;
506 case STHS34PF80_AVG_TMOS_2048:
507 max_odr = STHS34PF80_ODR_AT_0Hz50;
508 break;
509 }
510 }
511
512 if (ret == 0)
513 {
514 if (val > max_odr)
515 {
516 return -1;
517 }
518
519 ret = sths34pf80_odr_safe_set(ctx, &ctrl1, (uint8_t)val);
520 }
521
522 return ret;
523 }
524
525 /**
526 * @brief Selects the tmos odr.[get]
527 *
528 * @param ctx read / write interface definitions
529 * @param val ODR_OFF, ODR_AT_0Hz25, ODR_AT_0Hz50, ODR_1Hz, ODR_2Hz, ODR_4Hz, ODR_8Hz, ODR_15Hz, ODR_30Hz,
530 * @retval interface status (MANDATORY: return 0 -> no Error)
531 *
532 */
sths34pf80_odr_get(const stmdev_ctx_t * ctx,sths34pf80_odr_t * val)533 int32_t sths34pf80_odr_get(const stmdev_ctx_t *ctx, sths34pf80_odr_t *val)
534 {
535 sths34pf80_ctrl1_t ctrl1;
536 int32_t ret;
537
538 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
539
540 switch (ctrl1.odr)
541 {
542 case STHS34PF80_ODR_OFF:
543 *val = STHS34PF80_ODR_OFF;
544 break;
545
546 case STHS34PF80_ODR_AT_0Hz25:
547 *val = STHS34PF80_ODR_AT_0Hz25;
548 break;
549
550 case STHS34PF80_ODR_AT_0Hz50:
551 *val = STHS34PF80_ODR_AT_0Hz50;
552 break;
553
554 case STHS34PF80_ODR_AT_1Hz:
555 *val = STHS34PF80_ODR_AT_1Hz;
556 break;
557
558 case STHS34PF80_ODR_AT_2Hz:
559 *val = STHS34PF80_ODR_AT_2Hz;
560 break;
561
562 case STHS34PF80_ODR_AT_4Hz:
563 *val = STHS34PF80_ODR_AT_4Hz;
564 break;
565
566 case STHS34PF80_ODR_AT_8Hz:
567 *val = STHS34PF80_ODR_AT_8Hz;
568 break;
569
570 case STHS34PF80_ODR_AT_15Hz:
571 *val = STHS34PF80_ODR_AT_15Hz;
572 break;
573
574 case STHS34PF80_ODR_AT_30Hz:
575 *val = STHS34PF80_ODR_AT_30Hz;
576 break;
577
578 default:
579 *val = STHS34PF80_ODR_OFF;
580 break;
581 }
582 return ret;
583 }
584
585 /**
586 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
587 *
588 * @param ctx read / write interface definitions
589 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
590 * @retval interface status (MANDATORY: return 0 -> no Error)
591 *
592 */
sths34pf80_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)593 int32_t sths34pf80_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
594 {
595 sths34pf80_ctrl1_t ctrl1;
596 int32_t ret;
597
598 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
599
600 if (ret == 0)
601 {
602 ctrl1.bdu = val;
603 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
604 }
605
606 return ret;
607 }
608
609 /**
610 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
611 *
612 * @param ctx read / write interface definitions
613 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
614 * @retval interface status (MANDATORY: return 0 -> no Error)
615 *
616 */
sths34pf80_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)617 int32_t sths34pf80_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
618 {
619 sths34pf80_ctrl1_t ctrl1;
620 int32_t ret;
621
622 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
623
624 *val = ctrl1.bdu;
625
626
627 return ret;
628 }
629
630 /**
631 * @brief Selects data output mode.[set]
632 *
633 * @param ctx read / write interface definitions
634 * @param val IDLE_MODE, ONE_SHOT
635 * @retval interface status (MANDATORY: return 0 -> no Error)
636 *
637 */
sths34pf80_one_shot_set(const stmdev_ctx_t * ctx,sths34pf80_one_shot_t val)638 int32_t sths34pf80_one_shot_set(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t val)
639 {
640 sths34pf80_ctrl2_t ctrl2;
641 int32_t ret;
642
643 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
644
645 if (ret == 0)
646 {
647 ctrl2.one_shot = ((uint8_t)val & 0x1U);
648 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
649 }
650
651 return ret;
652 }
653
654 /**
655 * @brief Selects data output mode.[get]
656 *
657 * @param ctx read / write interface definitions
658 * @param val IDLE_MODE, ONE_SHOT
659 * @retval interface status (MANDATORY: return 0 -> no Error)
660 *
661 */
sths34pf80_one_shot_get(const stmdev_ctx_t * ctx,sths34pf80_one_shot_t * val)662 int32_t sths34pf80_one_shot_get(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t *val)
663 {
664 sths34pf80_ctrl2_t ctrl2;
665 int32_t ret;
666
667 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
668
669 switch (ctrl2.one_shot)
670 {
671 case STHS34PF80_IDLE_MODE:
672 *val = STHS34PF80_IDLE_MODE;
673 break;
674
675 case STHS34PF80_ONE_SHOT:
676 *val = STHS34PF80_ONE_SHOT;
677 break;
678
679 default:
680 *val = STHS34PF80_IDLE_MODE;
681 break;
682 }
683 return ret;
684 }
685
686 /**
687 * @brief Change memory bank.[set]
688 *
689 * @param ctx read / write interface definitions
690 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
691 * @retval interface status (MANDATORY: return 0 -> no Error)
692 *
693 */
sths34pf80_mem_bank_set(const stmdev_ctx_t * ctx,sths34pf80_mem_bank_t val)694 int32_t sths34pf80_mem_bank_set(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val)
695 {
696 sths34pf80_ctrl2_t ctrl2;
697 int32_t ret;
698
699 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
700
701 if (ret == 0)
702 {
703 ctrl2.func_cfg_access = ((uint8_t)val & 0x1U);
704 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
705 }
706
707 return ret;
708 }
709
710 /**
711 * @brief Change memory bank.[get]
712 *
713 * @param ctx read / write interface definitions
714 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
715 * @retval interface status (MANDATORY: return 0 -> no Error)
716 *
717 */
sths34pf80_mem_bank_get(const stmdev_ctx_t * ctx,sths34pf80_mem_bank_t * val)718 int32_t sths34pf80_mem_bank_get(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val)
719 {
720 sths34pf80_ctrl2_t ctrl2;
721 int32_t ret;
722
723 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
724
725 switch (ctrl2.func_cfg_access)
726 {
727 case STHS34PF80_MAIN_MEM_BANK:
728 *val = STHS34PF80_MAIN_MEM_BANK;
729 break;
730
731 case STHS34PF80_EMBED_FUNC_MEM_BANK:
732 *val = STHS34PF80_EMBED_FUNC_MEM_BANK;
733 break;
734
735 default:
736 *val = STHS34PF80_MAIN_MEM_BANK;
737 break;
738 }
739 return ret;
740 }
741
742 /**
743 * @brief Global reset of the device.[set]
744 *
745 * @param ctx read / write interface definitions
746 * @param val READY, RESTORE_CTRL_REGS,
747 * @retval interface status (MANDATORY: return 0 -> no Error)
748 *
749 */
sths34pf80_boot_set(const stmdev_ctx_t * ctx,uint8_t val)750 int32_t sths34pf80_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
751 {
752 sths34pf80_ctrl2_t ctrl2;
753 int32_t ret;
754
755 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
756
757 if (ret == 0)
758 {
759 ctrl2.boot = val;
760 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
761 }
762
763 return ret;
764 }
765
766 /**
767 * @brief Global reset of the device.[get]
768 *
769 * @param ctx read / write interface definitions
770 * @param val READY, RESTORE_CTRL_REGS,
771 * @retval interface status (MANDATORY: return 0 -> no Error)
772 *
773 */
sths34pf80_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)774 int32_t sths34pf80_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
775 {
776 sths34pf80_ctrl2_t ctrl2;
777 int32_t ret;
778
779 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
780 *val = ctrl2.boot;
781
782 return ret;
783 }
784
785 /**
786 * @brief status of drdy.[get]
787 *
788 * @param ctx read / write interface definitions
789 * @param val status of drdy bit (TAMB, TOBJ, TAMB_SHOCK, TPRESENCE, TMOTION).
790 * @retval interface status (MANDATORY: return 0 -> no Error)
791 *
792 */
sths34pf80_drdy_status_get(const stmdev_ctx_t * ctx,sths34pf80_drdy_status_t * val)793 int32_t sths34pf80_drdy_status_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_status_t *val)
794 {
795 sths34pf80_status_t status;
796 int32_t ret;
797
798 ret = sths34pf80_read_reg(ctx, STHS34PF80_STATUS, (uint8_t *)&status, 1);
799
800 val->drdy = status.drdy;
801
802 return ret;
803 }
804
805 /**
806 * @brief status of internal functions.[get]
807 *
808 * @param ctx read / write interface definitions
809 * @param val status of internal functions.
810 * @retval interface status (MANDATORY: return 0 -> no Error)
811 *
812 */
sths34pf80_func_status_get(const stmdev_ctx_t * ctx,sths34pf80_func_status_t * val)813 int32_t sths34pf80_func_status_get(const stmdev_ctx_t *ctx, sths34pf80_func_status_t *val)
814 {
815 sths34pf80_func_status_t func_status;
816 int32_t ret;
817
818 ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1);
819
820 val->tamb_shock_flag = func_status.tamb_shock_flag;
821 val->mot_flag = func_status.mot_flag;
822 val->pres_flag = func_status.pres_flag;
823
824 return ret;
825 }
826
827 /**
828 * @brief Object temperature output register.[get]
829 *
830 * @param ctx read / write interface definitions
831 * @param val Object temperature output register.
832 * @retval interface status (MANDATORY: return 0 -> no Error)
833 *
834 */
sths34pf80_tobject_raw_get(const stmdev_ctx_t * ctx,int16_t * val)835 int32_t sths34pf80_tobject_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
836 {
837 uint8_t buff[2];
838 int32_t ret;
839
840 ret = sths34pf80_read_reg(ctx, STHS34PF80_TOBJECT_L, &buff[0], 2);
841
842 *val = (int16_t)buff[1];
843 *val = (*val * 256) + (int16_t)buff[0];
844
845 return ret;
846 }
847
848 /**
849 * @brief Ambient temperature output register.[get]
850 *
851 * @param ctx read / write interface definitions
852 * @param val Ambient temperature output register.
853 * @retval interface status (MANDATORY: return 0 -> no Error)
854 *
855 */
sths34pf80_tambient_raw_get(const stmdev_ctx_t * ctx,int16_t * val)856 int32_t sths34pf80_tambient_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
857 {
858 uint8_t buff[2];
859 int32_t ret;
860
861 ret = sths34pf80_read_reg(ctx, STHS34PF80_TAMBIENT_L, &buff[0], 2);
862
863 *val = (int16_t)buff[1];
864 *val = (*val * 256) + (int16_t)buff[0];
865
866 return ret;
867 }
868
869 /**
870 * @brief Object compensation output register.[get]
871 *
872 * @param ctx read / write interface definitions
873 * @param val Object compensation output register.
874 * @retval interface status (MANDATORY: return 0 -> no Error)
875 *
876 */
sths34pf80_tobj_comp_raw_get(const stmdev_ctx_t * ctx,int16_t * val)877 int32_t sths34pf80_tobj_comp_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
878 {
879 uint8_t buff[2];
880 int32_t ret;
881
882 ret = sths34pf80_read_reg(ctx, STHS34PF80_TOBJ_COMP_L, &buff[0], 2);
883
884 *val = (int16_t)buff[1];
885 *val = (*val * 256) + (int16_t)buff[0];
886
887 return ret;
888 }
889
890 /**
891 * @brief Presence algo data output register.[get]
892 *
893 * @param ctx read / write interface definitions
894 * @param val Presence algo data output register.
895 * @retval interface status (MANDATORY: return 0 -> no Error)
896 *
897 */
sths34pf80_tpresence_raw_get(const stmdev_ctx_t * ctx,int16_t * val)898 int32_t sths34pf80_tpresence_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
899 {
900 uint8_t buff[2];
901 int32_t ret;
902
903 ret = sths34pf80_read_reg(ctx, STHS34PF80_TPRESENCE_L, &buff[0], 2);
904
905 *val = (int16_t)buff[1];
906 *val = (*val * 256) + (int16_t)buff[0];
907
908 return ret;
909 }
910
911 /**
912 * @brief Motion algo data output register.[get]
913 *
914 * @param ctx read / write interface definitions
915 * @param val Motion algo data output register.
916 * @retval interface status (MANDATORY: return 0 -> no Error)
917 *
918 */
sths34pf80_tmotion_raw_get(const stmdev_ctx_t * ctx,int16_t * val)919 int32_t sths34pf80_tmotion_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
920 {
921 uint8_t buff[2];
922 int32_t ret;
923
924 ret = sths34pf80_read_reg(ctx, STHS34PF80_TMOTION_L, &buff[0], 2);
925
926 *val = (int16_t)buff[1];
927 *val = (*val * 256) + (int16_t)buff[0];
928
929 return ret;
930 }
931
932 /**
933 * @brief Temperature ambient shock algo data output register.[get]
934 *
935 * @param ctx read / write interface definitions
936 * @param val Temperature ambient shock algo data output register.
937 * @retval interface status (MANDATORY: return 0 -> no Error)
938 *
939 */
sths34pf80_tamb_shock_raw_get(const stmdev_ctx_t * ctx,int16_t * val)940 int32_t sths34pf80_tamb_shock_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
941 {
942 uint8_t buff[2];
943 int32_t ret;
944
945 ret = sths34pf80_read_reg(ctx, STHS34PF80_TAMB_SHOCK_L, &buff[0], 2);
946
947 *val = (int16_t)buff[1];
948 *val = (*val * 256) + (int16_t)buff[0];
949
950 return ret;
951 }
952
953 /**
954 * @}
955 *
956 */
957
958 /**
959 * @defgroup Filters
960 * @brief Filters
961 * @{/
962 *
963 */
964 /**
965 * @brief low-pass filter configuration.[set]
966 *
967 * @param ctx read / write interface definitions
968 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
969 * @retval interface status (MANDATORY: return 0 -> no Error)
970 *
971 */
sths34pf80_lpf_m_bandwidth_set(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t val)972 int32_t sths34pf80_lpf_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val)
973 {
974 sths34pf80_lpf1_t lpf1;
975 int32_t ret;
976
977 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
978
979 if (ret == 0)
980 {
981 lpf1.lpf_m = ((uint8_t)val & 0x7U);
982 ret = sths34pf80_write_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
983 }
984
985 return ret;
986 }
987
988 /**
989 * @brief low-pass filter configuration.[get]
990 *
991 * @param ctx read / write interface definitions
992 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
993 * @retval interface status (MANDATORY: return 0 -> no Error)
994 *
995 */
sths34pf80_lpf_m_bandwidth_get(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t * val)996 int32_t sths34pf80_lpf_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val)
997 {
998 sths34pf80_lpf1_t lpf1;
999 int32_t ret;
1000
1001 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
1002
1003 switch ((lpf1.lpf_m))
1004 {
1005 case STHS34PF80_LPF_ODR_DIV_9:
1006 *val = STHS34PF80_LPF_ODR_DIV_9;
1007 break;
1008
1009 case STHS34PF80_LPF_ODR_DIV_20:
1010 *val = STHS34PF80_LPF_ODR_DIV_20;
1011 break;
1012
1013 case STHS34PF80_LPF_ODR_DIV_50:
1014 *val = STHS34PF80_LPF_ODR_DIV_50;
1015 break;
1016
1017 case STHS34PF80_LPF_ODR_DIV_100:
1018 *val = STHS34PF80_LPF_ODR_DIV_100;
1019 break;
1020
1021 case STHS34PF80_LPF_ODR_DIV_200:
1022 *val = STHS34PF80_LPF_ODR_DIV_200;
1023 break;
1024
1025 case STHS34PF80_LPF_ODR_DIV_400:
1026 *val = STHS34PF80_LPF_ODR_DIV_400;
1027 break;
1028
1029 case STHS34PF80_LPF_ODR_DIV_800:
1030 *val = STHS34PF80_LPF_ODR_DIV_800;
1031 break;
1032
1033 default:
1034 *val = STHS34PF80_LPF_ODR_DIV_9;
1035 break;
1036 }
1037 return ret;
1038 }
1039
1040 /**
1041 * @brief low-pass filter configuration.[set]
1042 *
1043 * @param ctx read / write interface definitions
1044 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
1045 * @retval interface status (MANDATORY: return 0 -> no Error)
1046 *
1047 */
sths34pf80_lpf_p_m_bandwidth_set(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t val)1048 int32_t sths34pf80_lpf_p_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val)
1049 {
1050 sths34pf80_lpf1_t lpf1;
1051 int32_t ret;
1052
1053 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
1054
1055 if (ret == 0)
1056 {
1057 lpf1.lpf_p_m = ((uint8_t)val & 0x7U);
1058 ret = sths34pf80_write_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
1059 }
1060
1061 return ret;
1062 }
1063
1064 /**
1065 * @brief low-pass filter configuration.[get]
1066 *
1067 * @param ctx read / write interface definitions
1068 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
1069 * @retval interface status (MANDATORY: return 0 -> no Error)
1070 *
1071 */
sths34pf80_lpf_p_m_bandwidth_get(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t * val)1072 int32_t sths34pf80_lpf_p_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val)
1073 {
1074 sths34pf80_lpf1_t lpf1;
1075 int32_t ret;
1076
1077 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
1078
1079 switch ((lpf1.lpf_p_m))
1080 {
1081 case STHS34PF80_LPF_ODR_DIV_9:
1082 *val = STHS34PF80_LPF_ODR_DIV_9;
1083 break;
1084
1085 case STHS34PF80_LPF_ODR_DIV_20:
1086 *val = STHS34PF80_LPF_ODR_DIV_20;
1087 break;
1088
1089 case STHS34PF80_LPF_ODR_DIV_50:
1090 *val = STHS34PF80_LPF_ODR_DIV_50;
1091 break;
1092
1093 case STHS34PF80_LPF_ODR_DIV_100:
1094 *val = STHS34PF80_LPF_ODR_DIV_100;
1095 break;
1096
1097 case STHS34PF80_LPF_ODR_DIV_200:
1098 *val = STHS34PF80_LPF_ODR_DIV_200;
1099 break;
1100
1101 case STHS34PF80_LPF_ODR_DIV_400:
1102 *val = STHS34PF80_LPF_ODR_DIV_400;
1103 break;
1104
1105 case STHS34PF80_LPF_ODR_DIV_800:
1106 *val = STHS34PF80_LPF_ODR_DIV_800;
1107 break;
1108
1109 default:
1110 *val = STHS34PF80_LPF_ODR_DIV_9;
1111 break;
1112 }
1113 return ret;
1114 }
1115
1116 /**
1117 * @brief low-pass filter configuration.[set]
1118 *
1119 * @param ctx read / write interface definitions
1120 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
1121 * @retval interface status (MANDATORY: return 0 -> no Error)
1122 *
1123 */
sths34pf80_lpf_a_t_bandwidth_set(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t val)1124 int32_t sths34pf80_lpf_a_t_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val)
1125 {
1126 sths34pf80_lpf2_t lpf2;
1127 int32_t ret;
1128
1129 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1);
1130
1131 if (ret == 0)
1132 {
1133 lpf2.lpf_a_t = ((uint8_t)val & 0x7U);
1134 ret = sths34pf80_write_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1);
1135 }
1136
1137 return ret;
1138 }
1139
1140 /**
1141 * @brief low-pass filter configuration.[get]
1142 *
1143 * @param ctx read / write interface definitions
1144 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
1145 * @retval interface status (MANDATORY: return 0 -> no Error)
1146 *
1147 */
sths34pf80_lpf_a_t_bandwidth_get(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t * val)1148 int32_t sths34pf80_lpf_a_t_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val)
1149 {
1150 sths34pf80_lpf2_t lpf2;
1151 int32_t ret;
1152
1153 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1);
1154
1155 switch ((lpf2.lpf_a_t))
1156 {
1157 case STHS34PF80_LPF_ODR_DIV_9:
1158 *val = STHS34PF80_LPF_ODR_DIV_9;
1159 break;
1160
1161 case STHS34PF80_LPF_ODR_DIV_20:
1162 *val = STHS34PF80_LPF_ODR_DIV_20;
1163 break;
1164
1165 case STHS34PF80_LPF_ODR_DIV_50:
1166 *val = STHS34PF80_LPF_ODR_DIV_50;
1167 break;
1168
1169 case STHS34PF80_LPF_ODR_DIV_100:
1170 *val = STHS34PF80_LPF_ODR_DIV_100;
1171 break;
1172
1173 case STHS34PF80_LPF_ODR_DIV_200:
1174 *val = STHS34PF80_LPF_ODR_DIV_200;
1175 break;
1176
1177 case STHS34PF80_LPF_ODR_DIV_400:
1178 *val = STHS34PF80_LPF_ODR_DIV_400;
1179 break;
1180
1181 case STHS34PF80_LPF_ODR_DIV_800:
1182 *val = STHS34PF80_LPF_ODR_DIV_800;
1183 break;
1184
1185 default:
1186 *val = STHS34PF80_LPF_ODR_DIV_9;
1187 break;
1188 }
1189 return ret;
1190 }
1191
1192 /**
1193 * @brief low-pass filter configuration.[set]
1194 *
1195 * @param ctx read / write interface definitions
1196 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
1197 * @retval interface status (MANDATORY: return 0 -> no Error)
1198 *
1199 */
sths34pf80_lpf_p_bandwidth_set(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t val)1200 int32_t sths34pf80_lpf_p_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val)
1201 {
1202 sths34pf80_lpf2_t lpf2;
1203 int32_t ret;
1204
1205 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1);
1206
1207 if (ret == 0)
1208 {
1209 lpf2.lpf_p = ((uint8_t)val & 0x7U);
1210 ret = sths34pf80_write_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1);
1211 }
1212
1213 return ret;
1214 }
1215
1216 /**
1217 * @brief low-pass filter configuration.[get]
1218 *
1219 * @param ctx read / write interface definitions
1220 * @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
1221 * @retval interface status (MANDATORY: return 0 -> no Error)
1222 *
1223 */
sths34pf80_lpf_p_bandwidth_get(const stmdev_ctx_t * ctx,sths34pf80_lpf_bandwidth_t * val)1224 int32_t sths34pf80_lpf_p_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val)
1225 {
1226 sths34pf80_lpf2_t lpf2;
1227 int32_t ret;
1228
1229 ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1);
1230
1231 switch ((lpf2.lpf_p))
1232 {
1233 case STHS34PF80_LPF_ODR_DIV_9:
1234 *val = STHS34PF80_LPF_ODR_DIV_9;
1235 break;
1236
1237 case STHS34PF80_LPF_ODR_DIV_20:
1238 *val = STHS34PF80_LPF_ODR_DIV_20;
1239 break;
1240
1241 case STHS34PF80_LPF_ODR_DIV_50:
1242 *val = STHS34PF80_LPF_ODR_DIV_50;
1243 break;
1244
1245 case STHS34PF80_LPF_ODR_DIV_100:
1246 *val = STHS34PF80_LPF_ODR_DIV_100;
1247 break;
1248
1249 case STHS34PF80_LPF_ODR_DIV_200:
1250 *val = STHS34PF80_LPF_ODR_DIV_200;
1251 break;
1252
1253 case STHS34PF80_LPF_ODR_DIV_400:
1254 *val = STHS34PF80_LPF_ODR_DIV_400;
1255 break;
1256
1257 case STHS34PF80_LPF_ODR_DIV_800:
1258 *val = STHS34PF80_LPF_ODR_DIV_800;
1259 break;
1260
1261 default:
1262 *val = STHS34PF80_LPF_ODR_DIV_9;
1263 break;
1264 }
1265 return ret;
1266 }
1267
1268 /**
1269 * @}
1270 *
1271 */
1272
1273 /**
1274 * @defgroup Interrupt PINs
1275 * @brief Interrupt PINs
1276 * @{/
1277 *
1278 */
1279 /**
1280 * @brief Selects interrupts to be routed.[set]
1281 *
1282 * @param ctx read / write interface definitions
1283 * @param val INT_HIZ, INT_DRDY, INT_OR,
1284 * @retval interface status (MANDATORY: return 0 -> no Error)
1285 *
1286 */
sths34pf80_route_int_set(const stmdev_ctx_t * ctx,sths34pf80_route_int_t val)1287 int32_t sths34pf80_route_int_set(const stmdev_ctx_t *ctx, sths34pf80_route_int_t val)
1288 {
1289 sths34pf80_ctrl3_t ctrl3;
1290 int32_t ret;
1291
1292 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1293
1294 if (ret == 0)
1295 {
1296 ctrl3.ien = ((uint8_t)val & 0x3U);
1297 if (val == STHS34PF80_INT_OR)
1298 {
1299 ctrl3.int_latched = 0; /* guarantee that latched is zero in INT_OR case */
1300 }
1301 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1302 }
1303
1304 return ret;
1305 }
1306
1307 /**
1308 * @brief Selects interrupts to be routed.[get]
1309 *
1310 * @param ctx read / write interface definitions
1311 * @param val INT_HIZ, INT_DRDY, INT_OR,
1312 * @retval interface status (MANDATORY: return 0 -> no Error)
1313 *
1314 */
sths34pf80_route_int_get(const stmdev_ctx_t * ctx,sths34pf80_route_int_t * val)1315 int32_t sths34pf80_route_int_get(const stmdev_ctx_t *ctx, sths34pf80_route_int_t *val)
1316 {
1317 sths34pf80_ctrl3_t ctrl3;
1318 int32_t ret;
1319
1320 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1321
1322 switch ((ctrl3.ien))
1323 {
1324 case STHS34PF80_INT_HIZ:
1325 *val = STHS34PF80_INT_HIZ;
1326 break;
1327
1328 case STHS34PF80_INT_DRDY:
1329 *val = STHS34PF80_INT_DRDY;
1330 break;
1331
1332 case STHS34PF80_INT_OR:
1333 *val = STHS34PF80_INT_OR;
1334 break;
1335
1336 default:
1337 *val = STHS34PF80_INT_HIZ;
1338 break;
1339 }
1340 return ret;
1341 }
1342
1343 /**
1344 * @brief Selects interrupts output.[set]
1345 *
1346 * @param ctx read / write interface definitions
1347 * @param val INT_NONE, INT_TSHOCK, INT_MOTION, INT_TSHOCK_MOTION, INT_PRESENCE, INT_TSHOCK_PRESENCE, INT_MOTION_PRESENCE, INT_ALL,
1348 * @retval interface status (MANDATORY: return 0 -> no Error)
1349 *
1350 */
sths34pf80_int_or_set(const stmdev_ctx_t * ctx,sths34pf80_int_or_t val)1351 int32_t sths34pf80_int_or_set(const stmdev_ctx_t *ctx, sths34pf80_int_or_t val)
1352 {
1353 sths34pf80_ctrl3_t ctrl3;
1354 int32_t ret;
1355
1356 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1357
1358 if (ret == 0)
1359 {
1360 ctrl3.int_msk = ((uint8_t)val & 0x7U);
1361 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1362 }
1363
1364 return ret;
1365 }
1366
1367 /**
1368 * @brief Selects interrupts output.[get]
1369 *
1370 * @param ctx read / write interface definitions
1371 * @param val INT_NONE, INT_TSHOCK, INT_MOTION, INT_TSHOCK_MOTION, INT_PRESENCE, INT_TSHOCK_PRESENCE, INT_MOTION_PRESENCE, INT_ALL,
1372 * @retval interface status (MANDATORY: return 0 -> no Error)
1373 *
1374 */
sths34pf80_int_or_get(const stmdev_ctx_t * ctx,sths34pf80_int_or_t * val)1375 int32_t sths34pf80_int_or_get(const stmdev_ctx_t *ctx, sths34pf80_int_or_t *val)
1376 {
1377 sths34pf80_ctrl3_t ctrl3;
1378 int32_t ret;
1379
1380 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1381
1382 switch ((ctrl3.int_msk))
1383 {
1384 case STHS34PF80_INT_NONE:
1385 *val = STHS34PF80_INT_NONE;
1386 break;
1387
1388 case STHS34PF80_INT_TSHOCK:
1389 *val = STHS34PF80_INT_TSHOCK;
1390 break;
1391
1392 case STHS34PF80_INT_MOTION:
1393 *val = STHS34PF80_INT_MOTION;
1394 break;
1395
1396 case STHS34PF80_INT_TSHOCK_MOTION:
1397 *val = STHS34PF80_INT_TSHOCK_MOTION;
1398 break;
1399
1400 case STHS34PF80_INT_PRESENCE:
1401 *val = STHS34PF80_INT_PRESENCE;
1402 break;
1403
1404 case STHS34PF80_INT_TSHOCK_PRESENCE:
1405 *val = STHS34PF80_INT_TSHOCK_PRESENCE;
1406 break;
1407
1408 case STHS34PF80_INT_MOTION_PRESENCE:
1409 *val = STHS34PF80_INT_MOTION_PRESENCE;
1410 break;
1411
1412 case STHS34PF80_INT_ALL:
1413 *val = STHS34PF80_INT_ALL;
1414 break;
1415
1416 default:
1417 *val = STHS34PF80_INT_NONE;
1418 break;
1419 }
1420 return ret;
1421 }
1422
1423 /**
1424 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
1425 *
1426 * @param ctx read / write interface definitions
1427 * @param val PUSH_PULL, OPEN_DRAIN,
1428 * @retval interface status (MANDATORY: return 0 -> no Error)
1429 *
1430 */
sths34pf80_int_mode_set(const stmdev_ctx_t * ctx,sths34pf80_int_mode_t val)1431 int32_t sths34pf80_int_mode_set(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t val)
1432 {
1433 sths34pf80_ctrl3_t ctrl3;
1434 int32_t ret;
1435
1436 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1437
1438 if (ret == 0)
1439 {
1440 ctrl3.pp_od = ((uint8_t)val.pin);
1441 ctrl3.int_h_l = ((uint8_t)val.polarity);
1442 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1443 }
1444
1445 return ret;
1446 }
1447
1448 /**
1449 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
1450 *
1451 * @param ctx read / write interface definitions
1452 * @param val PUSH_PULL, OPEN_DRAIN,
1453 * @retval interface status (MANDATORY: return 0 -> no Error)
1454 *
1455 */
sths34pf80_int_mode_get(const stmdev_ctx_t * ctx,sths34pf80_int_mode_t * val)1456 int32_t sths34pf80_int_mode_get(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val)
1457 {
1458 sths34pf80_ctrl3_t ctrl3;
1459 int32_t ret;
1460
1461 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1462
1463 switch (ctrl3.pp_od)
1464 {
1465 case STHS34PF80_PUSH_PULL:
1466 val->pin = STHS34PF80_PUSH_PULL;
1467 break;
1468
1469 case STHS34PF80_OPEN_DRAIN:
1470 val->pin = STHS34PF80_OPEN_DRAIN;
1471 break;
1472
1473 default:
1474 val->pin = STHS34PF80_PUSH_PULL;
1475 break;
1476 }
1477
1478 switch (ctrl3.int_h_l)
1479 {
1480 case STHS34PF80_ACTIVE_HIGH:
1481 val->polarity = STHS34PF80_ACTIVE_HIGH;
1482 break;
1483
1484 case STHS34PF80_ACTIVE_LOW:
1485 val->polarity = STHS34PF80_ACTIVE_LOW;
1486 break;
1487
1488 default:
1489 val->polarity = STHS34PF80_ACTIVE_HIGH;
1490 break;
1491 }
1492
1493 return ret;
1494 }
1495
1496 /**
1497 * @brief DRDY mode.[set]
1498 *
1499 * @param ctx read / write interface definitions
1500 * @param val DRDY_PULSED, DRDY_LATCHED,
1501 * @retval interface status (MANDATORY: return 0 -> no Error)
1502 *
1503 */
sths34pf80_drdy_mode_set(const stmdev_ctx_t * ctx,sths34pf80_drdy_mode_t val)1504 int32_t sths34pf80_drdy_mode_set(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val)
1505 {
1506 sths34pf80_ctrl3_t ctrl3;
1507 int32_t ret;
1508
1509 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1510
1511 if (ret == 0)
1512 {
1513 ctrl3.int_latched = (uint8_t)val;
1514 ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1515 }
1516
1517 return ret;
1518 }
1519
1520 /**
1521 * @brief DRDY mode.[get]
1522 *
1523 * @param ctx read / write interface definitions
1524 * @param val DRDY_PULSED, DRDY_LATCHED,
1525 * @retval interface status (MANDATORY: return 0 -> no Error)
1526 *
1527 */
sths34pf80_drdy_mode_get(const stmdev_ctx_t * ctx,sths34pf80_drdy_mode_t * val)1528 int32_t sths34pf80_drdy_mode_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val)
1529 {
1530 sths34pf80_ctrl3_t ctrl3;
1531 int32_t ret;
1532
1533 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1);
1534
1535 switch (ctrl3.int_latched)
1536 {
1537 case STHS34PF80_DRDY_PULSED:
1538 *val = STHS34PF80_DRDY_PULSED;
1539 break;
1540
1541 case STHS34PF80_DRDY_LATCHED:
1542 *val = STHS34PF80_DRDY_LATCHED;
1543 break;
1544
1545 default:
1546 *val = STHS34PF80_DRDY_PULSED;
1547 break;
1548 }
1549 return ret;
1550 }
1551
1552 /**
1553 * @}
1554 *
1555 */
1556
1557 /**
1558 * @defgroup Embedded
1559 * @brief Embedded
1560 * @{/
1561 *
1562 */
1563 /**
1564 * @brief Function Configuration write
1565 *
1566 * @param ctx read / write interface definitions
1567 * @param addr embedded register address
1568 * @param data embedded register data
1569 * @param len embedded register data len
1570 * @retval interface status (MANDATORY: return 0 -> no Error)
1571 *
1572 */
sths34pf80_func_cfg_write(const stmdev_ctx_t * ctx,uint8_t addr,uint8_t * data,uint8_t len)1573 int32_t sths34pf80_func_cfg_write(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len)
1574 {
1575 sths34pf80_ctrl1_t ctrl1;
1576 uint8_t odr;
1577 sths34pf80_page_rw_t page_rw = {0};
1578 int32_t ret;
1579 uint8_t i;
1580
1581 /* Save current odr and enter PD mode */
1582 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1583 odr = ctrl1.odr;
1584 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1585
1586 /* Enable access to embedded functions register */
1587 ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK);
1588
1589 /* Enable write mode */
1590 page_rw.func_cfg_write = 1;
1591 ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1);
1592
1593 /* Select register address (it will autoincrement when writing) */
1594 ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, &addr, 1);
1595
1596 for (i = 0; i < len; i++)
1597 {
1598 /* Write data */
1599 ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data[i], 1);
1600 }
1601
1602 /* Disable write mode */
1603 page_rw.func_cfg_write = 0;
1604 ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1);
1605
1606 /* Disable access to embedded functions register */
1607 ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK);
1608
1609 /* Set saved odr back */
1610 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1611
1612 return ret;
1613 }
1614
1615 /**
1616 * @brief Function Configuration read
1617 *
1618 * @param ctx read / write interface definitions
1619 * @param addr embedded register address
1620 * @param data embedded register data
1621 * @param len embedded register data len
1622 * @retval interface status (MANDATORY: return 0 -> no Error)
1623 *
1624 */
sths34pf80_func_cfg_read(const stmdev_ctx_t * ctx,uint8_t addr,uint8_t * data,uint8_t len)1625 int32_t sths34pf80_func_cfg_read(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len)
1626 {
1627 sths34pf80_ctrl1_t ctrl1;
1628 uint8_t odr;
1629 uint8_t reg_addr;
1630 sths34pf80_page_rw_t page_rw = {0};
1631 int32_t ret;
1632 uint8_t i;
1633
1634 /* Save current odr and enter PD mode */
1635 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1636 odr = ctrl1.odr;
1637 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1638
1639 /* Enable access to embedded functions register */
1640 ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK);
1641
1642 /* Enable read mode */
1643 page_rw.func_cfg_read = 1;
1644 ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1);
1645
1646 for (i = 0; i < len; i++)
1647 {
1648 /* Select register address */
1649 reg_addr = addr + i;
1650 ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, ®_addr, 1);
1651
1652 /* Read data */
1653 ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data[i], 1);
1654 }
1655
1656 /* Disable read mode */
1657 page_rw.func_cfg_read = 0;
1658 ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1);
1659
1660 /* Disable access to embedded functions register */
1661 ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK);
1662
1663 /* Set saved odr back */
1664 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1665
1666 return ret;
1667 }
1668
1669 /**
1670 * @brief Presence threshold.[set]
1671 *
1672 * @param ctx read / write interface definitions
1673 * @param val presence threshold level
1674 * @retval interface status (MANDATORY: return 0 -> no Error)
1675 *
1676 */
sths34pf80_presence_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1677 int32_t sths34pf80_presence_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1678 {
1679 sths34pf80_ctrl1_t ctrl1;
1680 uint8_t odr;
1681 uint8_t buff[2];
1682 int32_t ret;
1683
1684 if ((val & 0x8000U) != 0x0U)
1685 {
1686 /* threshold values are on 15 bits */
1687 return -1;
1688 }
1689
1690 /* Save current odr and enter PD mode */
1691 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1692 odr = ctrl1.odr;
1693 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1694
1695 buff[1] = (uint8_t)(val / 256U);
1696 buff[0] = (uint8_t)(val - (buff[1] * 256U));
1697 ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_PRESENCE_THS, &buff[0], 2);
1698
1699 ret += sths34pf80_reset_algo_bit_set(ctx);
1700
1701 /* Set saved odr back */
1702 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1703
1704 return ret;
1705 }
1706
1707 /**
1708 * @brief Presence threshold.[get]
1709 *
1710 * @param ctx read / write interface definitions
1711 * @param val presence threshold level
1712 * @retval interface status (MANDATORY: return 0 -> no Error)
1713 *
1714 */
sths34pf80_presence_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1715 int32_t sths34pf80_presence_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1716 {
1717 uint8_t buff[2];
1718 int32_t ret;
1719
1720 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_PRESENCE_THS, &buff[0], 2);
1721
1722 *val = buff[1];
1723 *val = (*val * 256U) + buff[0];
1724
1725 return ret;
1726 }
1727
1728 /**
1729 * @brief Motion threshold.[set]
1730 *
1731 * @param ctx read / write interface definitions
1732 * @param val motion threshold level
1733 * @retval interface status (MANDATORY: return 0 -> no Error)
1734 *
1735 */
sths34pf80_motion_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1736 int32_t sths34pf80_motion_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1737 {
1738 sths34pf80_ctrl1_t ctrl1;
1739 uint8_t odr;
1740 uint8_t buff[2];
1741 int32_t ret;
1742
1743 if ((val & 0x8000U) != 0x0U)
1744 {
1745 /* threshold values are on 15 bits */
1746 return -1;
1747 }
1748
1749 /* Save current odr and enter PD mode */
1750 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1751 odr = ctrl1.odr;
1752 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1753
1754 buff[1] = (uint8_t)(val / 256U);
1755 buff[0] = (uint8_t)(val - (buff[1] * 256U));
1756 ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_MOTION_THS, &buff[0], 2);
1757
1758 ret += sths34pf80_reset_algo_bit_set(ctx);
1759
1760 /* Set saved odr back */
1761 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1762
1763 return ret;
1764 }
1765
1766 /**
1767 * @brief Motion threshold.[get]
1768 *
1769 * @param ctx read / write interface definitions
1770 * @param val motion threshold level
1771 * @retval interface status (MANDATORY: return 0 -> no Error)
1772 *
1773 */
sths34pf80_motion_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1774 int32_t sths34pf80_motion_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1775 {
1776 uint8_t buff[2];
1777 int32_t ret;
1778
1779 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_MOTION_THS, &buff[0], 2);
1780
1781 *val = buff[1];
1782 *val = (*val * 256U) + buff[0];
1783
1784 return ret;
1785 }
1786
1787 /**
1788 * @brief Tambient shock threshold.[set]
1789 *
1790 * @param ctx read / write interface definitions
1791 * @param val Tambient shock threshold level
1792 * @retval interface status (MANDATORY: return 0 -> no Error)
1793 *
1794 */
sths34pf80_tambient_shock_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1795 int32_t sths34pf80_tambient_shock_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1796 {
1797 sths34pf80_ctrl1_t ctrl1;
1798 uint8_t odr;
1799 uint8_t buff[2];
1800 int32_t ret;
1801
1802 if ((val & 0x8000U) != 0x0U)
1803 {
1804 /* threshold values are on 15 bits */
1805 return -1;
1806 }
1807
1808 /* Save current odr and enter PD mode */
1809 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1810 odr = ctrl1.odr;
1811 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1812
1813 buff[1] = (uint8_t)(val / 256U);
1814 buff[0] = (uint8_t)(val - (buff[1] * 256U));
1815 ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_TAMB_SHOCK_THS, &buff[0], 2);
1816
1817 ret += sths34pf80_reset_algo_bit_set(ctx);
1818
1819 /* Set saved odr back */
1820 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1821
1822 return ret;
1823 }
1824
1825 /**
1826 * @brief Tambient shock threshold.[get]
1827 *
1828 * @param ctx read / write interface definitions
1829 * @param val Tambient shock threshold level
1830 * @retval interface status (MANDATORY: return 0 -> no Error)
1831 *
1832 */
sths34pf80_tambient_shock_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1833 int32_t sths34pf80_tambient_shock_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1834 {
1835 uint8_t buff[2];
1836 int32_t ret;
1837
1838 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_TAMB_SHOCK_THS, &buff[0], 2);
1839
1840 *val = buff[1];
1841 *val = (*val * 256U) + buff[0];
1842
1843 return ret;
1844 }
1845
1846 /**
1847 * @brief Motion hysteresis threshold.[set]
1848 *
1849 * @param ctx read / write interface definitions
1850 * @param val Motion hysteresis value
1851 * @retval interface status (MANDATORY: return 0 -> no Error)
1852 *
1853 */
sths34pf80_motion_hysteresis_set(const stmdev_ctx_t * ctx,uint8_t val)1854 int32_t sths34pf80_motion_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val)
1855 {
1856 sths34pf80_ctrl1_t ctrl1;
1857 uint8_t odr;
1858 int32_t ret;
1859
1860 /* Save current odr and enter PD mode */
1861 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1862 odr = ctrl1.odr;
1863 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1864
1865 ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_MOTION, &val, 1);
1866
1867 ret += sths34pf80_reset_algo_bit_set(ctx);
1868
1869 /* Set saved odr back */
1870 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1871
1872 return ret;
1873 }
1874
1875 /**
1876 * @brief Motion hysteresis threshold.[get]
1877 *
1878 * @param ctx read / write interface definitions
1879 * @param val Motion hysteresis value
1880 * @retval interface status (MANDATORY: return 0 -> no Error)
1881 *
1882 */
sths34pf80_motion_hysteresis_get(const stmdev_ctx_t * ctx,uint8_t * val)1883 int32_t sths34pf80_motion_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val)
1884 {
1885 int32_t ret;
1886
1887 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_HYST_MOTION, val, 1);
1888
1889 return ret;
1890 }
1891
1892 /**
1893 * @brief Presence hysteresis.[set]
1894 *
1895 * @param ctx read / write interface definitions
1896 * @param val Presence hysteresis value
1897 * @retval interface status (MANDATORY: return 0 -> no Error)
1898 *
1899 */
sths34pf80_presence_hysteresis_set(const stmdev_ctx_t * ctx,uint8_t val)1900 int32_t sths34pf80_presence_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val)
1901 {
1902 sths34pf80_ctrl1_t ctrl1;
1903 uint8_t odr;
1904 int32_t ret;
1905
1906 /* Save current odr and enter PD mode */
1907 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1908 odr = ctrl1.odr;
1909 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1910
1911 ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_PRESENCE, &val, 1);
1912
1913 ret += sths34pf80_reset_algo_bit_set(ctx);
1914
1915 /* Set saved odr back */
1916 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1917
1918 return ret;
1919 }
1920
1921 /**
1922 * @brief Presence hysteresis.[get]
1923 *
1924 * @param ctx read / write interface definitions
1925 * @param val Presence hysteresis value
1926 * @retval interface status (MANDATORY: return 0 -> no Error)
1927 *
1928 */
sths34pf80_presence_hysteresis_get(const stmdev_ctx_t * ctx,uint8_t * val)1929 int32_t sths34pf80_presence_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val)
1930 {
1931 int32_t ret;
1932
1933 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_HYST_PRESENCE, val, 1);
1934
1935 return ret;
1936 }
1937
1938 /**
1939 * @brief Tambient shock hysteresis.[set]
1940 *
1941 * @param ctx read / write interface definitions
1942 * @param val Tambient shock hysteresis value
1943 * @retval interface status (MANDATORY: return 0 -> no Error)
1944 *
1945 */
sths34pf80_tambient_shock_hysteresis_set(const stmdev_ctx_t * ctx,uint8_t val)1946 int32_t sths34pf80_tambient_shock_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val)
1947 {
1948 sths34pf80_ctrl1_t ctrl1;
1949 uint8_t odr;
1950 int32_t ret;
1951
1952 /* Save current odr and enter PD mode */
1953 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
1954 odr = ctrl1.odr;
1955 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
1956
1957 ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_TAMB_SHOCK, &val, 1);
1958
1959 ret += sths34pf80_reset_algo_bit_set(ctx);
1960
1961 /* Set saved odr back */
1962 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
1963
1964 return ret;
1965 }
1966
1967 /**
1968 * @brief Tambient shock hysteresis.[get]
1969 *
1970 * @param ctx read / write interface definitions
1971 * @param val Tambient shock hysteresis value
1972 * @retval interface status (MANDATORY: return 0 -> no Error)
1973 *
1974 */
sths34pf80_tambient_shock_hysteresis_get(const stmdev_ctx_t * ctx,uint8_t * val)1975 int32_t sths34pf80_tambient_shock_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val)
1976 {
1977 int32_t ret;
1978
1979 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_HYST_TAMB_SHOCK, val, 1);
1980
1981 return ret;
1982 }
1983
1984 /**
1985 * @brief Algo configuration.[set]
1986 *
1987 * @param ctx read / write interface definitions
1988 * @param val Algo configuration structure
1989 * @retval interface status (MANDATORY: return 0 -> no Error)
1990 *
1991 */
sths34pf80_algo_config_set(const stmdev_ctx_t * ctx,sths34pf80_algo_config_t val)1992 static int32_t sths34pf80_algo_config_set(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t val)
1993 {
1994 uint8_t tmp;
1995 int32_t ret;
1996
1997 tmp = (val.int_pulsed << 3) | (val.comp_type << 2) | (val.sel_abs << 1);
1998 ret = sths34pf80_func_cfg_write(ctx, STHS34PF80_ALGO_CONFIG, &tmp, 1);
1999
2000 return ret;
2001 }
2002
2003 /**
2004 * @brief Algo configuration.[get]
2005 *
2006 * @param ctx read / write interface definitions
2007 * @param val Algo configuration structure
2008 * @retval interface status (MANDATORY: return 0 -> no Error)
2009 *
2010 */
sths34pf80_algo_config_get(const stmdev_ctx_t * ctx,sths34pf80_algo_config_t * val)2011 static int32_t sths34pf80_algo_config_get(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t *val)
2012 {
2013 uint8_t tmp;
2014 int32_t ret;
2015
2016 ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_ALGO_CONFIG, &tmp, 1);
2017 val->sel_abs = (tmp >> 1) & 0x1U;
2018 val->comp_type = (tmp >> 2) & 0x1U;
2019 val->int_pulsed = (tmp >> 3) & 0x1U;
2020
2021 return ret;
2022 }
2023
2024 /**
2025 * @brief Tobject compensation.[set]
2026 *
2027 * @param ctx read / write interface definitions
2028 * @param val Ambient compensation for object temperature (0, 1)
2029 * @retval interface status (MANDATORY: return 0 -> no Error)
2030 *
2031 */
sths34pf80_tobject_algo_compensation_set(const stmdev_ctx_t * ctx,uint8_t val)2032 int32_t sths34pf80_tobject_algo_compensation_set(const stmdev_ctx_t *ctx, uint8_t val)
2033 {
2034 sths34pf80_ctrl1_t ctrl1;
2035 uint8_t odr;
2036 sths34pf80_algo_config_t config;
2037 int32_t ret;
2038
2039 /* Save current odr and enter PD mode */
2040 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
2041 odr = ctrl1.odr;
2042 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
2043 if (ret != 0)
2044 {
2045 return ret;
2046 }
2047
2048 ret = sths34pf80_algo_config_get(ctx, &config);
2049 config.comp_type = val;
2050 ret += sths34pf80_algo_config_set(ctx, config);
2051 ret += sths34pf80_reset_algo_bit_set(ctx);
2052
2053 /* Set saved odr back */
2054 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
2055
2056 return ret;
2057 }
2058
2059 /**
2060 * @brief Tobject compensation.[get]
2061 *
2062 * @param ctx read / write interface definitions
2063 * @param val Ambient compensation for object temperature (0, 1)
2064 * @retval interface status (MANDATORY: return 0 -> no Error)
2065 *
2066 */
sths34pf80_tobject_algo_compensation_get(const stmdev_ctx_t * ctx,uint8_t * val)2067 int32_t sths34pf80_tobject_algo_compensation_get(const stmdev_ctx_t *ctx, uint8_t *val)
2068 {
2069 sths34pf80_algo_config_t config;
2070 int32_t ret;
2071
2072 ret = sths34pf80_algo_config_get(ctx, &config);
2073 *val = config.comp_type;
2074
2075 return ret;
2076 }
2077
2078 /**
2079 * @brief presence absolute value.[set]
2080 *
2081 * @param ctx read / write interface definitions
2082 * @param val Presence absolute value (0, 1)
2083 * @retval interface status (MANDATORY: return 0 -> no Error)
2084 *
2085 */
sths34pf80_presence_abs_value_set(const stmdev_ctx_t * ctx,uint8_t val)2086 int32_t sths34pf80_presence_abs_value_set(const stmdev_ctx_t *ctx, uint8_t val)
2087 {
2088 sths34pf80_ctrl1_t ctrl1;
2089 uint8_t odr;
2090 sths34pf80_algo_config_t config;
2091 int32_t ret;
2092
2093 /* Save current odr and enter PD mode */
2094 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
2095 odr = ctrl1.odr;
2096 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0);
2097 if (ret != 0)
2098 {
2099 return ret;
2100 }
2101
2102 ret = sths34pf80_algo_config_get(ctx, &config);
2103 config.sel_abs = val;
2104 ret += sths34pf80_algo_config_set(ctx, config);
2105 ret += sths34pf80_reset_algo_bit_set(ctx);
2106
2107 /* Set saved odr back */
2108 ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr);
2109
2110 return ret;
2111 }
2112
2113 /**
2114 * @brief presence absolute value.[get]
2115 *
2116 * @param ctx read / write interface definitions
2117 * @param val Presence absolute value (0, 1)
2118 * @retval interface status (MANDATORY: return 0 -> no Error)
2119 *
2120 */
sths34pf80_presence_abs_value_get(const stmdev_ctx_t * ctx,uint8_t * val)2121 int32_t sths34pf80_presence_abs_value_get(const stmdev_ctx_t *ctx, uint8_t *val)
2122 {
2123 sths34pf80_algo_config_t config;
2124 int32_t ret;
2125
2126 ret = sths34pf80_algo_config_get(ctx, &config);
2127 *val = config.sel_abs;
2128
2129 return ret;
2130 }
2131
2132 /**
2133 * @brief int_or mode.[set]
2134 *
2135 * @param ctx read / write interface definitions
2136 * @param val int_pulsed value (0, 1)
2137 * @retval interface status (MANDATORY: return 0 -> no Error)
2138 *
2139 */
sths34pf80_int_or_pulsed_set(const stmdev_ctx_t * ctx,uint8_t val)2140 int32_t sths34pf80_int_or_pulsed_set(const stmdev_ctx_t *ctx, uint8_t val)
2141 {
2142 sths34pf80_algo_config_t config;
2143 int32_t ret;
2144
2145 ret = sths34pf80_algo_config_get(ctx, &config);
2146 config.int_pulsed = val;
2147 ret += sths34pf80_algo_config_set(ctx, config);
2148
2149 return ret;
2150 }
2151
2152 /**
2153 * @brief int_or mode.[get]
2154 *
2155 * @param ctx read / write interface definitions
2156 * @param val int_pulsed value (0, 1)
2157 * @retval interface status (MANDATORY: return 0 -> no Error)
2158 *
2159 */
sths34pf80_int_or_pulsed_get(const stmdev_ctx_t * ctx,uint8_t * val)2160 int32_t sths34pf80_int_or_pulsed_get(const stmdev_ctx_t *ctx, uint8_t *val)
2161 {
2162 sths34pf80_algo_config_t config;
2163 int32_t ret;
2164
2165 ret = sths34pf80_algo_config_get(ctx, &config);
2166 *val = config.int_pulsed;
2167
2168 return ret;
2169 }
2170
2171 /*
2172 * Internal routine to reset algo bit
2173 */
sths34pf80_reset_algo_bit_set(const stmdev_ctx_t * ctx)2174 static int32_t sths34pf80_reset_algo_bit_set(const stmdev_ctx_t *ctx)
2175 {
2176 sths34pf80_page_rw_t page_rw = {0};
2177 int32_t ret;
2178
2179 /* Enable access to embedded functions register */
2180 ret = sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK);
2181
2182 /* Enable write mode */
2183 page_rw.func_cfg_write = 1;
2184 ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1);
2185
2186 /* Select register address (it will autoincrement when writing) */
2187 uint8_t addr = STHS34PF80_RESET_ALGO;
2188 ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, &addr, 1);
2189
2190 /* Write data */
2191 uint8_t data = 0x01;
2192 ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data, 1);
2193
2194 /* Disable write mode */
2195 page_rw.func_cfg_write = 0;
2196 ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1);
2197
2198 /* Disable access to embedded functions register */
2199 ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK);
2200
2201 return ret;
2202 }
2203
2204 /**
2205 * @brief Reset algo
2206 *
2207 * @param ctx read / write interface definitions
2208 * @param val reset algo structure
2209 * @retval interface status (MANDATORY: return 0 -> no Error)
2210 *
2211 */
sths34pf80_algo_reset(const stmdev_ctx_t * ctx)2212 int32_t sths34pf80_algo_reset(const stmdev_ctx_t *ctx)
2213 {
2214 sths34pf80_ctrl1_t ctrl1;
2215 uint8_t odr;
2216 int32_t ret;
2217
2218 /* Save current odr and enter PD mode */
2219 ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
2220 odr = ctrl1.odr;
2221 ret += sths34pf80_safe_power_down(ctx, &ctrl1);
2222
2223 ret += sths34pf80_reset_algo_bit_set(ctx);
2224
2225 /* Set saved odr back */
2226 ctrl1.odr = odr;
2227 ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
2228
2229 return ret;
2230 }
2231
2232 /**
2233 * @}
2234 *
2235 */
2236
