1 /*
2 * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <string.h>
9 #include <stdbool.h>
10
11 #include "esp_attr.h"
12 #include "esp_err.h"
13
14 #include "esp_log.h"
15 #include "esp_chip_info.h"
16 #include "esp_app_format.h"
17
18 #include "esp_efuse.h"
19 #include "esp_private/cache_err_int.h"
20 #include "esp_clk_internal.h"
21 // For workaround `rtc_clk_recalib_bbpll()`
22 #include "esp_private/rtc_clk.h"
23
24 #include "esp_rom_efuse.h"
25 #include "esp_rom_uart.h"
26 #include "esp_rom_sys.h"
27 #include "esp_rom_caps.h"
28 #include "sdkconfig.h"
29
30 #if CONFIG_IDF_TARGET_ESP32
31 #include "soc/dport_reg.h"
32 #include "esp32/rtc.h"
33 #include "esp32/rom/cache.h"
34 #include "esp32/rom/secure_boot.h"
35 #elif CONFIG_IDF_TARGET_ESP32S2
36 #include "esp32s2/rtc.h"
37 #include "esp32s2/rom/cache.h"
38 #include "esp32s2/rom/secure_boot.h"
39 #include "esp32s2/memprot.h"
40 #elif CONFIG_IDF_TARGET_ESP32S3
41 #include "esp32s3/rtc.h"
42 #include "esp32s3/rom/cache.h"
43 #include "esp32s3/rom/secure_boot.h"
44 #include "esp_memprot.h"
45 #include "soc/assist_debug_reg.h"
46 #include "soc/system_reg.h"
47 #include "esp32s3/rom/opi_flash.h"
48 #elif CONFIG_IDF_TARGET_ESP32C3
49 #include "esp32c3/rtc.h"
50 #include "esp32c3/rom/cache.h"
51 #include "esp32c3/rom/secure_boot.h"
52 #include "esp_memprot.h"
53 #elif CONFIG_IDF_TARGET_ESP32C6
54 #include "esp32c6/rtc.h"
55 #include "esp32c6/rom/cache.h"
56 #include "esp_memprot.h"
57 #elif CONFIG_IDF_TARGET_ESP32H2
58 #include "esp32h2/rtc.h"
59 #include "esp32h2/rom/cache.h"
60 #include "esp_memprot.h"
61 #elif CONFIG_IDF_TARGET_ESP32C2
62 #include "esp32c2/rtc.h"
63 #include "esp32c2/rom/cache.h"
64 #include "esp32c2/rom/rtc.h"
65 #include "esp32c2/rom/secure_boot.h"
66 #endif
67
68 #include "esp_private/esp_mmu_map_private.h"
69 #if CONFIG_SPIRAM
70 #include "esp_psram.h"
71 #include "esp_private/mmu_psram_flash.h"
72 #include "esp_private/esp_psram_extram.h"
73 #endif
74
75 #include "esp_private/spi_flash_os.h"
76 #include "esp_private/mspi_timing_tuning.h"
77 #include "bootloader_flash_config.h"
78 #include "bootloader_flash.h"
79 #include "esp_private/crosscore_int.h"
80 #include "esp_flash_encrypt.h"
81
82 #include "esp_private/sleep_gpio.h"
83 #include "hal/wdt_hal.h"
84 #include "soc/rtc.h"
85 #include "hal/cache_hal.h"
86 #include "hal/cache_ll.h"
87 #include "hal/efuse_ll.h"
88 #include "soc/periph_defs.h"
89 #include "esp_cpu.h"
90 #include "esp_private/esp_clk.h"
91 #include "spi_flash_mmap.h"
92
93 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
94 #include "esp_private/trax.h"
95 #endif
96
97 #include "bootloader_mem.h"
98
99 #if CONFIG_APP_BUILD_TYPE_RAM
100 #include "esp_rom_spiflash.h"
101 #include "bootloader_init.h"
102 #endif // CONFIG_APP_BUILD_TYPE_RAM
103
104 //This dependency will be removed in the future
105 #include "soc/ext_mem_defs.h"
106
107 #include "esp_private/startup_internal.h"
108 #include "esp_private/system_internal.h"
109
110 extern int _bss_start;
111 extern int _bss_end;
112 extern int _rtc_bss_start;
113 extern int _rtc_bss_end;
114 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
115 extern int _bss_bt_start;
116 extern int _bss_bt_end;
117 #endif // CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
118 extern int _instruction_reserved_start;
119 extern int _instruction_reserved_end;
120 extern int _rodata_reserved_start;
121 extern int _rodata_reserved_end;
122
123 extern int _vector_table;
124
125 static const char *TAG = "cpu_start";
126
127 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
128 extern int _ext_ram_bss_start;
129 extern int _ext_ram_bss_end;
130 #endif
131
132 #ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
133 extern int _iram_bss_start;
134 extern int _iram_bss_end;
135 #endif
136
137 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
138 static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
139 static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
140
141 static volatile bool s_resume_cores;
142 #endif
143
core_intr_matrix_clear(void)144 static void core_intr_matrix_clear(void)
145 {
146 uint32_t core_id = esp_cpu_get_core_id();
147
148 for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
149 esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
150 }
151 }
152
153 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
startup_resume_other_cores(void)154 void startup_resume_other_cores(void)
155 {
156 s_resume_cores = true;
157 }
158
call_start_cpu1(void)159 void IRAM_ATTR call_start_cpu1(void)
160 {
161 esp_cpu_intr_set_ivt_addr(&_vector_table);
162
163 ets_set_appcpu_boot_addr(0);
164
165 bootloader_init_mem();
166
167 #if CONFIG_ESP_CONSOLE_NONE
168 esp_rom_install_channel_putc(1, NULL);
169 esp_rom_install_channel_putc(2, NULL);
170 #else // CONFIG_ESP_CONSOLE_NONE
171 esp_rom_install_uart_printf();
172 esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
173 #endif
174
175 #if CONFIG_IDF_TARGET_ESP32
176 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
177 DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
178 #else
179 REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
180 REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
181 #endif
182
183 s_cpu_up[1] = true;
184 ESP_EARLY_LOGI(TAG, "App cpu up.");
185
186 // Clear interrupt matrix for APP CPU core
187 core_intr_matrix_clear();
188
189 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
190 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
191 //has started, but it isn't active *on this CPU* yet.
192 esp_cache_err_int_init();
193 #endif
194
195 #if (CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP32_TRAX_TWOBANKS) || \
196 (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP32S3_TRAX_TWOBANKS)
197 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
198 #endif
199
200 s_cpu_inited[1] = true;
201
202 while (!s_resume_cores) {
203 esp_rom_delay_us(100);
204 }
205
206 SYS_STARTUP_FN();
207 }
208
start_other_core(void)209 static void start_other_core(void)
210 {
211 esp_chip_info_t chip_info;
212 esp_chip_info(&chip_info);
213
214 // If not the single core variant of a target - check this since there is
215 // no separate soc_caps.h for the single core variant.
216 if (!(chip_info.cores > 1)) {
217 ESP_EARLY_LOGE(TAG, "Running on single core variant of a chip, but app is built with multi-core support.");
218 ESP_EARLY_LOGE(TAG, "Check that CONFIG_FREERTOS_UNICORE is enabled in menuconfig");
219 abort();
220 }
221
222 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
223
224 #if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
225 Cache_Flush(1);
226 Cache_Read_Enable(1);
227 #endif // #if CONFIG_IDF_TARGET_ESP32 && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
228
229 esp_cpu_unstall(1);
230
231 // Enable clock and reset APP CPU. Note that OpenOCD may have already
232 // enabled clock and taken APP CPU out of reset. In this case don't reset
233 // APP CPU again, as that will clear the breakpoints which may have already
234 // been set.
235 #if CONFIG_IDF_TARGET_ESP32
236 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
237 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
238 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
239 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
240 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
241 }
242 #elif CONFIG_IDF_TARGET_ESP32S3
243 if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
244 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
245 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
246 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
247 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
248 }
249 #endif
250 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
251
252 bool cpus_up = false;
253
254 while (!cpus_up) {
255 cpus_up = true;
256 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
257 cpus_up &= s_cpu_up[i];
258 }
259 esp_rom_delay_us(100);
260 }
261 }
262
263 #if CONFIG_IDF_TARGET_ESP32
restore_app_mmu_from_pro_mmu(void)264 static void restore_app_mmu_from_pro_mmu(void)
265 {
266 const int mmu_reg_num = 2048;
267 volatile uint32_t* from = (uint32_t*)DR_REG_FLASH_MMU_TABLE_PRO;
268 volatile uint32_t* to = (uint32_t*)DR_REG_FLASH_MMU_TABLE_APP;
269 for (int i = 0; i < mmu_reg_num; i++) {
270 *(to++) = *(from++);
271 }
272 }
273 #endif
274 // This function is needed to make the multicore app runnable on a unicore bootloader (built with FREERTOS UNICORE).
275 // It does some cache settings for other CPUs.
do_multicore_settings(void)276 void IRAM_ATTR do_multicore_settings(void)
277 {
278 // We intentionally do not check the cache settings before changing them,
279 // because it helps to get the application to run on older bootloaders.
280 #ifdef CONFIG_IDF_TARGET_ESP32
281 if (!efuse_ll_get_disable_app_cpu()) {
282 Cache_Read_Disable(1);
283 Cache_Flush(1);
284 DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
285 mmu_init(1);
286 DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
287 // We do not enable cache for CPU1 now because it will be done later in start_other_core().
288 }
289 restore_app_mmu_from_pro_mmu();
290 #endif
291
292 cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0);
293 #ifndef CONFIG_IDF_TARGET_ESP32
294 // 1. disable the cache before changing its settings.
295 cache_hal_disable(CACHE_TYPE_ALL);
296 #endif
297 for (unsigned core = 1; core < SOC_CPU_CORES_NUM; core++) {
298 // 2. change cache settings. All cores must have the same settings.
299 cache_ll_l1_enable_bus(core, cache_bus_mask_core0);
300 }
301 #ifndef CONFIG_IDF_TARGET_ESP32
302 // 3. enable the cache after changing its settings.
303 cache_hal_enable(CACHE_TYPE_ALL);
304 #endif
305 }
306 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
307
308 /*
309 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
310 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
311 */
call_start_cpu0(void)312 void IRAM_ATTR call_start_cpu0(void)
313 {
314 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
315 soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
316 #else
317 soc_reset_reason_t __attribute__((unused)) rst_reas[1];
318 #endif
319
320 #ifdef __riscv
321 if (esp_cpu_dbgr_is_attached()) {
322 /* Let debugger some time to detect that target started, halt it, enable ebreaks and resume.
323 500ms should be enough. */
324 for (uint32_t ms_num = 0; ms_num < 2; ms_num++) {
325 esp_rom_delay_us(100000);
326 }
327 }
328 // Configure the global pointer register
329 // (This should be the first thing IDF app does, as any other piece of code could be
330 // relaxed by the linker to access something relative to __global_pointer$)
331 __asm__ __volatile__ (
332 ".option push\n"
333 ".option norelax\n"
334 "la gp, __global_pointer$\n"
335 ".option pop"
336 );
337 #endif
338
339 // Move exception vectors to IRAM
340 esp_cpu_intr_set_ivt_addr(&_vector_table);
341
342 rst_reas[0] = esp_rom_get_reset_reason(0);
343 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
344 rst_reas[1] = esp_rom_get_reset_reason(1);
345 #endif
346
347 //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
348 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
349
350 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
351 // Clear Bluetooth bss
352 memset(&_bss_bt_start, 0, (&_bss_bt_end - &_bss_bt_start) * sizeof(_bss_bt_start));
353 #endif // CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
354
355 #if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
356 // Clear IRAM BSS
357 memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start));
358 #endif
359
360 #if SOC_RTC_FAST_MEM_SUPPORTED || SOC_RTC_SLOW_MEM_SUPPORTED
361 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
362 if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) {
363 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
364 }
365 #endif
366
367 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
368 #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
369 ESP_EARLY_LOGI(TAG, "Unicore app");
370 #else
371 ESP_EARLY_LOGI(TAG, "Multicore app");
372 // It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
373 do_multicore_settings();
374 #endif
375 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
376
377 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
378 //cache hal ctx needs to be initialised
379 cache_hal_init();
380 #endif
381
382 // When the APP is loaded into ram for execution, some hardware initialization behaviors
383 // in the bootloader are still necessary
384 #if CONFIG_APP_BUILD_TYPE_RAM
385 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
386 #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
387 esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
388 #else
389 esp_rom_spiflash_attach(0, false);
390 #endif
391 #endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
392 bootloader_init();
393 #endif //#if CONFIG_APP_BUILD_TYPE_RAM
394
395 #ifndef CONFIG_BOOTLOADER_WDT_ENABLE
396 // from panic handler we can be reset by RWDT or TG0WDT
397 if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0
398 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
399 || rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0
400 #endif
401 ) {
402 wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
403 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
404 wdt_hal_disable(&rtc_wdt_ctx);
405 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
406 }
407 #endif
408
409 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
410 #if CONFIG_IDF_TARGET_ESP32S2
411 /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
412 extern void esp_config_instruction_cache_mode(void);
413 esp_config_instruction_cache_mode();
414
415 /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache.
416 Configure the mode of data : cache size, cache associated ways, cache line size.
417 Enable data cache, so if we don't use SPIRAM, it just works. */
418 extern void esp_config_data_cache_mode(void);
419 esp_config_data_cache_mode();
420 Cache_Enable_DCache(0);
421 #endif
422
423 #if CONFIG_IDF_TARGET_ESP32S3
424 /* Configure the mode of instruction cache : cache size, cache line size. */
425 extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
426 rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
427
428 /* If we need use SPIRAM, we should use data cache.
429 Configure the mode of data : cache size, cache line size.*/
430 Cache_Suspend_DCache();
431 extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
432 rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
433 Cache_Resume_DCache(0);
434 #endif // CONFIG_IDF_TARGET_ESP32S3
435
436 #if CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
437 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
438 // For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data
439 // are all in internal RAM. If the RAM loadable ELF has any requirement to memory map the
440 // external flash then it should use flash or partition mmap APIs.
441 uint32_t cache_mmu_irom_size = 0;
442 __attribute__((unused)) uint32_t cache_mmu_drom_size = 0;
443 #else // CONFIG_APP_BUILD_TYPE_ELF_RAM
444 uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
445 uint32_t cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
446
447 uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
448 __attribute__((unused)) uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
449 #endif // !CONFIG_APP_BUILD_TYPE_ELF_RAM
450
451 /* Configure the Cache MMU size for instruction and rodata in flash. */
452 Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
453 #endif // CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
454
455 #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
456 bool efuse_opflash_en = efuse_ll_get_flash_type();
457 if (!efuse_opflash_en) {
458 ESP_EARLY_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!");
459 abort();
460 }
461 #endif
462 esp_mspi_pin_init();
463 // For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
464 // So we have to read it here in SPI mode, before entering the OPI mode.
465 bootloader_flash_update_id();
466
467 // Configure the power related stuff. After this the MSPI timing tuning can be done.
468 esp_rtc_init();
469
470 /**
471 * This function initialise the Flash chip to the user-defined settings.
472 *
473 * In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
474 * different chips.
475 * In this stage, we re-configure the Flash (and MSPI) to required configuration
476 */
477 spi_flash_init_chip_state();
478 #if SOC_MEMSPI_SRC_FREQ_120M
479 // This function needs to be called when PLL is enabled. Needs to be called after spi_flash_init_chip_state in case
480 // some state of flash is modified.
481 mspi_timing_flash_tuning();
482 #endif
483
484 esp_mmu_map_init();
485
486 #if CONFIG_SPIRAM_BOOT_INIT
487 if (esp_psram_init() != ESP_OK) {
488 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
489 ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
490 abort();
491 #endif
492
493 #if CONFIG_SPIRAM_IGNORE_NOTFOUND
494 ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
495 #else
496 ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
497 abort();
498 #endif
499 }
500 #endif
501 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
502
503 if (esp_efuse_check_errors() != ESP_OK) {
504 esp_restart();
505 }
506
507 bootloader_init_mem();
508
509 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
510 s_cpu_up[0] = true;
511 #endif
512
513 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
514
515 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
516 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
517 start_other_core();
518 #else
519 ESP_EARLY_LOGI(TAG, "Single core mode");
520 #if CONFIG_IDF_TARGET_ESP32
521 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core
522 #elif CONFIG_IDF_TARGET_ESP32S3
523 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
524 #if SOC_APPCPU_HAS_CLOCK_GATING_BUG
525 /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
526 signals to ensure that the App core stops running in single-core mode. */
527 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
528 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
529 #endif
530 #endif // CONFIG_IDF_TARGET_ESP32
531 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
532 #endif // SOC_CPU_CORES_NUM > 1
533
534 #if CONFIG_SPIRAM_MEMTEST
535 if (esp_psram_is_initialized()) {
536 bool ext_ram_ok = esp_psram_extram_test();
537 if (!ext_ram_ok) {
538 ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
539 abort();
540 }
541 }
542 #endif //CONFIG_SPIRAM_MEMTEST
543
544 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
545 //TODO: IDF-5023, replace with MMU driver
546 #if CONFIG_IDF_TARGET_ESP32S3
547 int s_instr_flash2spiram_off = 0;
548 int s_rodata_flash2spiram_off = 0;
549 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
550 s_instr_flash2spiram_off = instruction_flash2spiram_offset();
551 #endif
552 #if CONFIG_SPIRAM_RODATA
553 s_rodata_flash2spiram_off = rodata_flash2spiram_offset();
554 #endif
555 Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), \
556 cache_mmu_drom_size / sizeof(uint32_t), \
557 (uint32_t)&_rodata_reserved_start, \
558 (uint32_t)&_rodata_reserved_end, \
559 s_instr_flash2spiram_off, \
560 s_rodata_flash2spiram_off);
561 #endif // CONFIG_IDF_TARGET_ESP32S3
562
563 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP || \
564 CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
565 uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0;
566 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP
567 icache_wrap_enable = 1;
568 #endif
569 #if CONFIG_ESP32S2_DATA_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
570 dcache_wrap_enable = 1;
571 #endif
572 extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
573 esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
574 #endif
575
576 #if CONFIG_ESP32S3_DATA_CACHE_16KB
577 Cache_Invalidate_DCache_All();
578 Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
579 #endif
580
581 #if CONFIG_IDF_TARGET_ESP32C2
582 // TODO : IDF-5020
583 #if CONFIG_ESP32C2_INSTRUCTION_CACHE_WRAP
584 extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable);
585 esp_enable_cache_wrap(1);
586 #endif
587 #endif
588 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
589
590 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
591 memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
592 #endif
593
594 //Enable trace memory and immediately start trace.
595 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
596 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3
597 #if CONFIG_ESP32_TRAX_TWOBANKS || CONFIG_ESP32S3_TRAX_TWOBANKS
598 trax_enable(TRAX_ENA_PRO_APP);
599 #else
600 trax_enable(TRAX_ENA_PRO);
601 #endif
602 #elif CONFIG_IDF_TARGET_ESP32S2
603 trax_enable(TRAX_ENA_PRO);
604 #endif
605 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
606 #endif // CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
607
608 esp_clk_init();
609 esp_perip_clk_init();
610
611 // Now that the clocks have been set-up, set the startup time from RTC
612 // and default RTC-backed system time provider.
613 g_startup_time = esp_rtc_get_time_us();
614
615 // Clear interrupt matrix for PRO CPU core
616 core_intr_matrix_clear();
617
618 #ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
619 #ifdef CONFIG_ESP_CONSOLE_UART
620 uint32_t clock_hz = esp_clk_apb_freq();
621 #if ESP_ROM_UART_CLK_IS_XTAL
622 clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM
623 #endif
624 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
625 esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
626 #endif
627 #endif
628
629 // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins
630 if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
631 esp_deep_sleep_wakeup_io_reset();
632 }
633
634 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
635 esp_cache_err_int_init();
636 #endif
637
638 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST
639 // Memprot cannot be locked during OS startup as the lock-on prevents any PMS changes until a next reboot
640 // If such a situation appears, it is likely an malicious attempt to bypass the system safety setup -> print error & reset
641
642 #if CONFIG_IDF_TARGET_ESP32S2
643 if (esp_memprot_is_locked_any()) {
644 #else
645 bool is_locked = false;
646 if (esp_mprot_is_conf_locked_any(&is_locked) != ESP_OK || is_locked) {
647 #endif
648 ESP_EARLY_LOGE(TAG, "Memprot feature locked after the system reset! Potential safety corruption, rebooting.");
649 esp_restart_noos_dig();
650 }
651
652 //default configuration of PMS Memprot
653 esp_err_t memp_err = ESP_OK;
654 #if CONFIG_IDF_TARGET_ESP32S2 //specific for ESP32S2 unless IDF-3024 is merged
655 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
656 memp_err = esp_memprot_set_prot(PANIC_HNDL_ON, MEMPROT_LOCK, NULL);
657 #else
658 memp_err = esp_memprot_set_prot(PANIC_HNDL_ON, MEMPROT_UNLOCK, NULL);
659 #endif
660 #else //CONFIG_IDF_TARGET_ESP32S2 specific end
661 esp_memp_config_t memp_cfg = ESP_MEMPROT_DEFAULT_CONFIG();
662 #if !CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
663 memp_cfg.lock_feature = false;
664 #endif
665 memp_err = esp_mprot_set_prot(&memp_cfg);
666 #endif //other IDF_TARGETS end
667
668 if (memp_err != ESP_OK) {
669 ESP_EARLY_LOGE(TAG, "Failed to set Memprot feature (0x%08X: %s), rebooting.", memp_err, esp_err_to_name(memp_err));
670 esp_restart_noos_dig();
671 }
672 #endif //CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && !CONFIG_ESP_SYSTEM_MEMPROT_TEST
673
674 // Read the application binary image header. This will also decrypt the header if the image is encrypted.
675 __attribute__((unused)) esp_image_header_t fhdr = {0};
676 #if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
677 fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO;
678 fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2;
679 fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB;
680
681 bootloader_flash_unlock();
682 #else
683 // We can access the image header through the cache by reading from the memory-mapped virtual DROM start offset
684 uint32_t fhdr_src_addr = (uint32_t)(&_rodata_reserved_start) - sizeof(esp_image_header_t) - sizeof(esp_image_segment_header_t);
685 hal_memcpy(&fhdr, (void *) fhdr_src_addr, sizeof(fhdr));
686 if (fhdr.magic != ESP_IMAGE_HEADER_MAGIC) {
687 ESP_EARLY_LOGE(TAG, "Invalid app image header");
688 abort();
689 }
690
691
692 #endif // CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
693
694 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
695 #if CONFIG_IDF_TARGET_ESP32
696 #if !CONFIG_SPIRAM_BOOT_INIT
697 // If psram is uninitialized, we need to improve some flash configuration.
698 bootloader_flash_clock_config(&fhdr);
699 bootloader_flash_gpio_config(&fhdr);
700 bootloader_flash_dummy_config(&fhdr);
701 bootloader_flash_cs_timing_config();
702 #endif //!CONFIG_SPIRAM_BOOT_INIT
703 #endif //CONFIG_IDF_TARGET_ESP32
704
705 #if CONFIG_SPI_FLASH_SIZE_OVERRIDE
706 int app_flash_size = esp_image_get_flash_size(fhdr.spi_size);
707 if (app_flash_size < 1 * 1024 * 1024) {
708 ESP_EARLY_LOGE(TAG, "Invalid flash size in app image header.");
709 abort();
710 }
711 bootloader_flash_update_size(app_flash_size);
712 #endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE
713 #endif //!CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
714
715 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
716 s_cpu_inited[0] = true;
717
718 volatile bool cpus_inited = false;
719
720 while (!cpus_inited) {
721 cpus_inited = true;
722 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
723 cpus_inited &= s_cpu_inited[i];
724 }
725 esp_rom_delay_us(100);
726 }
727 #endif
728
729 SYS_STARTUP_FN();
730 }
731
