1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_SSI_H 9 #define _HARDWARE_STRUCTS_SSI_H 10 11 /** 12 * \file rp2040/ssi.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/ssi.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/ssi.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0 28 // Control register 0 29 // 0x01000000 [24] SSTE (0) Slave select toggle enable 30 // 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format 31 // 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode + 32 // 0x0000f000 [15:12] CFS (0x0) Control frame size + 33 // 0x00000800 [11] SRL (0) Shift register loop (test mode) 34 // 0x00000400 [10] SLV_OE (0) Slave output enable 35 // 0x00000300 [9:8] TMOD (0x0) Transfer mode 36 // 0x00000080 [7] SCPOL (0) Serial clock polarity 37 // 0x00000040 [6] SCPH (0) Serial clock phase 38 // 0x00000030 [5:4] FRF (0x0) Frame format 39 // 0x0000000f [3:0] DFS (0x0) Data frame size 40 io_rw_32 ctrlr0; 41 42 _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1 43 // Master Control register 1 44 // 0x0000ffff [15:0] NDF (0x0000) Number of data frames 45 io_rw_32 ctrlr1; 46 47 _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR 48 // SSI Enable 49 // 0x00000001 [0] SSI_EN (0) SSI enable 50 io_rw_32 ssienr; 51 52 _REG_(SSI_MWCR_OFFSET) // SSI_MWCR 53 // Microwire Control 54 // 0x00000004 [2] MHS (0) Microwire handshaking 55 // 0x00000002 [1] MDD (0) Microwire control 56 // 0x00000001 [0] MWMOD (0) Microwire transfer mode 57 io_rw_32 mwcr; 58 59 _REG_(SSI_SER_OFFSET) // SSI_SER 60 // Slave enable 61 // 0x00000001 [0] SER (0) For each bit: + 62 io_rw_32 ser; 63 64 _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR 65 // Baud rate 66 // 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider 67 io_rw_32 baudr; 68 69 _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR 70 // TX FIFO threshold level 71 // 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold 72 io_rw_32 txftlr; 73 74 _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR 75 // RX FIFO threshold level 76 // 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold 77 io_rw_32 rxftlr; 78 79 _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR 80 // TX FIFO level 81 // 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level 82 io_ro_32 txflr; 83 84 _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR 85 // RX FIFO level 86 // 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level 87 io_ro_32 rxflr; 88 89 _REG_(SSI_SR_OFFSET) // SSI_SR 90 // Status register 91 // 0x00000040 [6] DCOL (0) Data collision error 92 // 0x00000020 [5] TXE (0) Transmission error 93 // 0x00000010 [4] RFF (0) Receive FIFO full 94 // 0x00000008 [3] RFNE (0) Receive FIFO not empty 95 // 0x00000004 [2] TFE (0) Transmit FIFO empty 96 // 0x00000002 [1] TFNF (0) Transmit FIFO not full 97 // 0x00000001 [0] BUSY (0) SSI busy flag 98 io_ro_32 sr; 99 100 _REG_(SSI_IMR_OFFSET) // SSI_IMR 101 // Interrupt mask 102 // 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask 103 // 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask 104 // 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask 105 // 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask 106 // 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask 107 // 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask 108 io_rw_32 imr; 109 110 _REG_(SSI_ISR_OFFSET) // SSI_ISR 111 // Interrupt status 112 // 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status 113 // 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status 114 // 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status 115 // 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status 116 // 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status 117 // 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status 118 io_ro_32 isr; 119 120 _REG_(SSI_RISR_OFFSET) // SSI_RISR 121 // Raw interrupt status 122 // 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status 123 // 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status 124 // 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status 125 // 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status 126 // 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status 127 // 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status 128 io_ro_32 risr; 129 130 _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR 131 // TX FIFO overflow interrupt clear 132 // 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt 133 io_ro_32 txoicr; 134 135 _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR 136 // RX FIFO overflow interrupt clear 137 // 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt 138 io_ro_32 rxoicr; 139 140 _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR 141 // RX FIFO underflow interrupt clear 142 // 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt 143 io_ro_32 rxuicr; 144 145 _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR 146 // Multi-master interrupt clear 147 // 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt 148 io_ro_32 msticr; 149 150 _REG_(SSI_ICR_OFFSET) // SSI_ICR 151 // Interrupt clear 152 // 0x00000001 [0] ICR (0) Clear-on-read all active interrupts 153 io_ro_32 icr; 154 155 _REG_(SSI_DMACR_OFFSET) // SSI_DMACR 156 // DMA control 157 // 0x00000002 [1] TDMAE (0) Transmit DMA enable 158 // 0x00000001 [0] RDMAE (0) Receive DMA enable 159 io_rw_32 dmacr; 160 161 _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR 162 // DMA TX data level 163 // 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level 164 io_rw_32 dmatdlr; 165 166 _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR 167 // DMA RX data level 168 // 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1) 169 io_rw_32 dmardlr; 170 171 _REG_(SSI_IDR_OFFSET) // SSI_IDR 172 // Identification register 173 // 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code 174 io_ro_32 idr; 175 176 _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID 177 // Version ID 178 // 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X 179 io_ro_32 ssi_version_id; 180 181 _REG_(SSI_DR0_OFFSET) // SSI_DR0 182 // Data Register 0 (of 36) 183 // 0xffffffff [31:0] DR (0x00000000) First data register of 36 184 io_rw_32 dr0; 185 186 uint32_t _pad0[35]; 187 188 _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY 189 // RX sample delay 190 // 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles) 191 io_rw_32 rx_sample_dly; 192 193 _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0 194 // SPI control 195 // 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to... 196 // 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable 197 // 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable 198 // 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable 199 // 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data... 200 // 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b) 201 // 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments) 202 // 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format 203 io_rw_32 spi_ctrlr0; 204 205 _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE 206 // TX drive edge 207 // 0x000000ff [7:0] TDE (0x00) TXD drive edge 208 io_rw_32 txd_drive_edge; 209 } ssi_hw_t; 210 211 #define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE) 212 static_assert(sizeof (ssi_hw_t) == 0x00fc, ""); 213 214 #endif // _HARDWARE_STRUCTS_SSI_H 215 216
