1 /*
2  * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <string.h>
8 #include "esp_types.h"
9 #include "esp_attr.h"
10 #include "esp_intr_alloc.h"
11 #include "esp_log.h"
12 #include "esp_err.h"
13 #include "esp_pm.h"
14 #include "esp_heap_caps.h"
15 #include "esp_rom_gpio.h"
16 #include "esp_rom_sys.h"
17 #include "soc/lldesc.h"
18 #include "soc/soc_caps.h"
19 #include "soc/spi_periph.h"
20 #include "soc/soc_memory_layout.h"
21 #include "hal/spi_ll.h"
22 #include "hal/spi_slave_hal.h"
23 #include "freertos/FreeRTOS.h"
24 #include "freertos/semphr.h"
25 #include "freertos/task.h"
26 #include "sdkconfig.h"
27 
28 #include "driver/gpio.h"
29 #include "driver/spi_common_internal.h"
30 #include "driver/spi_slave.h"
31 #include "hal/spi_slave_hal.h"
32 
33 static const char *SPI_TAG = "spi_slave";
34 #define SPI_CHECK(a, str, ret_val) \
35     if (!(a)) { \
36         ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
37         return (ret_val); \
38     }
39 
40 #ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
41 #define SPI_SLAVE_ISR_ATTR IRAM_ATTR
42 #else
43 #define SPI_SLAVE_ISR_ATTR
44 #endif
45 
46 #ifdef CONFIG_SPI_SLAVE_IN_IRAM
47 #define SPI_SLAVE_ATTR IRAM_ATTR
48 #else
49 #define SPI_SLAVE_ATTR
50 #endif
51 
52 typedef struct {
53     int id;
54     spi_slave_interface_config_t cfg;
55     intr_handle_t intr;
56     spi_slave_hal_context_t hal;
57     spi_slave_transaction_t *cur_trans;
58     uint32_t flags;
59     int max_transfer_sz;
60     QueueHandle_t trans_queue;
61     QueueHandle_t ret_queue;
62     bool dma_enabled;
63     uint32_t tx_dma_chan;
64     uint32_t rx_dma_chan;
65 #ifdef CONFIG_PM_ENABLE
66     esp_pm_lock_handle_t pm_lock;
67 #endif
68 } spi_slave_t;
69 
70 static spi_slave_t *spihost[SOC_SPI_PERIPH_NUM];
71 
72 static void IRAM_ATTR spi_intr(void *arg);
73 
is_valid_host(spi_host_device_t host)74 static inline bool is_valid_host(spi_host_device_t host)
75 {
76 //SPI1 can be used as GPSPI only on ESP32
77 #if CONFIG_IDF_TARGET_ESP32
78     return host >= SPI1_HOST && host <= SPI3_HOST;
79 #elif (SOC_SPI_PERIPH_NUM == 2)
80     return host == SPI2_HOST;
81 #elif (SOC_SPI_PERIPH_NUM == 3)
82     return host >= SPI2_HOST && host <= SPI3_HOST;
83 #endif
84 }
85 
bus_is_iomux(spi_slave_t * host)86 static inline bool bus_is_iomux(spi_slave_t *host)
87 {
88     return host->flags&SPICOMMON_BUSFLAG_IOMUX_PINS;
89 }
90 
freeze_cs(spi_slave_t * host)91 static void freeze_cs(spi_slave_t *host)
92 {
93     esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, spi_periph_signal[host->id].spics_in, false);
94 }
95 
96 // Use this function instead of cs_initial to avoid overwrite the output config
97 // This is used in test by internal gpio matrix connections
restore_cs(spi_slave_t * host)98 static inline void restore_cs(spi_slave_t *host)
99 {
100     if (bus_is_iomux(host)) {
101         gpio_iomux_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in);
102     } else {
103         esp_rom_gpio_connect_in_signal(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in, false);
104     }
105 }
106 
spi_slave_initialize(spi_host_device_t host,const spi_bus_config_t * bus_config,const spi_slave_interface_config_t * slave_config,spi_dma_chan_t dma_chan)107 esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, spi_dma_chan_t dma_chan)
108 {
109     bool spi_chan_claimed;
110     uint32_t actual_tx_dma_chan = 0;
111     uint32_t actual_rx_dma_chan = 0;
112     esp_err_t ret = ESP_OK;
113     esp_err_t err;
114     SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
115 #ifdef CONFIG_IDF_TARGET_ESP32
116     SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG );
117 #elif CONFIG_IDF_TARGET_ESP32S2
118     SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG );
119 #elif SOC_GDMA_SUPPORTED
120     SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG );
121 #endif
122     SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
123 #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM
124     SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM)==0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
125 #endif
126     SPI_CHECK(slave_config->spics_io_num < 0 || GPIO_IS_VALID_GPIO(slave_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG);
127 
128     spi_chan_claimed=spicommon_periph_claim(host, "spi slave");
129     SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
130 
131     spihost[host] = malloc(sizeof(spi_slave_t));
132     if (spihost[host] == NULL) {
133         ret = ESP_ERR_NO_MEM;
134         goto cleanup;
135     }
136     memset(spihost[host], 0, sizeof(spi_slave_t));
137     memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t));
138     spihost[host]->id = host;
139 
140     bool use_dma = (dma_chan != SPI_DMA_DISABLED);
141     spihost[host]->dma_enabled = use_dma;
142     if (use_dma) {
143         ret = spicommon_dma_chan_alloc(host, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan);
144         if (ret != ESP_OK) {
145             goto cleanup;
146         }
147     }
148 
149     err = spicommon_bus_initialize_io(host, bus_config, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags);
150     if (err!=ESP_OK) {
151         ret = err;
152         goto cleanup;
153     }
154     if (slave_config->spics_io_num >= 0) {
155         spicommon_cs_initialize(host, slave_config->spics_io_num, 0, !bus_is_iomux(spihost[host]));
156     }
157 
158     // The slave DMA suffers from unexpected transactions. Forbid reading if DMA is enabled by disabling the CS line.
159     if (use_dma) freeze_cs(spihost[host]);
160 
161     int dma_desc_ct = 0;
162     spihost[host]->tx_dma_chan = actual_tx_dma_chan;
163     spihost[host]->rx_dma_chan = actual_rx_dma_chan;
164     if (use_dma) {
165         //See how many dma descriptors we need and allocate them
166         dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN;
167         if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given
168         spihost[host]->max_transfer_sz = dma_desc_ct * SPI_MAX_DMA_LEN;
169     } else {
170         //We're limited to non-DMA transfers: the SPI work registers can hold 64 bytes at most.
171         spihost[host]->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE;
172     }
173 #ifdef CONFIG_PM_ENABLE
174     err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_slave",
175             &spihost[host]->pm_lock);
176     if (err != ESP_OK) {
177         ret = err;
178         goto cleanup;
179     }
180     // Lock APB frequency while SPI slave driver is in use
181     esp_pm_lock_acquire(spihost[host]->pm_lock);
182 #endif //CONFIG_PM_ENABLE
183 
184     //Create queues
185     spihost[host]->trans_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *));
186     spihost[host]->ret_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *));
187     if (!spihost[host]->trans_queue || !spihost[host]->ret_queue) {
188         ret = ESP_ERR_NO_MEM;
189         goto cleanup;
190     }
191 
192     int flags = bus_config->intr_flags | ESP_INTR_FLAG_INTRDISABLED;
193     err = esp_intr_alloc(spicommon_irqsource_for_host(host), flags, spi_intr, (void *)spihost[host], &spihost[host]->intr);
194     if (err != ESP_OK) {
195         ret = err;
196         goto cleanup;
197     }
198 
199     spi_slave_hal_context_t *hal = &spihost[host]->hal;
200     //assign the SPI, RX DMA and TX DMA peripheral registers beginning address
201     spi_slave_hal_config_t hal_config = {
202         .host_id = host,
203         .dma_in = SPI_LL_GET_HW(host),
204         .dma_out = SPI_LL_GET_HW(host)
205     };
206     spi_slave_hal_init(hal, &hal_config);
207 
208     if (dma_desc_ct) {
209         hal->dmadesc_tx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
210         hal->dmadesc_rx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
211         if (!hal->dmadesc_tx || !hal->dmadesc_rx) {
212             ret = ESP_ERR_NO_MEM;
213             goto cleanup;
214         }
215     }
216     hal->dmadesc_n = dma_desc_ct;
217     hal->rx_lsbfirst = (slave_config->flags & SPI_SLAVE_RXBIT_LSBFIRST) ? 1 : 0;
218     hal->tx_lsbfirst = (slave_config->flags & SPI_SLAVE_TXBIT_LSBFIRST) ? 1 : 0;
219     hal->mode = slave_config->mode;
220     hal->use_dma = use_dma;
221     hal->tx_dma_chan = actual_tx_dma_chan;
222     hal->rx_dma_chan = actual_rx_dma_chan;
223 
224     spi_slave_hal_setup_device(hal);
225 
226     return ESP_OK;
227 
228 cleanup:
229     if (spihost[host]) {
230         if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
231         if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
232         free(spihost[host]->hal.dmadesc_tx);
233         free(spihost[host]->hal.dmadesc_rx);
234 #ifdef CONFIG_PM_ENABLE
235         if (spihost[host]->pm_lock) {
236             esp_pm_lock_release(spihost[host]->pm_lock);
237             esp_pm_lock_delete(spihost[host]->pm_lock);
238         }
239 #endif
240     }
241     spi_slave_hal_deinit(&spihost[host]->hal);
242     if (spihost[host]->dma_enabled) {
243         spicommon_dma_chan_free(host);
244     }
245 
246     free(spihost[host]);
247     spihost[host] = NULL;
248     spicommon_periph_free(host);
249 
250     return ret;
251 }
252 
spi_slave_free(spi_host_device_t host)253 esp_err_t spi_slave_free(spi_host_device_t host)
254 {
255     SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
256     SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
257     if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
258     if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
259     if (spihost[host]->dma_enabled) {
260         spicommon_dma_chan_free(host);
261     }
262     free(spihost[host]->hal.dmadesc_tx);
263     free(spihost[host]->hal.dmadesc_rx);
264     esp_intr_free(spihost[host]->intr);
265 #ifdef CONFIG_PM_ENABLE
266     esp_pm_lock_release(spihost[host]->pm_lock);
267     esp_pm_lock_delete(spihost[host]->pm_lock);
268 #endif //CONFIG_PM_ENABLE
269     free(spihost[host]);
270     spihost[host] = NULL;
271     spicommon_periph_free(host);
272     return ESP_OK;
273 }
274 
275 
spi_slave_queue_trans(spi_host_device_t host,const spi_slave_transaction_t * trans_desc,TickType_t ticks_to_wait)276 esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
277 {
278     BaseType_t r;
279     SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
280     SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
281     SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
282 			"txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
283     SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->rx_buffer==NULL ||
284         (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) &&
285             (trans_desc->length%4==0)),
286         "rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG);
287 
288     SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG);
289     r = xQueueSend(spihost[host]->trans_queue, (void *)&trans_desc, ticks_to_wait);
290     if (!r) return ESP_ERR_TIMEOUT;
291     esp_intr_enable(spihost[host]->intr);
292     return ESP_OK;
293 }
294 
295 
spi_slave_get_trans_result(spi_host_device_t host,spi_slave_transaction_t ** trans_desc,TickType_t ticks_to_wait)296 esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait)
297 {
298     BaseType_t r;
299     SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
300     SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
301     r = xQueueReceive(spihost[host]->ret_queue, (void *)trans_desc, ticks_to_wait);
302     if (!r) return ESP_ERR_TIMEOUT;
303     return ESP_OK;
304 }
305 
306 
spi_slave_transmit(spi_host_device_t host,spi_slave_transaction_t * trans_desc,TickType_t ticks_to_wait)307 esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
308 {
309     esp_err_t ret;
310     spi_slave_transaction_t *ret_trans;
311     //ToDo: check if any spi transfers in flight
312     ret = spi_slave_queue_trans(host, trans_desc, ticks_to_wait);
313     if (ret != ESP_OK) return ret;
314     ret = spi_slave_get_trans_result(host, &ret_trans, ticks_to_wait);
315     if (ret != ESP_OK) return ret;
316     assert(ret_trans == trans_desc);
317     return ESP_OK;
318 }
319 
spi_slave_restart_after_dmareset(void * arg)320 static void SPI_SLAVE_ISR_ATTR spi_slave_restart_after_dmareset(void *arg)
321 {
322     spi_slave_t *host = (spi_slave_t *)arg;
323     esp_intr_enable(host->intr);
324 }
325 
326 //This is run in interrupt context and apart from initialization and destruction, this is the only code
327 //touching the host (=spihost[x]) variable. The rest of the data arrives in queues. That is why there are
328 //no muxes in this code.
spi_intr(void * arg)329 static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
330 {
331     BaseType_t r;
332     BaseType_t do_yield = pdFALSE;
333     spi_slave_transaction_t *trans = NULL;
334     spi_slave_t *host = (spi_slave_t *)arg;
335     spi_slave_hal_context_t *hal = &host->hal;
336 
337     assert(spi_slave_hal_usr_is_done(hal));
338 
339     bool use_dma = host->dma_enabled;
340     if (host->cur_trans) {
341         // When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready.
342         if (use_dma) freeze_cs(host);
343 
344         spi_slave_hal_store_result(hal);
345         host->cur_trans->trans_len = spi_slave_hal_get_rcv_bitlen(hal);
346 
347         if (spi_slave_hal_dma_need_reset(hal)) {
348             //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same
349             spicommon_dmaworkaround_req_reset(host->tx_dma_chan, spi_slave_restart_after_dmareset, host);
350         }
351         if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans);
352         //Okay, transaction is done.
353         //Return transaction descriptor.
354         xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield);
355         host->cur_trans = NULL;
356     }
357     if (use_dma) {
358         //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same
359         spicommon_dmaworkaround_idle(host->tx_dma_chan);
360         if (spicommon_dmaworkaround_reset_in_progress()) {
361             //We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr.
362             esp_intr_disable(host->intr);
363             if (do_yield) portYIELD_FROM_ISR();
364             return;
365         }
366     }
367 
368     //Disable interrupt before checking to avoid concurrency issue.
369     esp_intr_disable(host->intr);
370     //Grab next transaction
371     r = xQueueReceiveFromISR(host->trans_queue, &trans, &do_yield);
372     if (r) {
373         //enable the interrupt again if there is packet to send
374         esp_intr_enable(host->intr);
375 
376         //We have a transaction. Send it.
377         host->cur_trans = trans;
378 
379         hal->bitlen = trans->length;
380         hal->rx_buffer = trans->rx_buffer;
381         hal->tx_buffer = trans->tx_buffer;
382 
383         if (use_dma) {
384             //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same
385             spicommon_dmaworkaround_transfer_active(host->tx_dma_chan);
386         }
387 
388         spi_slave_hal_prepare_data(hal);
389 
390         //The slave rx dma get disturbed by unexpected transaction. Only connect the CS when slave is ready.
391         if (use_dma) {
392             restore_cs(host);
393         }
394 
395         //Kick off transfer
396         spi_slave_hal_user_start(hal);
397         if (host->cfg.post_setup_cb) host->cfg.post_setup_cb(trans);
398     }
399     if (do_yield) portYIELD_FROM_ISR();
400 }
401