1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <assert.h>
9 #include <string.h>
10 #include <stdio.h>
11 #include <sys/param.h> // For MIN/MAX(a, b)
12
13 #include <zephyr/kernel.h>
14 #include <soc/soc.h>
15 #include <soc/soc_memory_layout.h>
16 #include "soc/io_mux_reg.h"
17 #include "sdkconfig.h"
18 #include "esp_attr.h"
19 #include "esp_cpu.h"
20 #include "spi_flash_mmap.h"
21 #include "esp_log.h"
22 #include "esp_private/system_internal.h"
23 #include "esp_private/spi_flash_os.h"
24 #include "esp_private/esp_clk.h"
25 #include "esp_private/esp_gpio_reserve.h"
26 #if CONFIG_IDF_TARGET_ESP32
27 #include "esp32/rom/cache.h"
28 #include "esp32/rom/spi_flash.h"
29 #elif CONFIG_IDF_TARGET_ESP32S2
30 #include "esp32s2/rom/cache.h"
31 #elif CONFIG_IDF_TARGET_ESP32S3
32 #include "soc/spi_mem_reg.h"
33 #include "esp32s3/rom/opi_flash.h"
34 #include "esp32s3/rom/cache.h"
35 #include "esp32s3/opi_flash_private.h"
36 #elif CONFIG_IDF_TARGET_ESP32C3
37 #include "esp32c3/rom/cache.h"
38 #elif CONFIG_IDF_TARGET_ESP32C2
39 #include "esp32c2/rom/cache.h"
40 #elif CONFIG_IDF_TARGET_ESP32C6
41 #include "esp32c6/rom/cache.h"
42 #endif
43 #include "esp_rom_spiflash.h"
44 #include "esp_flash_partitions.h"
45 #include "esp_private/mspi_timing_tuning.h"
46 #include "esp_private/cache_utils.h"
47 #include "esp_flash.h"
48 #include "esp_attr.h"
49 #include "bootloader_flash.h"
50 #include "bootloader_flash_config.h"
51 #include "esp_compiler.h"
52 #include "esp_rom_efuse.h"
53 #if CONFIG_SPIRAM
54 #include "esp_private/esp_psram_io.h"
55 #endif
56 #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
57 #include "hal/cache_hal.h"
58 #endif
59
60 /* bytes erased by SPIEraseBlock() ROM function */
61 #define BLOCK_ERASE_SIZE 65536
62
63 /* Limit number of bytes written/read in a single SPI operation,
64 as these operations disable all higher priority tasks from running.
65 */
66 #ifdef CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
67 #define MAX_WRITE_CHUNK CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
68 #else
69 #define MAX_WRITE_CHUNK 8192
70 #endif // CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
71
72 #define MAX_READ_CHUNK 16384
73
74 static const char *TAG __attribute__((unused)) = "spi_flash";
75
76 const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_default_ops = {
77 .start = spi_flash_disable_interrupts_caches_and_other_cpu,
78 .end = spi_flash_enable_interrupts_caches_and_other_cpu,
79 };
80
81 const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_no_os_ops = {
82 .start = spi_flash_disable_interrupts_caches_and_other_cpu_no_os,
83 .end = spi_flash_enable_interrupts_caches_no_os,
84 };
85
86 static const spi_flash_guard_funcs_t *s_flash_guard_ops;
87
spi_flash_guard_set(const spi_flash_guard_funcs_t * funcs)88 void IRAM_ATTR spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs)
89 {
90 s_flash_guard_ops = funcs;
91 }
92
spi_flash_guard_get(void)93 const spi_flash_guard_funcs_t *IRAM_ATTR spi_flash_guard_get(void)
94 {
95 return s_flash_guard_ops;
96 }
97
98
99 #ifdef CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
100 #define UNSAFE_WRITE_ADDRESS abort()
101 #else
102 #define UNSAFE_WRITE_ADDRESS return false
103 #endif
104
105
is_safe_write_address(size_t addr,size_t size)106 static __attribute__((unused)) bool is_safe_write_address(size_t addr, size_t size)
107 {
108 if (!esp_partition_main_flash_region_safe(addr, size)) {
109 UNSAFE_WRITE_ADDRESS;
110 }
111 return true;
112 }
113
114 #if CONFIG_SPI_FLASH_ROM_IMPL
115 #include "esp_heap_caps.h"
116
spi_flash_malloc_internal(size_t size)117 void IRAM_ATTR *spi_flash_malloc_internal(size_t size)
118 {
119 return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
120 }
121
spi_flash_rom_impl_init(void)122 void IRAM_ATTR spi_flash_rom_impl_init(void)
123 {
124 spi_flash_guard_set(&g_flash_guard_default_ops);
125
126 /* These two functions are in ROM only */
127 extern void spi_flash_mmap_os_func_set(void *(*func1)(size_t size), void (*func2)(void *p));
128 spi_flash_mmap_os_func_set(spi_flash_malloc_internal, heap_caps_free);
129
130 extern esp_err_t spi_flash_mmap_page_num_init(uint32_t page_num);
131 spi_flash_mmap_page_num_init(128);
132 }
133 #endif
134
esp_mspi_pin_init(void)135 void IRAM_ATTR esp_mspi_pin_init(void)
136 {
137 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
138 bool octal_mspi_required = bootloader_flash_is_octal_mode_enabled();
139 #if CONFIG_SPIRAM_MODE_OCT
140 octal_mspi_required |= true;
141 #endif
142
143 if (octal_mspi_required) {
144 esp_rom_opiflash_pin_config();
145 mspi_timing_set_pin_drive_strength();
146 }
147 //Set F4R4 board pin drive strength. TODO: IDF-3663
148 #endif
149 /* Reserve the GPIO pins */
150 uint64_t reserve_pin_mask = 0;
151 for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
152 reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
153 }
154 esp_gpio_reserve_pins(reserve_pin_mask);
155 }
156
spi_flash_init_chip_state(void)157 esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
158 {
159 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
160 if (bootloader_flash_is_octal_mode_enabled()) {
161 return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
162 } else
163 #endif
164 {
165 #if CONFIG_IDF_TARGET_ESP32S3
166 // Currently, only esp32s3 allows high performance mode.
167 return spi_flash_enable_high_performance_mode();
168 #else
169 return ESP_OK;
170 #endif // CONFIG_IDF_TARGET_ESP32S3
171 }
172 }
173
spi_flash_set_rom_required_regs(void)174 void IRAM_ATTR spi_flash_set_rom_required_regs(void)
175 {
176 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
177 if (bootloader_flash_is_octal_mode_enabled()) {
178 //Disable the variable dummy mode when doing timing tuning
179 CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
180 /**
181 * STR /DTR mode setting is done every time when `esp_rom_opiflash_exec_cmd` is called
182 *
183 * Add any registers that are not set in ROM SPI flash functions here in the future
184 */
185 }
186 #endif
187 }
188
189 #if CONFIG_SPIRAM_MODE_OCT
190 // This function will only be called when Octal PSRAM enabled.
spi_flash_set_vendor_required_regs(void)191 void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
192 {
193 if (bootloader_flash_is_octal_mode_enabled()) {
194 esp_opiflash_set_required_regs();
195 SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 1, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
196 } else {
197 //Flash chip requires MSPI specifically, call this function to set them
198 // Set back MSPI registers after Octal PSRAM initialization.
199 SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 0, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
200 }
201 }
202 #endif
203
204 static const uint8_t s_mspi_io_num_default[] = {
205 SPI_CLK_GPIO_NUM,
206 SPI_Q_GPIO_NUM,
207 SPI_D_GPIO_NUM,
208 SPI_CS0_GPIO_NUM,
209 SPI_HD_GPIO_NUM,
210 SPI_WP_GPIO_NUM,
211 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
212 SPI_DQS_GPIO_NUM,
213 SPI_D4_GPIO_NUM,
214 SPI_D5_GPIO_NUM,
215 SPI_D6_GPIO_NUM,
216 SPI_D7_GPIO_NUM
217 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
218 };
219
esp_mspi_get_io(esp_mspi_io_t io)220 uint8_t esp_mspi_get_io(esp_mspi_io_t io)
221 {
222 #if CONFIG_SPIRAM
223 if (io == ESP_MSPI_IO_CS1) {
224 return esp_psram_io_get_cs_io();
225 }
226 #endif
227
228 assert(io >= ESP_MSPI_IO_CLK);
229 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
230 assert(io <= ESP_MSPI_IO_D7);
231 #else
232 assert(io <= ESP_MSPI_IO_WP);
233 #endif
234
235 #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
236 uint8_t mspi_io = 0;
237 uint32_t spiconfig = 0;
238
239 if (io == ESP_MSPI_IO_WP) {
240 /**
241 * wp pad is a bit special:
242 * 1. since 32's efuse does not have enough bits for wp pad, so wp pad config put in flash bin header
243 * 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num
244 */
245 #if CONFIG_IDF_TARGET_ESP32
246 return bootloader_flash_get_wp_pin();
247 #else
248 spiconfig = esp_rom_efuse_get_flash_wp_gpio();
249 return (spiconfig == 0x3f) ? s_mspi_io_num_default[io] : spiconfig & 0x3f;
250 #endif
251 }
252
253 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
254 spiconfig = (io < ESP_MSPI_IO_WP) ? esp_rom_efuse_get_flash_gpio_info() : esp_rom_efuse_get_opiconfig();
255 #else
256 spiconfig = esp_rom_efuse_get_flash_gpio_info();
257 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
258
259 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
260 mspi_io = s_mspi_io_num_default[io];
261 } else if (io < ESP_MSPI_IO_WP) {
262 /**
263 * [0 : 5] -- CLK
264 * [6 :11] -- Q(D1)
265 * [12:17] -- D(D0)
266 * [18:23] -- CS
267 * [24:29] -- HD(D3)
268 */
269 mspi_io = (spiconfig >> io * 6) & 0x3f;
270 }
271 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
272 else {
273 /**
274 * [0 : 5] -- DQS
275 * [6 :11] -- D4
276 * [12:17] -- D5
277 * [18:23] -- D6
278 * [24:29] -- D7
279 */
280 mspi_io = (spiconfig >> (io - ESP_MSPI_IO_DQS) * 6) & 0x3f;
281 }
282 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
283 return mspi_io;
284 #else // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
285 return s_mspi_io_num_default[io];
286 #endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
287 }
288
289 #if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
290
spi_flash_set_clock_src(soc_periph_mspi_clk_src_t clk_src)291 IRAM_ATTR void spi_flash_set_clock_src(soc_periph_mspi_clk_src_t clk_src)
292 {
293 cache_hal_freeze(CACHE_TYPE_INSTRUCTION);
294 spimem_flash_ll_set_clock_source(clk_src);
295 cache_hal_unfreeze(CACHE_TYPE_INSTRUCTION);
296 }
297 #endif // SOC_MEMSPI_CLOCK_IS_INDEPENDENT
298
