1 // Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 // HAL for SPI Flash (non-IRAM part)
16 // The IRAM part is in spi_flash_hal_iram.c, spi_flash_hal_gpspi.c, spi_flash_hal_common.inc.
17
18 #include <stdlib.h>
19 #include <string.h>
20 #include "soc/soc_caps.h"
21 #include "hal/spi_flash_hal.h"
22 #include "hal/log.h"
23
24 #define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
25
26 static const char TAG[] = "FLASH_HAL";
27
28 typedef struct {
29 int div;
30 spi_flash_ll_clock_reg_t clock_reg_val;
31 } spi_flash_hal_clock_config_t;
32
33
34
35
36 static const spi_flash_hal_clock_config_t spi_flash_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
37 {16, SPI_FLASH_LL_CLKREG_VAL_5MHZ},
38 {8, SPI_FLASH_LL_CLKREG_VAL_10MHZ},
39 {4, SPI_FLASH_LL_CLKREG_VAL_20MHZ},
40 {3, SPI_FLASH_LL_CLKREG_VAL_26MHZ},
41 {2, SPI_FLASH_LL_CLKREG_VAL_40MHZ},
42 {1, SPI_FLASH_LL_CLKREG_VAL_80MHZ},
43 };
44
45 #if !CONFIG_IDF_TARGET_ESP32
46 static const spi_flash_hal_clock_config_t spi_flash_gpspi_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
47 {16, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_5MHZ}},
48 {8, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_10MHZ}},
49 {4, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_20MHZ}},
50 {3, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_26MHZ}},
51 {2, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_40MHZ}},
52 {1, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_80MHZ}},
53 };
54 #else
55 #define spi_flash_gpspi_clk_cfg_reg spi_flash_clk_cfg_reg
56 #endif
57
get_dummy_n(bool gpio_is_used,int input_delay_ns,int eff_clk)58 static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk)
59 {
60 const int apbclk_kHz = APB_CLK_FREQ / 1000;
61 //calculate how many apb clocks a period has
62 const int apbclk_n = APB_CLK_FREQ / eff_clk;
63 const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0;
64
65 //calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off.
66 int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000;
67 if (apb_period_n < 0) {
68 apb_period_n = 0;
69 }
70
71 return apb_period_n / apbclk_n;
72 }
73
74 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
extra_dummy_under_timing_tuning(const spi_flash_hal_config_t * cfg)75 static inline int extra_dummy_under_timing_tuning(const spi_flash_hal_config_t *cfg)
76 {
77 bool main_flash = (cfg->host_id == SPI1_HOST && cfg->cs_num == 0);
78 int extra_dummy = 0;
79 if (main_flash) {
80 /**
81 * For Octal Flash, the dummy is `usr_dummy` + `extra_dummy`, they are in two different regs, we don't touch `extra_dummy` here, so set extra_dummy 0.
82 * Instead, for both Quad and Octal Flash, we use `usr_dummy` and set the whole dummy length (usr_dummy + extra_dummy) to this register.
83 */
84 extra_dummy = cfg->extra_dummy;
85 } else {
86 // TODO: for other flash chips, dummy get logic implement here. Currently, still calculate extra dummy by itself.
87 abort();
88 }
89
90 return extra_dummy;
91 }
92 #endif //SOC_SPI_MEM_SUPPORT_TIME_TUNING
93
spi_flash_hal_init(spi_flash_hal_context_t * data_out,const spi_flash_hal_config_t * cfg)94 esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg)
95 {
96 if (!esp_ptr_internal(data_out) && cfg->host_id == SPI1_HOST) {
97 return ESP_ERR_INVALID_ARG;
98 }
99 if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
100 return ESP_ERR_INVALID_ARG;
101 }
102
103 bool gpspi = (cfg->host_id > SPI1_HOST);
104 const spi_flash_hal_clock_config_t *clock_cfg = gpspi? &spi_flash_gpspi_clk_cfg_reg[cfg->speed]: &spi_flash_clk_cfg_reg[cfg->speed];
105
106 *data_out = (spi_flash_hal_context_t) {
107 .inst = data_out->inst, // Keeps the function pointer table
108 .spi = spi_flash_ll_get_hw(cfg->host_id),
109 .cs_num = cfg->cs_num,
110 .cs_hold = cfg->cs_hold,
111 .cs_setup = cfg->cs_setup,
112 .base_io_mode = cfg->default_io_mode,
113 };
114 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
115 if (cfg->using_timing_tuning) {
116 data_out->extra_dummy = extra_dummy_under_timing_tuning(cfg);
117 data_out->clock_conf = cfg->clock_config;
118 } else
119 #endif // SOC_SPI_MEM_SUPPORT_TIME_TUNING
120 {
121 data_out->extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, APB_CLK_FREQ/clock_cfg->div);
122 data_out->clock_conf = clock_cfg->clock_reg_val;
123 }
124
125
126 if (cfg->auto_sus_en) {
127 data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND;
128 data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME;
129 }
130
131 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
132 if (cfg->octal_mode_en) {
133 data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_OCTAL_MODE;
134 }
135
136 if (cfg->default_io_mode == SPI_FLASH_OPI_DTR) {
137 data_out->slicer_flags |= SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR;
138 }
139 #endif
140
141 HAL_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
142 return ESP_OK;
143 }
144
spi_flash_hal_supports_direct_write(spi_flash_host_inst_t * host,const void * p)145 bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p)
146 {
147 bool direct_write = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST)
148 || esp_ptr_in_dram(p) );
149 return direct_write;
150 }
151
152
spi_flash_hal_supports_direct_read(spi_flash_host_inst_t * host,const void * p)153 bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
154 {
155 //currently the host doesn't support to read through dma, no word-aligned requirements
156 bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST)
157 || esp_ptr_in_dram(p) );
158 return direct_read;
159 }
160
