1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8 #include <string.h>
9 #include "sdkconfig.h"
10 #include "driver/spi_master.h"
11 #include "soc/spi_periph.h"
12 #include "esp_types.h"
13 #include "esp_attr.h"
14 #include "esp_log.h"
15 #include "esp_err.h"
16 #include "soc/soc.h"
17 #include "soc/soc_caps.h"
18 #include "soc/soc_pins.h"
19 #include "soc/lldesc.h"
20 #include "driver/gpio.h"
21 #include "driver/periph_ctrl.h"
22 #include "esp_heap_caps.h"
23 #include "driver/spi_common_internal.h"
24 #include "stdatomic.h"
25 #include "hal/spi_hal.h"
26 #include "hal/gpio_hal.h"
27 #include "esp_rom_gpio.h"
28 #if CONFIG_IDF_TARGET_ESP32
29 #include "soc/dport_reg.h"
30 #endif
31 #if SOC_GDMA_SUPPORTED
32 #include "esp_private/gdma.h"
33 #endif
34
35 static const char *SPI_TAG = "spi";
36
37 #define SPI_CHECK(a, str, ret_val) do { \
38 if (!(a)) { \
39 ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
40 return (ret_val); \
41 } \
42 } while(0)
43
44 #define SPI_CHECK_PIN(pin_num, pin_name, check_output) if (check_output) { \
45 SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(pin_num), pin_name" not valid", ESP_ERR_INVALID_ARG); \
46 } else { \
47 SPI_CHECK(GPIO_IS_VALID_GPIO(pin_num), pin_name" not valid", ESP_ERR_INVALID_ARG); \
48 }
49
50 #define SPI_MAIN_BUS_DEFAULT() { \
51 .host_id = 0, \
52 .bus_attr = { \
53 .tx_dma_chan = 0, \
54 .rx_dma_chan = 0, \
55 .max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE, \
56 .dma_desc_num= 0, \
57 }, \
58 }
59
60 #define FUNC_GPIO PIN_FUNC_GPIO
61
62
63 typedef struct {
64 int host_id;
65 spi_destroy_func_t destroy_func;
66 void* destroy_arg;
67 spi_bus_attr_t bus_attr;
68 #if SOC_GDMA_SUPPORTED
69 gdma_channel_handle_t tx_channel;
70 gdma_channel_handle_t rx_channel;
71 #endif
72 } spicommon_bus_context_t;
73
74 //Periph 1 is 'claimed' by SPI flash code.
75 static atomic_bool spi_periph_claimed[SOC_SPI_PERIPH_NUM] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false),
76 #if (SOC_SPI_PERIPH_NUM >= 3)
77 ATOMIC_VAR_INIT(false),
78 #endif
79 #if (SOC_SPI_PERIPH_NUM >= 4)
80 ATOMIC_VAR_INIT(false),
81 #endif
82 };
83
84 static const char* spi_claiming_func[3] = {NULL, NULL, NULL};
85 static spicommon_bus_context_t s_mainbus = SPI_MAIN_BUS_DEFAULT();
86 static spicommon_bus_context_t* bus_ctx[SOC_SPI_PERIPH_NUM] = {&s_mainbus};
87
88 #if !SOC_GDMA_SUPPORTED
89 //Each bit stands for 1 dma channel, BIT(0) should be used for SPI1
90 static uint8_t spi_dma_chan_enabled = 0;
91 static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED;
92 #endif //#if !SOC_GDMA_SUPPORTED
93
94
is_valid_host(spi_host_device_t host)95 static inline bool is_valid_host(spi_host_device_t host)
96 {
97 #if (SOC_SPI_PERIPH_NUM == 2)
98 return host >= SPI1_HOST && host <= SPI2_HOST;
99 #elif (SOC_SPI_PERIPH_NUM == 3)
100 return host >= SPI1_HOST && host <= SPI3_HOST;
101 #endif
102 }
103
104 //----------------------------------------------------------alloc spi periph-------------------------------------------------------//
105 //Returns true if this peripheral is successfully claimed, false if otherwise.
spicommon_periph_claim(spi_host_device_t host,const char * source)106 bool spicommon_periph_claim(spi_host_device_t host, const char* source)
107 {
108 bool false_var = false;
109 bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &false_var, true);
110 if (ret) {
111 spi_claiming_func[host] = source;
112 periph_module_enable(spi_periph_signal[host].module);
113 } else {
114 ESP_EARLY_LOGE(SPI_TAG, "SPI%d already claimed by %s.", host+1, spi_claiming_func[host]);
115 }
116 return ret;
117 }
118
spicommon_periph_in_use(spi_host_device_t host)119 bool spicommon_periph_in_use(spi_host_device_t host)
120 {
121 return atomic_load(&spi_periph_claimed[host]);
122 }
123
124 //Returns true if this peripheral is successfully freed, false if otherwise.
spicommon_periph_free(spi_host_device_t host)125 bool spicommon_periph_free(spi_host_device_t host)
126 {
127 bool true_var = true;
128 bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &true_var, false);
129 if (ret) periph_module_disable(spi_periph_signal[host].module);
130 return ret;
131 }
132
spicommon_irqsource_for_host(spi_host_device_t host)133 int spicommon_irqsource_for_host(spi_host_device_t host)
134 {
135 return spi_periph_signal[host].irq;
136 }
137
spicommon_irqdma_source_for_host(spi_host_device_t host)138 int spicommon_irqdma_source_for_host(spi_host_device_t host)
139 {
140 return spi_periph_signal[host].irq_dma;
141 }
142
143 //----------------------------------------------------------alloc dma periph-------------------------------------------------------//
144 #if !SOC_GDMA_SUPPORTED
get_dma_periph(int dma_chan)145 static inline periph_module_t get_dma_periph(int dma_chan)
146 {
147 assert(dma_chan >= 1 && dma_chan <= SOC_SPI_DMA_CHAN_NUM);
148 #if CONFIG_IDF_TARGET_ESP32S2
149 if (dma_chan == 1) {
150 return PERIPH_SPI2_DMA_MODULE;
151 } else if (dma_chan == 2) {
152 return PERIPH_SPI3_DMA_MODULE;
153 } else {
154 abort();
155 }
156 #elif CONFIG_IDF_TARGET_ESP32
157 return PERIPH_SPI_DMA_MODULE;
158 #endif
159 }
160
claim_dma_chan(int dma_chan,uint32_t * out_actual_dma_chan)161 static bool claim_dma_chan(int dma_chan, uint32_t *out_actual_dma_chan)
162 {
163 bool ret = false;
164
165 portENTER_CRITICAL(&spi_dma_spinlock);
166 bool is_used = (BIT(dma_chan) & spi_dma_chan_enabled);
167 if (!is_used) {
168 spi_dma_chan_enabled |= BIT(dma_chan);
169 periph_module_enable(get_dma_periph(dma_chan));
170 *out_actual_dma_chan = dma_chan;
171 ret = true;
172 }
173 portEXIT_CRITICAL(&spi_dma_spinlock);
174
175 return ret;
176 }
177
connect_spi_and_dma(spi_host_device_t host,int dma_chan)178 static void connect_spi_and_dma(spi_host_device_t host, int dma_chan)
179 {
180 #if CONFIG_IDF_TARGET_ESP32
181 DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
182 #elif CONFIG_IDF_TARGET_ESP32S2
183 //On ESP32S2, each SPI controller has its own DMA channel. So there is no need to connect them.
184 #endif
185 }
186
alloc_dma_chan(spi_host_device_t host_id,spi_dma_chan_t dma_chan,uint32_t * out_actual_tx_dma_chan,uint32_t * out_actual_rx_dma_chan)187 static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan)
188 {
189 assert(is_valid_host(host_id));
190 #if CONFIG_IDF_TARGET_ESP32
191 assert(dma_chan > SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO);
192 #elif CONFIG_IDF_TARGET_ESP32S2
193 assert(dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO);
194 #endif
195
196 esp_err_t ret = ESP_OK;
197 bool success = false;
198 uint32_t actual_dma_chan = 0;
199
200 if (dma_chan == SPI_DMA_CH_AUTO) {
201 #if CONFIG_IDF_TARGET_ESP32
202 for (int i = 1; i < SOC_SPI_DMA_CHAN_NUM+1; i++) {
203 success = claim_dma_chan(i, &actual_dma_chan);
204 if (success) {
205 break;
206 }
207 }
208 #elif CONFIG_IDF_TARGET_ESP32S2
209 //On ESP32S2, each SPI controller has its own DMA channel
210 success = claim_dma_chan(host_id, &actual_dma_chan);
211 #endif //#if CONFIG_IDF_TARGET_XXX
212 } else {
213 success = claim_dma_chan((int)dma_chan, &actual_dma_chan);
214 }
215
216 //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same
217 *out_actual_tx_dma_chan = actual_dma_chan;
218 *out_actual_rx_dma_chan = actual_dma_chan;
219
220 if (!success) {
221 SPI_CHECK(false, "no available dma channel", ESP_ERR_NOT_FOUND);
222 }
223
224 connect_spi_and_dma(host_id, *out_actual_tx_dma_chan);
225
226 return ret;
227 }
228
229 #else //SOC_GDMA_SUPPORTED
alloc_dma_chan(spi_host_device_t host_id,spi_dma_chan_t dma_chan,uint32_t * out_actual_tx_dma_chan,uint32_t * out_actual_rx_dma_chan)230 static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan)
231 {
232 assert(is_valid_host(host_id));
233 assert(dma_chan == SPI_DMA_CH_AUTO);
234
235 esp_err_t ret = ESP_OK;
236 spicommon_bus_context_t *ctx = bus_ctx[host_id];
237
238 if (dma_chan == SPI_DMA_CH_AUTO) {
239 gdma_channel_alloc_config_t tx_alloc_config = {
240 .flags.reserve_sibling = 1,
241 .direction = GDMA_CHANNEL_DIRECTION_TX,
242 };
243 ret = gdma_new_channel(&tx_alloc_config, &ctx->tx_channel);
244 if (ret != ESP_OK) {
245 return ret;
246 }
247
248 gdma_channel_alloc_config_t rx_alloc_config = {
249 .direction = GDMA_CHANNEL_DIRECTION_RX,
250 .sibling_chan = ctx->tx_channel,
251 };
252 ret = gdma_new_channel(&rx_alloc_config, &ctx->rx_channel);
253 if (ret != ESP_OK) {
254 return ret;
255 }
256
257 if (host_id == SPI2_HOST) {
258 gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2));
259 gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2));
260 }
261 #if (SOC_SPI_PERIPH_NUM >= 3)
262 else if (host_id == SPI3_HOST) {
263 gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3));
264 gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3));
265 }
266 #endif
267 gdma_get_channel_id(ctx->tx_channel, (int *)out_actual_tx_dma_chan);
268 gdma_get_channel_id(ctx->rx_channel, (int *)out_actual_rx_dma_chan);
269 }
270
271 return ret;
272 }
273 #endif //#if !SOC_GDMA_SUPPORTED
274
spicommon_dma_chan_alloc(spi_host_device_t host_id,spi_dma_chan_t dma_chan,uint32_t * out_actual_tx_dma_chan,uint32_t * out_actual_rx_dma_chan)275 esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan)
276 {
277 assert(is_valid_host(host_id));
278 #if CONFIG_IDF_TARGET_ESP32
279 assert(dma_chan > SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO);
280 #elif CONFIG_IDF_TARGET_ESP32S2
281 assert(dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO);
282 #endif
283
284 esp_err_t ret = ESP_OK;
285 uint32_t actual_tx_dma_chan = 0;
286 uint32_t actual_rx_dma_chan = 0;
287 spicommon_bus_context_t *ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t));
288 if (!ctx) {
289 ret = ESP_ERR_NO_MEM;
290 goto cleanup;
291 }
292 bus_ctx[host_id] = ctx;
293 ctx->host_id = host_id;
294
295 ret = alloc_dma_chan(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan);
296 if (ret != ESP_OK) {
297 goto cleanup;
298 }
299 ctx->bus_attr.tx_dma_chan = actual_tx_dma_chan;
300 ctx->bus_attr.rx_dma_chan = actual_rx_dma_chan;
301 *out_actual_tx_dma_chan = actual_tx_dma_chan;
302 *out_actual_rx_dma_chan = actual_rx_dma_chan;
303
304 return ret;
305
306 cleanup:
307 free(ctx);
308 ctx = NULL;
309 return ret;
310 }
311
312 //----------------------------------------------------------free dma periph-------------------------------------------------------//
dma_chan_free(spi_host_device_t host_id)313 static esp_err_t dma_chan_free(spi_host_device_t host_id)
314 {
315 assert(is_valid_host(host_id));
316
317 spicommon_bus_context_t *ctx = bus_ctx[host_id];
318 #if !SOC_GDMA_SUPPORTED
319 //On ESP32S2, each SPI controller has its own DMA channel
320 int dma_chan = ctx->bus_attr.tx_dma_chan;
321 assert(spi_dma_chan_enabled & BIT(dma_chan));
322
323 portENTER_CRITICAL(&spi_dma_spinlock);
324 spi_dma_chan_enabled &= ~BIT(dma_chan);
325 periph_module_disable(get_dma_periph(dma_chan));
326 portEXIT_CRITICAL(&spi_dma_spinlock);
327
328 #else //SOC_GDMA_SUPPORTED
329 if (ctx->rx_channel) {
330 gdma_disconnect(ctx->rx_channel);
331 gdma_del_channel(ctx->rx_channel);
332 }
333 if (ctx->tx_channel) {
334 gdma_disconnect(ctx->tx_channel);
335 gdma_del_channel(ctx->tx_channel);
336 }
337 #endif
338
339 return ESP_OK;
340 }
341
spicommon_dma_chan_free(spi_host_device_t host_id)342 esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id)
343 {
344 assert(is_valid_host(host_id));
345
346 esp_err_t ret = dma_chan_free(host_id);
347 free(bus_ctx[host_id]);
348 bus_ctx[host_id] = NULL;
349
350 return ret;
351 }
352
353 //----------------------------------------------------------IO general-------------------------------------------------------//
354 #if SOC_SPI_SUPPORT_OCT
check_iomux_pins_oct(spi_host_device_t host,const spi_bus_config_t * bus_config)355 static bool check_iomux_pins_oct(spi_host_device_t host, const spi_bus_config_t* bus_config)
356 {
357 if (host != SPI2_HOST) {
358 return false;
359 }
360 int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num,
361 bus_config->sclk_io_num, bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num};
362 int io_mux_nums[] = {SPI2_IOMUX_PIN_NUM_MOSI_OCT, SPI2_IOMUX_PIN_NUM_MISO_OCT, SPI2_IOMUX_PIN_NUM_WP_OCT, SPI2_IOMUX_PIN_NUM_HD_OCT,
363 SPI2_IOMUX_PIN_NUM_CLK_OCT, SPI2_IOMUX_PIN_NUM_IO4_OCT, SPI2_IOMUX_PIN_NUM_IO5_OCT, SPI2_IOMUX_PIN_NUM_IO6_OCT, SPI2_IOMUX_PIN_NUM_IO7_OCT};
364 for (size_t i = 0; i < sizeof(io_nums)/sizeof(io_nums[0]); i++) {
365 if (io_nums[i] >= 0 && io_nums[i] != io_mux_nums[i]) {
366 return false;
367 }
368 }
369 return true;
370 }
371 #endif
372
check_iomux_pins_quad(spi_host_device_t host,const spi_bus_config_t * bus_config)373 static bool check_iomux_pins_quad(spi_host_device_t host, const spi_bus_config_t* bus_config)
374 {
375 if (bus_config->sclk_io_num>=0 &&
376 bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) {
377 return false;
378 }
379 if (bus_config->quadwp_io_num>=0 &&
380 bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) {
381 return false;
382 }
383 if (bus_config->quadhd_io_num>=0 &&
384 bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) {
385 return false;
386 }
387 if (bus_config->mosi_io_num >= 0 &&
388 bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) {
389 return false;
390 }
391 if (bus_config->miso_io_num>=0 &&
392 bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) {
393 return false;
394 }
395 return true;
396 }
397
bus_uses_iomux_pins(spi_host_device_t host,const spi_bus_config_t * bus_config)398 static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t* bus_config)
399 {
400 //Check if SPI pins could be routed to iomux.
401 #if SOC_SPI_SUPPORT_OCT
402 //The io mux pins available for Octal mode is not the same as the ones we use for non-Octal mode.
403 if ((bus_config->flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL) {
404 return check_iomux_pins_oct(host, bus_config);
405 }
406 #endif
407 return check_iomux_pins_quad(host, bus_config);
408 }
409
410 #if SOC_SPI_SUPPORT_OCT
bus_iomux_pins_set_oct(spi_host_device_t host,const spi_bus_config_t * bus_config)411 static void bus_iomux_pins_set_oct(spi_host_device_t host, const spi_bus_config_t* bus_config)
412 {
413 assert(host == SPI2_HOST);
414 int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num,
415 bus_config->sclk_io_num, bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num};
416 int io_signals[] = {spi_periph_signal[host].spid_in, spi_periph_signal[host].spiq_in, spi_periph_signal[host].spiwp_in,
417 spi_periph_signal[host].spihd_in,spi_periph_signal[host].spiclk_in, spi_periph_signal[host].spid4_out,
418 spi_periph_signal[host].spid5_out, spi_periph_signal[host].spid6_out, spi_periph_signal[host].spid7_out};
419 for (size_t i = 0; i < sizeof(io_nums)/sizeof(io_nums[0]); i++) {
420 if (io_nums[i] > 0) {
421 gpio_iomux_in(io_nums[i], io_signals[i]);
422 // In Octal mode use function channel 2
423 gpio_iomux_out(io_nums[i], SPI2_FUNC_NUM_OCT, false);
424 }
425 }
426 }
427 #endif //SOC_SPI_SUPPORT_OCT
428
bus_iomux_pins_set_quad(spi_host_device_t host,const spi_bus_config_t * bus_config)429 static void bus_iomux_pins_set_quad(spi_host_device_t host, const spi_bus_config_t* bus_config)
430 {
431 if (bus_config->mosi_io_num >= 0) {
432 gpio_iomux_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in);
433 gpio_iomux_out(bus_config->mosi_io_num, spi_periph_signal[host].func, false);
434 }
435 if (bus_config->miso_io_num >= 0) {
436 gpio_iomux_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in);
437 gpio_iomux_out(bus_config->miso_io_num, spi_periph_signal[host].func, false);
438 }
439 if (bus_config->quadwp_io_num >= 0) {
440 gpio_iomux_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in);
441 gpio_iomux_out(bus_config->quadwp_io_num, spi_periph_signal[host].func, false);
442 }
443 if (bus_config->quadhd_io_num >= 0) {
444 gpio_iomux_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in);
445 gpio_iomux_out(bus_config->quadhd_io_num, spi_periph_signal[host].func, false);
446 }
447 if (bus_config->sclk_io_num >= 0) {
448 gpio_iomux_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in);
449 gpio_iomux_out(bus_config->sclk_io_num, spi_periph_signal[host].func, false);
450 }
451 }
452
bus_iomux_pins_set(spi_host_device_t host,const spi_bus_config_t * bus_config)453 static void bus_iomux_pins_set(spi_host_device_t host, const spi_bus_config_t* bus_config)
454 {
455 #if SOC_SPI_SUPPORT_OCT
456 if ((bus_config->flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL) {
457 bus_iomux_pins_set_oct(host, bus_config);
458 return;
459 }
460 #endif
461 bus_iomux_pins_set_quad(host, bus_config);
462 }
463
464 /*
465 Do the common stuff to hook up a SPI host to a bus defined by a bunch of GPIO pins. Feed it a host number and a
466 bus config struct and it'll set up the GPIO matrix and enable the device. If a pin is set to non-negative value,
467 it should be able to be initialized.
468 */
spicommon_bus_initialize_io(spi_host_device_t host,const spi_bus_config_t * bus_config,uint32_t flags,uint32_t * flags_o)469 esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, uint32_t flags, uint32_t* flags_o)
470 {
471 #if SOC_SPI_SUPPORT_OCT
472 // In the driver of previous version, spi data4 ~ spi data7 are not in spi_bus_config_t struct. So the new-added pins come as 0
473 // if they are not really set. Add this boolean variable to check if the user has set spi data4 ~spi data7 pins .
474 bool io4_7_is_blank = !bus_config->data4_io_num && !bus_config->data5_io_num && !bus_config->data6_io_num && !bus_config->data7_io_num;
475 // This boolean variable specifies if user sets pins used for octal mode (users can set spi data4 ~ spi data7 to -1).
476 bool io4_7_enabled = !io4_7_is_blank && bus_config->data4_io_num >= 0 && bus_config->data5_io_num >= 0 &&
477 bus_config->data6_io_num >= 0 && bus_config->data7_io_num >= 0;
478 SPI_CHECK((flags & SPICOMMON_BUSFLAG_MASTER) || !((flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL), "Octal SPI mode / OPI mode only works when SPI is used as Master", ESP_ERR_INVALID_ARG);
479 SPI_CHECK(host == SPI2_HOST || !((flags & SPICOMMON_BUSFLAG_OCTAL) == SPICOMMON_BUSFLAG_OCTAL), "Only SPI2 supports Octal SPI mode / OPI mode", ESP_ERR_INVALID_ARG);
480 #endif //SOC_SPI_SUPPORT_OCT
481
482 uint32_t temp_flag = 0;
483
484 bool miso_need_output;
485 bool mosi_need_output;
486 bool sclk_need_output;
487 if ((flags&SPICOMMON_BUSFLAG_MASTER) != 0) {
488 //initial for master
489 miso_need_output = ((flags&SPICOMMON_BUSFLAG_DUAL) != 0) ? true : false;
490 mosi_need_output = true;
491 sclk_need_output = true;
492 } else {
493 //initial for slave
494 miso_need_output = true;
495 mosi_need_output = ((flags&SPICOMMON_BUSFLAG_DUAL) != 0) ? true : false;
496 sclk_need_output = false;
497 }
498
499 const bool wp_need_output = true;
500 const bool hd_need_output = true;
501
502 //check pin capabilities
503 if (bus_config->sclk_io_num>=0) {
504 temp_flag |= SPICOMMON_BUSFLAG_SCLK;
505 SPI_CHECK_PIN(bus_config->sclk_io_num, "sclk", sclk_need_output);
506 }
507 if (bus_config->quadwp_io_num>=0) {
508 SPI_CHECK_PIN(bus_config->quadwp_io_num, "wp", wp_need_output);
509 }
510 if (bus_config->quadhd_io_num>=0) {
511 SPI_CHECK_PIN(bus_config->quadhd_io_num, "hd", hd_need_output);
512 }
513 #if SOC_SPI_SUPPORT_OCT
514 const bool io4_need_output = true;
515 const bool io5_need_output = true;
516 const bool io6_need_output = true;
517 const bool io7_need_output = true;
518 // set flags for OCTAL mode according to the existence of spi data4 ~ spi data7
519 if (io4_7_enabled) {
520 temp_flag |= SPICOMMON_BUSFLAG_IO4_IO7;
521 if (bus_config->data4_io_num >= 0) {
522 SPI_CHECK_PIN(bus_config->data4_io_num, "spi data4", io4_need_output);
523 }
524 if (bus_config->data5_io_num >= 0) {
525 SPI_CHECK_PIN(bus_config->data5_io_num, "spi data5", io5_need_output);
526 }
527 if (bus_config->data6_io_num >= 0) {
528 SPI_CHECK_PIN(bus_config->data6_io_num, "spi data6", io6_need_output);
529 }
530 if (bus_config->data7_io_num >= 0) {
531 SPI_CHECK_PIN(bus_config->data7_io_num, "spi data7", io7_need_output);
532 }
533 }
534 #endif //SOC_SPI_SUPPORT_OCT
535
536 //set flags for QUAD mode according to the existence of wp and hd
537 if (bus_config->quadhd_io_num >= 0 && bus_config->quadwp_io_num >= 0) temp_flag |= SPICOMMON_BUSFLAG_WPHD;
538 if (bus_config->mosi_io_num >= 0) {
539 temp_flag |= SPICOMMON_BUSFLAG_MOSI;
540 SPI_CHECK_PIN(bus_config->mosi_io_num, "mosi", mosi_need_output);
541 }
542 if (bus_config->miso_io_num >= 0) {
543 temp_flag |= SPICOMMON_BUSFLAG_MISO;
544 SPI_CHECK_PIN(bus_config->miso_io_num, "miso", miso_need_output);
545 }
546 //set flags for DUAL mode according to output-capability of MOSI and MISO pins.
547 if ( (bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) &&
548 (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num)) ) {
549 temp_flag |= SPICOMMON_BUSFLAG_DUAL;
550 }
551
552 //check if the selected pins correspond to the iomux pins of the peripheral
553 bool use_iomux = !(flags & SPICOMMON_BUSFLAG_GPIO_PINS) && bus_uses_iomux_pins(host, bus_config);
554 if (use_iomux) {
555 temp_flag |= SPICOMMON_BUSFLAG_IOMUX_PINS;
556 } else {
557 temp_flag |= SPICOMMON_BUSFLAG_GPIO_PINS;
558 }
559
560 uint32_t missing_flag = flags & ~temp_flag;
561 missing_flag &= ~SPICOMMON_BUSFLAG_MASTER;//don't check this flag
562
563 if (missing_flag != 0) {
564 //check pins existence
565 if (missing_flag & SPICOMMON_BUSFLAG_SCLK) {
566 ESP_LOGE(SPI_TAG, "sclk pin required.");
567 }
568 if (missing_flag & SPICOMMON_BUSFLAG_MOSI) {
569 ESP_LOGE(SPI_TAG, "mosi pin required.");
570 }
571 if (missing_flag & SPICOMMON_BUSFLAG_MISO) {
572 ESP_LOGE(SPI_TAG, "miso pin required.");
573 }
574 if (missing_flag & SPICOMMON_BUSFLAG_DUAL) {
575 ESP_LOGE(SPI_TAG, "not both mosi and miso output capable");
576 }
577 if (missing_flag & SPICOMMON_BUSFLAG_WPHD) {
578 ESP_LOGE(SPI_TAG, "both wp and hd required.");
579 }
580 if (missing_flag & SPICOMMON_BUSFLAG_IOMUX_PINS) {
581 ESP_LOGE(SPI_TAG, "not using iomux pins");
582 }
583 #if SOC_SPI_SUPPORT_OCT
584 if (missing_flag & SPICOMMON_BUSFLAG_IO4_IO7) {
585 ESP_LOGE(SPI_TAG, "spi data4 ~ spi data7 are required.");
586 }
587 #endif
588 SPI_CHECK(missing_flag == 0, "not all required capabilities satisfied.", ESP_ERR_INVALID_ARG);
589 }
590
591 if (use_iomux) {
592 //All SPI iomux pin selections resolve to 1, so we put that here instead of trying to figure
593 //out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway.
594 ESP_LOGD(SPI_TAG, "SPI%d use iomux pins.", host+1);
595 bus_iomux_pins_set(host, bus_config);
596 } else {
597 //Use GPIO matrix
598 ESP_LOGD(SPI_TAG, "SPI%d use gpio matrix.", host+1);
599 if (bus_config->mosi_io_num >= 0) {
600 if (mosi_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) {
601 gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT_OUTPUT);
602 esp_rom_gpio_connect_out_signal(bus_config->mosi_io_num, spi_periph_signal[host].spid_out, false, false);
603 } else {
604 gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT);
605 }
606 esp_rom_gpio_connect_in_signal(bus_config->mosi_io_num, spi_periph_signal[host].spid_in, false);
607 #if CONFIG_IDF_TARGET_ESP32S2
608 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]);
609 #endif
610 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO);
611 }
612 if (bus_config->miso_io_num >= 0) {
613 if (miso_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) {
614 gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT_OUTPUT);
615 esp_rom_gpio_connect_out_signal(bus_config->miso_io_num, spi_periph_signal[host].spiq_out, false, false);
616 } else {
617 gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT);
618 }
619 esp_rom_gpio_connect_in_signal(bus_config->miso_io_num, spi_periph_signal[host].spiq_in, false);
620 #if CONFIG_IDF_TARGET_ESP32S2
621 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]);
622 #endif
623 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO);
624 }
625 if (bus_config->quadwp_io_num >= 0) {
626 gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT);
627 esp_rom_gpio_connect_out_signal(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_out, false, false);
628 esp_rom_gpio_connect_in_signal(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in, false);
629 #if CONFIG_IDF_TARGET_ESP32S2
630 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]);
631 #endif
632 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO);
633 }
634 if (bus_config->quadhd_io_num >= 0) {
635 gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT);
636 esp_rom_gpio_connect_out_signal(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_out, false, false);
637 esp_rom_gpio_connect_in_signal(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in, false);
638 #if CONFIG_IDF_TARGET_ESP32S2
639 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]);
640 #endif
641 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO);
642 }
643 if (bus_config->sclk_io_num >= 0) {
644 if (sclk_need_output) {
645 gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT_OUTPUT);
646 esp_rom_gpio_connect_out_signal(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_out, false, false);
647 } else {
648 gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT);
649 }
650 esp_rom_gpio_connect_in_signal(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in, false);
651 #if CONFIG_IDF_TARGET_ESP32S2
652 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]);
653 #endif
654 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO);
655 }
656 #if SOC_SPI_SUPPORT_OCT
657 if (flags & SPICOMMON_BUSFLAG_OCTAL) {
658 int io_nums[] = {bus_config->data4_io_num, bus_config->data5_io_num, bus_config->data6_io_num, bus_config->data7_io_num};
659 uint8_t io_signals[4][2] = {{spi_periph_signal[host].spid4_out, spi_periph_signal[host].spid4_in},
660 {spi_periph_signal[host].spid5_out, spi_periph_signal[host].spid5_in},
661 {spi_periph_signal[host].spid6_out, spi_periph_signal[host].spid6_in},
662 {spi_periph_signal[host].spid7_out, spi_periph_signal[host].spid7_in}};
663 for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) {
664 if (io_nums[i] >= 0) {
665 gpio_set_direction(io_nums[i], GPIO_MODE_INPUT_OUTPUT);
666 esp_rom_gpio_connect_out_signal(io_nums[i], io_signals[i][0], false, false);
667 esp_rom_gpio_connect_in_signal(io_nums[i], io_signals[i][1], false);
668 #if CONFIG_IDF_TARGET_ESP32S2
669 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_nums[i]]);
670 #endif
671 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_nums[i]], FUNC_GPIO);
672 }
673 }
674 }
675 #endif //SOC_SPI_SUPPORT_OCT
676 }
677
678 if (flags_o) *flags_o = temp_flag;
679 return ESP_OK;
680 }
681
spicommon_bus_free_io_cfg(const spi_bus_config_t * bus_cfg)682 esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg)
683 {
684 int pin_array[] = {
685 bus_cfg->mosi_io_num,
686 bus_cfg->miso_io_num,
687 bus_cfg->sclk_io_num,
688 bus_cfg->quadwp_io_num,
689 bus_cfg->quadhd_io_num,
690 };
691 for (int i = 0; i < sizeof(pin_array)/sizeof(int); i ++) {
692 const int io = pin_array[i];
693 if (io >= 0 && GPIO_IS_VALID_GPIO(io)) gpio_reset_pin(io);
694 }
695 return ESP_OK;
696 }
697
spicommon_cs_initialize(spi_host_device_t host,int cs_io_num,int cs_num,int force_gpio_matrix)698 void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix)
699 {
700 if (!force_gpio_matrix && cs_io_num == spi_periph_signal[host].spics0_iomux_pin && cs_num == 0) {
701 //The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
702 gpio_iomux_in(cs_io_num, spi_periph_signal[host].spics_in);
703 gpio_iomux_out(cs_io_num, spi_periph_signal[host].func, false);
704 } else {
705 //Use GPIO matrix
706 if (GPIO_IS_VALID_OUTPUT_GPIO(cs_io_num)) {
707 gpio_set_direction(cs_io_num, GPIO_MODE_INPUT_OUTPUT);
708 esp_rom_gpio_connect_out_signal(cs_io_num, spi_periph_signal[host].spics_out[cs_num], false, false);
709 } else {
710 gpio_set_direction(cs_io_num, GPIO_MODE_INPUT);
711 }
712 if (cs_num == 0) esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false);
713 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]);
714 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO);
715 }
716 }
717
spicommon_cs_free_io(int cs_gpio_num)718 void spicommon_cs_free_io(int cs_gpio_num)
719 {
720 assert(cs_gpio_num>=0 && GPIO_IS_VALID_GPIO(cs_gpio_num));
721 gpio_reset_pin(cs_gpio_num);
722 }
723
spicommon_bus_using_iomux(spi_host_device_t host)724 bool spicommon_bus_using_iomux(spi_host_device_t host)
725 {
726 #define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false
727
728 CHECK_IOMUX_PIN(host, spid);
729 CHECK_IOMUX_PIN(host, spiq);
730 CHECK_IOMUX_PIN(host, spiwp);
731 CHECK_IOMUX_PIN(host, spihd);
732 return true;
733 }
734
735
spi_bus_main_set_lock(spi_bus_lock_handle_t lock)736 void spi_bus_main_set_lock(spi_bus_lock_handle_t lock)
737 {
738 bus_ctx[0]->bus_attr.lock = lock;
739 }
740
spi_bus_lock_get_by_id(spi_host_device_t host_id)741 spi_bus_lock_handle_t spi_bus_lock_get_by_id(spi_host_device_t host_id)
742 {
743 return bus_ctx[host_id]->bus_attr.lock;
744 }
745
746 //----------------------------------------------------------master bus init-------------------------------------------------------//
spi_bus_initialize(spi_host_device_t host_id,const spi_bus_config_t * bus_config,spi_dma_chan_t dma_chan)747 esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, spi_dma_chan_t dma_chan)
748 {
749 esp_err_t err = ESP_OK;
750 spicommon_bus_context_t *ctx = NULL;
751 spi_bus_attr_t *bus_attr = NULL;
752 uint32_t actual_tx_dma_chan = 0;
753 uint32_t actual_rx_dma_chan = 0;
754
755 SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG);
756 SPI_CHECK(bus_ctx[host_id] == NULL, "SPI bus already initialized.", ESP_ERR_INVALID_STATE);
757 #ifdef CONFIG_IDF_TARGET_ESP32
758 SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG );
759 #elif CONFIG_IDF_TARGET_ESP32S2
760 SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG );
761 #elif SOC_GDMA_SUPPORTED
762 SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG );
763 #endif
764 SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
765 #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM
766 SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM)==0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_MASTER_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
767 #endif
768
769 bool spi_chan_claimed = spicommon_periph_claim(host_id, "spi master");
770 SPI_CHECK(spi_chan_claimed, "host_id already in use", ESP_ERR_INVALID_STATE);
771
772 //clean and initialize the context
773 ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t));
774 if (!ctx) {
775 err = ESP_ERR_NO_MEM;
776 goto cleanup;
777 }
778 bus_ctx[host_id] = ctx;
779 ctx->host_id = host_id;
780 bus_attr = &ctx->bus_attr;
781 bus_attr->bus_cfg = *bus_config;
782
783 if (dma_chan != SPI_DMA_DISABLED) {
784 bus_attr->dma_enabled = 1;
785
786 err = alloc_dma_chan(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan);
787 if (err != ESP_OK) {
788 goto cleanup;
789 }
790 bus_attr->tx_dma_chan = actual_tx_dma_chan;
791 bus_attr->rx_dma_chan = actual_rx_dma_chan;
792
793 int dma_desc_ct = lldesc_get_required_num(bus_config->max_transfer_sz);
794 if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given
795
796 bus_attr->max_transfer_sz = dma_desc_ct * LLDESC_MAX_NUM_PER_DESC;
797 bus_attr->dmadesc_tx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
798 bus_attr->dmadesc_rx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
799 if (bus_attr->dmadesc_tx == NULL || bus_attr->dmadesc_rx == NULL) {
800 err = ESP_ERR_NO_MEM;
801 goto cleanup;
802 }
803 bus_attr->dma_desc_num = dma_desc_ct;
804 } else {
805 bus_attr->dma_enabled = 0;
806 bus_attr->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE;
807 bus_attr->dma_desc_num = 0;
808 }
809
810 spi_bus_lock_config_t lock_config = {
811 .host_id = host_id,
812 .cs_num = SOC_SPI_PERIPH_CS_NUM(host_id),
813 };
814 err = spi_bus_init_lock(&bus_attr->lock, &lock_config);
815 if (err != ESP_OK) {
816 goto cleanup;
817 }
818
819 #ifdef CONFIG_PM_ENABLE
820 err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_master",
821 &bus_attr->pm_lock);
822 if (err != ESP_OK) {
823 goto cleanup;
824 }
825 #endif //CONFIG_PM_ENABLE
826
827 err = spicommon_bus_initialize_io(host_id, bus_config, SPICOMMON_BUSFLAG_MASTER | bus_config->flags, &bus_attr->flags);
828 if (err != ESP_OK) {
829 goto cleanup;
830 }
831
832 return ESP_OK;
833
834 cleanup:
835 if (bus_attr) {
836 #ifdef CONFIG_PM_ENABLE
837 esp_pm_lock_delete(bus_attr->pm_lock);
838 #endif
839 if (bus_attr->lock) {
840 spi_bus_deinit_lock(bus_attr->lock);
841 }
842 free(bus_attr->dmadesc_tx);
843 free(bus_attr->dmadesc_rx);
844 bus_attr->dmadesc_tx = NULL;
845 bus_attr->dmadesc_rx = NULL;
846 if (bus_attr->dma_enabled) {
847 dma_chan_free(host_id);
848 }
849 }
850 spicommon_periph_free(host_id);
851 free(bus_ctx[host_id]);
852 bus_ctx[host_id] = NULL;
853 return err;
854 }
855
spi_bus_get_attr(spi_host_device_t host_id)856 const spi_bus_attr_t* spi_bus_get_attr(spi_host_device_t host_id)
857 {
858 if (bus_ctx[host_id] == NULL) return NULL;
859
860 return &bus_ctx[host_id]->bus_attr;
861 }
862
spi_bus_free(spi_host_device_t host_id)863 esp_err_t spi_bus_free(spi_host_device_t host_id)
864 {
865 esp_err_t err = ESP_OK;
866 spicommon_bus_context_t* ctx = bus_ctx[host_id];
867 spi_bus_attr_t* bus_attr = &ctx->bus_attr;
868
869 if (ctx->destroy_func) {
870 err = ctx->destroy_func(ctx->destroy_arg);
871 }
872
873 spicommon_bus_free_io_cfg(&bus_attr->bus_cfg);
874
875 #ifdef CONFIG_PM_ENABLE
876 esp_pm_lock_delete(bus_attr->pm_lock);
877 #endif
878 spi_bus_deinit_lock(bus_attr->lock);
879 free(bus_attr->dmadesc_rx);
880 free(bus_attr->dmadesc_tx);
881 bus_attr->dmadesc_tx = NULL;
882 bus_attr->dmadesc_rx = NULL;
883 if (bus_attr->dma_enabled > 0) {
884 dma_chan_free(host_id);
885 }
886 spicommon_periph_free(host_id);
887 free(ctx);
888 bus_ctx[host_id] = NULL;
889 return err;
890 }
891
spi_bus_register_destroy_func(spi_host_device_t host_id,spi_destroy_func_t f,void * arg)892 esp_err_t spi_bus_register_destroy_func(spi_host_device_t host_id,
893 spi_destroy_func_t f, void *arg)
894 {
895 bus_ctx[host_id]->destroy_func = f;
896 bus_ctx[host_id]->destroy_arg = arg;
897 return ESP_OK;
898 }
899
900
901 /*
902 Code for workaround for DMA issue in ESP32 v0/v1 silicon
903 */
904 #if CONFIG_IDF_TARGET_ESP32
905 static volatile int dmaworkaround_channels_busy[2] = {0, 0};
906 static dmaworkaround_cb_t dmaworkaround_cb;
907 static void *dmaworkaround_cb_arg;
908 static portMUX_TYPE dmaworkaround_mux = portMUX_INITIALIZER_UNLOCKED;
909 static int dmaworkaround_waiting_for_chan = 0;
910 #endif
911
spicommon_dmaworkaround_req_reset(int dmachan,dmaworkaround_cb_t cb,void * arg)912 bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg)
913 {
914 #if CONFIG_IDF_TARGET_ESP32
915 int otherchan = (dmachan == 1) ? 2 : 1;
916 bool ret;
917 portENTER_CRITICAL_ISR(&dmaworkaround_mux);
918 if (dmaworkaround_channels_busy[otherchan-1]) {
919 //Other channel is busy. Call back when it's done.
920 dmaworkaround_cb = cb;
921 dmaworkaround_cb_arg = arg;
922 dmaworkaround_waiting_for_chan = otherchan;
923 ret = false;
924 } else {
925 //Reset DMA
926 periph_module_reset( PERIPH_SPI_DMA_MODULE );
927 ret = true;
928 }
929 portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
930 return ret;
931 #else
932 //no need to reset
933 return true;
934 #endif
935 }
936
spicommon_dmaworkaround_reset_in_progress(void)937 bool IRAM_ATTR spicommon_dmaworkaround_reset_in_progress(void)
938 {
939 #if CONFIG_IDF_TARGET_ESP32
940 return (dmaworkaround_waiting_for_chan != 0);
941 #else
942 return false;
943 #endif
944 }
945
spicommon_dmaworkaround_idle(int dmachan)946 void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
947 {
948 #if CONFIG_IDF_TARGET_ESP32
949 portENTER_CRITICAL_ISR(&dmaworkaround_mux);
950 dmaworkaround_channels_busy[dmachan-1] = 0;
951 if (dmaworkaround_waiting_for_chan == dmachan) {
952 //Reset DMA
953 periph_module_reset( PERIPH_SPI_DMA_MODULE );
954 dmaworkaround_waiting_for_chan = 0;
955 //Call callback
956 dmaworkaround_cb(dmaworkaround_cb_arg);
957
958 }
959 portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
960 #endif
961 }
962
spicommon_dmaworkaround_transfer_active(int dmachan)963 void IRAM_ATTR spicommon_dmaworkaround_transfer_active(int dmachan)
964 {
965 #if CONFIG_IDF_TARGET_ESP32
966 portENTER_CRITICAL_ISR(&dmaworkaround_mux);
967 dmaworkaround_channels_busy[dmachan-1] = 1;
968 portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
969 #endif
970 }
971
