1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #include <stdint.h> 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /******************Basic PHY Registers*******************/ 23 24 /** 25 * @brief BMCR(Basic Mode Control Register) 26 * 27 */ 28 typedef union { 29 struct { 30 uint32_t reserved : 7; /*!< Reserved */ 31 uint32_t collision_test : 1; /*!< Collision test */ 32 uint32_t duplex_mode : 1; /*!< Duplex mode:Full Duplex(1) and Half Duplex(0) */ 33 uint32_t restart_auto_nego : 1; /*!< Restart auto-negotiation */ 34 uint32_t isolate : 1; /*!< Isolate the PHY from MII except the SMI interface */ 35 uint32_t power_down : 1; /*!< Power off PHY except SMI interface */ 36 uint32_t en_auto_nego : 1; /*!< Enable auto negotiation */ 37 uint32_t speed_select : 1; /*!< Select speed: 100Mbps(1) and 10Mbps(0) */ 38 uint32_t en_loopback : 1; /*!< Enables transmit data to be routed to the receive path */ 39 uint32_t reset : 1; /*!< Reset PHY registers. This bit is self-clearing. */ 40 }; 41 uint32_t val; 42 } bmcr_reg_t; 43 #define ETH_PHY_BMCR_REG_ADDR (0x00) 44 45 /** 46 * @brief BMSR(Basic Mode Status Register) 47 * 48 */ 49 typedef union { 50 struct { 51 uint32_t ext_capability : 1; /*!< Extended register capability */ 52 uint32_t jabber_detect : 1; /*!< Jabber condition detected */ 53 uint32_t link_status : 1; /*!< Link status */ 54 uint32_t auto_nego_ability : 1; /*!< Auto negotiation ability */ 55 uint32_t remote_fault : 1; /*!< Remote fault detected */ 56 uint32_t auto_nego_complete : 1; /*!< Auto negotiation completed */ 57 uint32_t mf_preamble_suppress : 1; /*!< Preamble suppression capability for management frame */ 58 uint32_t reserved : 1; /*!< Reserved */ 59 uint32_t ext_status : 1; /*!< Extended Status */ 60 uint32_t base100_t2_hdx : 1; /*!< 100Base-T2 Half Duplex capability */ 61 uint32_t base100_t2_fdx : 1; /*!< 100Base-T2 Full Duplex capability */ 62 uint32_t base10_t_hdx : 1; /*!< 10Base-T Half Duplex capability */ 63 uint32_t base10_t_fdx : 1; /*!< 10Base-T Full Duplex capability */ 64 uint32_t base100_tx_hdx : 1; /*!< 100Base-Tx Half Duplex capability */ 65 uint32_t base100_tx_fdx : 1; /*!< 100Base-Tx Full Duplex capability */ 66 uint32_t based100_t4 : 1; /*!< 100Base-T4 capability */ 67 }; 68 uint32_t val; 69 } bmsr_reg_t; 70 #define ETH_PHY_BMSR_REG_ADDR (0x01) 71 72 /** 73 * @brief PHYIDR1(PHY Identifier Register 1) 74 * 75 */ 76 typedef union { 77 struct { 78 uint32_t oui_msb : 16; /*!< Organizationally Unique Identifier(OUI) most significant bits */ 79 }; 80 uint32_t val; 81 } phyidr1_reg_t; 82 #define ETH_PHY_IDR1_REG_ADDR (0x02) 83 84 /** 85 * @brief PHYIDR2(PHY Identifier Register 2) 86 * 87 */ 88 typedef union { 89 struct { 90 uint32_t model_revision : 4; /*!< Model revision number */ 91 uint32_t vendor_model : 6; /*!< Vendor model number */ 92 uint32_t oui_lsb : 6; /*!< Organizationally Unique Identifier(OUI) least significant bits */ 93 }; 94 uint32_t val; 95 } phyidr2_reg_t; 96 #define ETH_PHY_IDR2_REG_ADDR (0x03) 97 98 /** 99 * @brief ANAR(Auto-Negotiation Advertisement Register) 100 * 101 */ 102 typedef union { 103 struct { 104 uint32_t protocol_select : 5; /*!< Binary encoded selector supported by this PHY */ 105 uint32_t base10_t : 1; /*!< 10Base-T support */ 106 uint32_t base10_t_fd : 1; /*!< 10Base-T full duplex support */ 107 uint32_t base100_tx : 1; /*!< 100Base-TX support */ 108 uint32_t base100_tx_fd : 1; /*!< 100Base-TX full duplex support */ 109 uint32_t base100_t4 : 1; /*!< 100Base-T4 support */ 110 uint32_t symmetric_pause : 1; /*!< Symmetric pause support for full duplex links */ 111 uint32_t asymmetric_pause : 1; /*!< Asymmetric pause support for full duplex links */ 112 uint32_t reserved1 : 1; /*!< Reserved */ 113 uint32_t remote_fault : 1; /*!< Advertise remote fault detection capability */ 114 uint32_t acknowledge : 1; /*!< Link partner ability data reception acknowledged */ 115 uint32_t next_page : 1; /*!< Next page indication, if set, next page transfer is desired */ 116 }; 117 uint32_t val; 118 } anar_reg_t; 119 #define ETH_PHY_ANAR_REG_ADDR (0x04) 120 121 /** 122 * @brief ANLPAR(Auto-Negotiation Link Partner Ability Register) 123 * 124 */ 125 typedef union { 126 struct { 127 uint32_t protocol_select : 5; /*!< Link Partner’s binary encoded node selector */ 128 uint32_t base10_t : 1; /*!< 10Base-T support */ 129 uint32_t base10_t_fd : 1; /*!< 10Base-T full duplex support */ 130 uint32_t base100_tx : 1; /*!< 100Base-TX support */ 131 uint32_t base100_tx_fd : 1; /*!< 100Base-TX full duplex support */ 132 uint32_t base100_t4 : 1; /*!< 100Base-T4 support */ 133 uint32_t symmetric_pause : 1; /*!< Symmetric pause supported by Link Partner */ 134 uint32_t asymmetric_pause : 1; /*!< Asymmetric pause supported by Link Partner */ 135 uint32_t reserved : 1; /*!< Reserved */ 136 uint32_t remote_fault : 1; /*!< Link partner is indicating a remote fault */ 137 uint32_t acknowledge : 1; /*!< Acknowledges from link partner */ 138 uint32_t next_page : 1; /*!< Next page indication */ 139 }; 140 uint32_t val; 141 } anlpar_reg_t; 142 #define ETH_PHY_ANLPAR_REG_ADDR (0x05) 143 144 /** 145 * @brief ANER(Auto-Negotiate Expansion Register) 146 * 147 */ 148 typedef union { 149 struct { 150 uint32_t link_partner_auto_nego_able : 1; /*!< Link partner auto-negotiation ability */ 151 uint32_t link_page_received : 1; /*!< Link code word page has received */ 152 uint32_t next_page_able : 1; /*!< Next page ablility */ 153 uint32_t link_partner_next_page_able : 1; /*!< Link partner next page ability */ 154 uint32_t parallel_detection_fault : 1; /*!< Parallel detection fault */ 155 uint32_t reserved : 11; /*!< Reserved */ 156 }; 157 uint32_t val; 158 } aner_reg_t; 159 #define ETH_PHY_ANER_REG_ADDR (0x06) 160 161 #ifdef __cplusplus 162 } 163 #endif 164
