1 /*
2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stddef.h>
9 #include <stdint.h>
10 #include <string.h>
11
12 #include <platform_def.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <common/bl_common.h>
17 #include <common/debug.h>
18 #include <common/runtime_svc.h>
19 #include <context.h>
20 #include <drivers/console.h>
21 #include <lib/el3_runtime/context_mgmt.h>
22 #include <lib/pmf/pmf.h>
23 #include <lib/psci/psci.h>
24 #include <lib/runtime_instr.h>
25 #include <lib/utils.h>
26 #include <plat/common/platform.h>
27 #include <platform_sp_min.h>
28 #include <services/std_svc.h>
29 #include <smccc_helpers.h>
30
31 #include "sp_min_private.h"
32
33 #if ENABLE_RUNTIME_INSTRUMENTATION
PMF_REGISTER_SERVICE_SMC(rt_instr_svc,PMF_RT_INSTR_SVC_ID,RT_INSTR_TOTAL_IDS,PMF_STORE_ENABLE)34 PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
35 RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
36 #endif
37
38 /* Pointers to per-core cpu contexts */
39 static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
40
41 /* SP_MIN only stores the non secure smc context */
42 static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
43
44 /******************************************************************************
45 * Define the smccc helper library APIs
46 *****************************************************************************/
47 void *smc_get_ctx(unsigned int security_state)
48 {
49 assert(security_state == NON_SECURE);
50 return &sp_min_smc_context[plat_my_core_pos()];
51 }
52
smc_set_next_ctx(unsigned int security_state)53 void smc_set_next_ctx(unsigned int security_state)
54 {
55 assert(security_state == NON_SECURE);
56 /* SP_MIN stores only non secure smc context. Nothing to do here */
57 }
58
smc_get_next_ctx(void)59 void *smc_get_next_ctx(void)
60 {
61 return &sp_min_smc_context[plat_my_core_pos()];
62 }
63
64 /*******************************************************************************
65 * This function returns a pointer to the most recent 'cpu_context' structure
66 * for the calling CPU that was set as the context for the specified security
67 * state. NULL is returned if no such structure has been specified.
68 ******************************************************************************/
cm_get_context(uint32_t security_state)69 void *cm_get_context(uint32_t security_state)
70 {
71 assert(security_state == NON_SECURE);
72 return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
73 }
74
75 /*******************************************************************************
76 * This function sets the pointer to the current 'cpu_context' structure for the
77 * specified security state for the calling CPU
78 ******************************************************************************/
cm_set_context(void * context,uint32_t security_state)79 void cm_set_context(void *context, uint32_t security_state)
80 {
81 assert(security_state == NON_SECURE);
82 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context;
83 }
84
85 /*******************************************************************************
86 * This function returns a pointer to the most recent 'cpu_context' structure
87 * for the CPU identified by `cpu_idx` that was set as the context for the
88 * specified security state. NULL is returned if no such structure has been
89 * specified.
90 ******************************************************************************/
cm_get_context_by_index(unsigned int cpu_idx,unsigned int security_state)91 void *cm_get_context_by_index(unsigned int cpu_idx,
92 unsigned int security_state)
93 {
94 assert(security_state == NON_SECURE);
95 return sp_min_cpu_ctx_ptr[cpu_idx];
96 }
97
98 /*******************************************************************************
99 * This function sets the pointer to the current 'cpu_context' structure for the
100 * specified security state for the CPU identified by CPU index.
101 ******************************************************************************/
cm_set_context_by_index(unsigned int cpu_idx,void * context,unsigned int security_state)102 void cm_set_context_by_index(unsigned int cpu_idx, void *context,
103 unsigned int security_state)
104 {
105 assert(security_state == NON_SECURE);
106 sp_min_cpu_ctx_ptr[cpu_idx] = context;
107 }
108
copy_cpu_ctx_to_smc_stx(const regs_t * cpu_reg_ctx,smc_ctx_t * next_smc_ctx)109 static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx,
110 smc_ctx_t *next_smc_ctx)
111 {
112 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
113 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
114 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
115 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
116 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
117 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
118 }
119
120 /*******************************************************************************
121 * This function invokes the PSCI library interface to initialize the
122 * non secure cpu context and copies the relevant cpu context register values
123 * to smc context. These registers will get programmed during `smc_exit`.
124 ******************************************************************************/
sp_min_prepare_next_image_entry(void)125 static void sp_min_prepare_next_image_entry(void)
126 {
127 entry_point_info_t *next_image_info;
128 cpu_context_t *ctx = cm_get_context(NON_SECURE);
129 u_register_t ns_sctlr;
130
131 /* Program system registers to proceed to non-secure */
132 next_image_info = sp_min_plat_get_bl33_ep_info();
133 assert(next_image_info);
134 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
135
136 INFO("SP_MIN: Preparing exit to normal world\n");
137 print_entry_point_info(next_image_info);
138
139 psci_prepare_next_non_secure_ctx(next_image_info);
140 smc_set_next_ctx(NON_SECURE);
141
142 /* Copy r0, lr and spsr from cpu context to SMC context */
143 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
144 smc_get_next_ctx());
145
146 /* Temporarily set the NS bit to access NS SCTLR */
147 write_scr(read_scr() | SCR_NS_BIT);
148 isb();
149 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
150 write_sctlr(ns_sctlr);
151 isb();
152
153 write_scr(read_scr() & ~SCR_NS_BIT);
154 isb();
155 }
156
157 /******************************************************************************
158 * Implement the ARM Standard Service function to get arguments for a
159 * particular service.
160 *****************************************************************************/
get_arm_std_svc_args(unsigned int svc_mask)161 uintptr_t get_arm_std_svc_args(unsigned int svc_mask)
162 {
163 /* Setup the arguments for PSCI Library */
164 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint);
165
166 /* PSCI is the only ARM Standard Service implemented */
167 assert(svc_mask == PSCI_FID_MASK);
168
169 return (uintptr_t)&psci_args;
170 }
171
172 /******************************************************************************
173 * The SP_MIN main function. Do the platform and PSCI Library setup. Also
174 * initialize the runtime service framework.
175 *****************************************************************************/
sp_min_main(void)176 void sp_min_main(void)
177 {
178 NOTICE("SP_MIN: %s\n", version_string);
179 NOTICE("SP_MIN: %s\n", build_message);
180
181 /* Perform the SP_MIN platform setup */
182 sp_min_platform_setup();
183
184 /* Initialize the runtime services e.g. psci */
185 INFO("SP_MIN: Initializing runtime services\n");
186 runtime_svc_init();
187
188 /*
189 * We are ready to enter the next EL. Prepare entry into the image
190 * corresponding to the desired security state after the next ERET.
191 */
192 sp_min_prepare_next_image_entry();
193
194 /*
195 * Perform any platform specific runtime setup prior to cold boot exit
196 * from SP_MIN.
197 */
198 sp_min_plat_runtime_setup();
199
200 console_flush();
201 }
202
203 /******************************************************************************
204 * This function is invoked during warm boot. Invoke the PSCI library
205 * warm boot entry point which takes care of Architectural and platform setup/
206 * restore. Copy the relevant cpu_context register values to smc context which
207 * will get programmed during `smc_exit`.
208 *****************************************************************************/
sp_min_warm_boot(void)209 void sp_min_warm_boot(void)
210 {
211 smc_ctx_t *next_smc_ctx;
212 cpu_context_t *ctx = cm_get_context(NON_SECURE);
213 u_register_t ns_sctlr;
214
215 psci_warmboot_entrypoint();
216
217 smc_set_next_ctx(NON_SECURE);
218
219 next_smc_ctx = smc_get_next_ctx();
220 zeromem(next_smc_ctx, sizeof(smc_ctx_t));
221
222 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
223 next_smc_ctx);
224
225 /* Temporarily set the NS bit to access NS SCTLR */
226 write_scr(read_scr() | SCR_NS_BIT);
227 isb();
228 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
229 write_sctlr(ns_sctlr);
230 isb();
231
232 write_scr(read_scr() & ~SCR_NS_BIT);
233 isb();
234 }
235
236 #if SP_MIN_WITH_SECURE_FIQ
237 /******************************************************************************
238 * This function is invoked on secure interrupts. By construction of the
239 * SP_MIN, secure interrupts can only be handled when core executes in non
240 * secure state.
241 *****************************************************************************/
sp_min_fiq(void)242 void sp_min_fiq(void)
243 {
244 uint32_t id;
245
246 id = plat_ic_acknowledge_interrupt();
247 sp_min_plat_fiq_handler(id);
248 plat_ic_end_of_interrupt(id);
249 }
250 #endif /* SP_MIN_WITH_SECURE_FIQ */
251
