1/* 2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/clock/kinetis_pcc.h> 10#include <zephyr/dt-bindings/clock/kinetis_scg.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13 14/ { 15 aliases { 16 watchdog0 = &wdog; 17 }; 18 19 chosen { 20 zephyr,flash-controller = &ftfe; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-m4f"; 30 reg = <0>; 31 cpu-power-states = <&idle &stop &pstop1 &pstop2>; 32 }; 33 34 power-states { 35 idle: idle { 36 compatible = "zephyr,power-state"; 37 power-state-name = "runtime-idle"; 38 }; 39 40 stop: stop { 41 compatible = "zephyr,power-state"; 42 power-state-name = "suspend-to-idle"; 43 substate-id = <0>; 44 }; 45 46 pstop1: pstop1 { 47 compatible = "zephyr,power-state"; 48 power-state-name = "suspend-to-idle"; 49 substate-id = <1>; 50 }; 51 52 pstop2: pstop2 { 53 compatible = "zephyr,power-state"; 54 power-state-name = "suspend-to-idle"; 55 substate-id = <2>; 56 }; 57 }; 58 }; 59 60 temp0: temp0 { 61 compatible = "nxp,kinetis-temperature"; 62 io-channels = <&adc0 26>, <&adc0 27>; 63 io-channel-names = "SENSOR", "BANDGAP"; 64 bandgap-voltage = <1000000>; 65 vtemp25 = <740500>; 66 sensor-slope-cold = <1564>; 67 sensor-slope-hot = <1564>; 68 status = "disabled"; 69 }; 70 71 temp1: temp1 { 72 compatible = "nxp,kinetis-temperature"; 73 io-channels = <&adc1 26>, <&adc1 27>; 74 io-channel-names = "SENSOR", "BANDGAP"; 75 bandgap-voltage = <1000000>; 76 vtemp25 = <740500>; 77 sensor-slope-cold = <1564>; 78 sensor-slope-hot = <1564>; 79 status = "disabled"; 80 }; 81 82 temp2: temp2 { 83 compatible = "nxp,kinetis-temperature"; 84 io-channels = <&adc2 26>, <&adc2 27>; 85 io-channel-names = "SENSOR", "BANDGAP"; 86 bandgap-voltage = <1000000>; 87 vtemp25 = <740500>; 88 sensor-slope-cold = <1564>; 89 sensor-slope-hot = <1564>; 90 status = "disabled"; 91 }; 92 93 /* Dummy pinctrl node, filled with pin mux options at board level */ 94 pinctrl: pinctrl { 95 compatible = "nxp,port-pinctrl"; 96 status = "okay"; 97 }; 98 99 soc { 100 edma: dma-controller@40008000 { 101 compatible = "nxp,mcux-edma"; 102 nxp,version = <2>; 103 dma-channels = <16>; 104 dma-requests = <64>; 105 nxp,mem2mem; 106 reg = <0x40008000 0x1000>, <0x40021000 0x1000>; 107 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 108 <4 0>, <5 0>, <6 0>, <7 0>, 109 <8 0>, <9 0>, <10 0>, <11 0>, 110 <12 0>, <13 0>, <14 0>, <15 0>, 111 <16 0>; 112 status = "disabled"; 113 #dma-cells = <2>; 114 }; 115 116 mpu: mpu@4000d000 { 117 compatible = "nxp,sysmpu"; 118 reg = <0x4000d000 0x1000>; 119 status = "disabled"; 120 }; 121 122 sim: sim@40048000 { 123 compatible = "nxp,kinetis-ke1xf-sim"; 124 reg = <0x40048000 0x1000>; 125 }; 126 127 scg: scg@40064000 { 128 compatible = "nxp,kinetis-scg"; 129 reg = <0x40064000 0x1000>; 130 #clock-cells = <1>; 131 132 sosc_clk: sosc_clk { 133 compatible = "fixed-clock"; 134 status = "disabled"; 135 #clock-cells = <0>; 136 }; 137 138 sirc_clk: sirc_clk { 139 compatible = "fixed-clock"; 140 clock-frequency = <8000000>; 141 #clock-cells = <0>; 142 }; 143 144 firc_clk: firc_clk { 145 compatible = "fixed-clock"; 146 clock-frequency = <48000000>; 147 #clock-cells = <0>; 148 }; 149 150 pll: pll { 151 compatible = "fixed-factor-clock"; 152 clocks = <&sosc_clk>; 153 clock-div = <1>; 154 clock-mult = <16>; 155 #clock-cells = <0>; 156 }; 157 158 spll_clk: spll_clk { 159 compatible = "fixed-factor-clock"; 160 clocks = <&pll>; 161 clock-div = <2>; 162 #clock-cells = <0>; 163 }; 164 165 core_clk: core_clk { 166 compatible = "fixed-factor-clock"; 167 clocks = <&firc_clk>; 168 clock-div = <1>; 169 #clock-cells = <0>; 170 }; 171 172 bus_clk: bus_clk { 173 compatible = "fixed-factor-clock"; 174 clocks = <&core_clk>; 175 clock-div = <1>; 176 #clock-cells = <0>; 177 }; 178 179 slow_clk: slow_clk { 180 compatible = "fixed-factor-clock"; 181 clocks = <&core_clk>; 182 clock-div = <2>; 183 #clock-cells = <0>; 184 }; 185 186 clkout_clk: clkout_clk { 187 compatible = "fixed-factor-clock"; 188 status = "disabled"; 189 clocks = <&firc_clk>; 190 #clock-cells = <0>; 191 }; 192 193 splldiv1_clk: splldiv1_clk { 194 compatible = "fixed-factor-clock"; 195 clocks = <&spll_clk>; 196 clock-div = <0>; 197 #clock-cells = <0>; 198 }; 199 200 splldiv2_clk: splldiv2_clk { 201 compatible = "fixed-factor-clock"; 202 clocks = <&spll_clk>; 203 clock-div = <0>; 204 #clock-cells = <0>; 205 }; 206 207 sircdiv1_clk: sircdiv1_clk { 208 compatible = "fixed-factor-clock"; 209 clocks = <&sirc_clk>; 210 clock-div = <0>; 211 #clock-cells = <0>; 212 }; 213 214 sircdiv2_clk: sircdiv2_clk { 215 compatible = "fixed-factor-clock"; 216 clocks = <&sirc_clk>; 217 clock-div = <0>; 218 #clock-cells = <0>; 219 }; 220 221 fircdiv1_clk: fircdiv1_clk { 222 compatible = "fixed-factor-clock"; 223 clocks = <&firc_clk>; 224 clock-div = <0>; 225 #clock-cells = <0>; 226 }; 227 228 fircdiv2_clk: fircdiv2_clk { 229 compatible = "fixed-factor-clock"; 230 clocks = <&firc_clk>; 231 clock-div = <0>; 232 #clock-cells = <0>; 233 }; 234 235 soscdiv1_clk: soscdiv1_clk { 236 compatible = "fixed-factor-clock"; 237 clocks = <&sosc_clk>; 238 clock-div = <0>; 239 #clock-cells = <0>; 240 }; 241 242 soscdiv2_clk: soscdiv2_clk { 243 compatible = "fixed-factor-clock"; 244 clocks = <&sosc_clk>; 245 clock-div = <0>; 246 #clock-cells = <0>; 247 }; 248 }; 249 250 pmc: pmc@4007d000 { 251 reg = <0x4007d000 0x1000>; 252 253 lpo: lpo128k { 254 /* LPO clock */ 255 compatible = "fixed-clock"; 256 clock-frequency = <128000>; 257 #clock-cells = <0>; 258 }; 259 }; 260 261 pcc: pcc@40065000 { 262 compatible = "nxp,kinetis-pcc"; 263 reg = <0x40065000 0x1000>; 264 #clock-cells = <2>; 265 }; 266 267 rtc: rtc@4003d000 { 268 compatible = "nxp,rtc"; 269 reg = <0x4003d000 0x1000>; 270 interrupts = <46 0>, <47 0>; 271 interrupt-names = "alarm", "seconds"; 272 clock-frequency = <32768>; 273 prescaler = <32768>; 274 }; 275 276 dac0: dac@4003f000 { 277 compatible = "nxp,kinetis-dac32"; 278 reg = <0x4003f000 0x1000>; 279 interrupts = <56 0>; 280 clocks = <&scg KINETIS_SCG_BUS_CLK>; 281 voltage-reference = <1>; 282 buffered; 283 status = "disabled"; 284 #io-channel-cells = <1>; 285 }; 286 287 lptmr0: lptmr@40040000 { 288 compatible = "nxp,lptmr"; 289 reg = <0x40040000 0x1000>; 290 interrupts = <58 0>; 291 clock-frequency = <128000>; 292 prescaler = <1>; 293 clk-source = <1>; 294 resolution = <16>; 295 }; 296 297 wdog: watchdog@40052000 { 298 compatible = "nxp,wdog32"; 299 reg = <0x40052000 0x1000>; 300 interrupts = <22 0>; 301 clocks = <&lpo>; 302 clk-source = <1>; 303 clk-divider = <256>; 304 }; 305 306 pwt: pwt@40056000 { 307 compatible = "nxp,kinetis-pwt"; 308 reg = <0x40056000 0x1000>; 309 interrupts = <29 0>; 310 clocks = <&scg KINETIS_SCG_BUS_CLK>; 311 prescaler = <1>; 312 status = "disabled"; 313 314 #pwm-cells = <3>; 315 }; 316 317 ftfe: flash-controller@40020000 { 318 compatible = "nxp,kinetis-ftfe"; 319 reg = <0x40020000 0x1000>; 320 interrupts = <18 0>, <19 0>; 321 interrupt-names = "command-complete", "read-collision"; 322 323 #address-cells = <1>; 324 #size-cells = <1>; 325 }; 326 327 lpuart0: uart@4006a000 { 328 compatible = "nxp,lpuart"; 329 reg = <0x4006a000 0x1000>; 330 interrupts = <31 0>, <32 0>; 331 interrupt-names = "transmit", "receive"; 332 clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>; 333 dmas = <&edma 1 2>, <&edma 2 3>; 334 dma-names = "rx", "tx"; 335 status = "disabled"; 336 }; 337 338 lpuart1: uart@4006b000 { 339 compatible = "nxp,lpuart"; 340 reg = <0x4006b000 0x1000>; 341 interrupts = <33 0>, <34 0>; 342 interrupt-names = "transmit", "receive"; 343 clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>; 344 dmas = <&edma 3 4>, <&edma 4 5>; 345 dma-names = "rx", "tx"; 346 status = "disabled"; 347 }; 348 349 lpuart2: uart@4006c000 { 350 compatible = "nxp,lpuart"; 351 reg = <0x4006c000 0x1000>; 352 interrupts = <35 0>, <36 0>; 353 interrupt-names = "transmit", "receive"; 354 clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>; 355 dmas = <&edma 5 6>, <&edma 5 7>; 356 dma-names = "rx", "tx"; 357 status = "disabled"; 358 }; 359 360 lpi2c0: i2c@40066000 { 361 compatible = "nxp,lpi2c"; 362 clock-frequency = <I2C_BITRATE_STANDARD>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <0x40066000 0x1000>; 366 interrupts = <24 0>; 367 clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>; 368 status = "disabled"; 369 }; 370 371 lpi2c1: i2c@40067000 { 372 compatible = "nxp,lpi2c"; 373 clock-frequency = <I2C_BITRATE_STANDARD>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x40067000 0x1000>; 377 interrupts = <25 0>; 378 clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>; 379 status = "disabled"; 380 }; 381 382 lpspi0: spi@4002c000 { 383 compatible = "nxp,lpspi"; 384 reg = <0x4002c000 0x1000>; 385 interrupts = <26 0>; 386 clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>; 387 status = "disabled"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 }; 391 392 lpspi1: spi@4002d000 { 393 compatible = "nxp,lpspi"; 394 reg = <0x4002d000 0x1000>; 395 interrupts = <27 0>; 396 clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>; 397 status = "disabled"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 }; 401 402 flexcan0: can@40024000 { 403 compatible = "nxp,flexcan"; 404 reg = <0x40024000 0x1000>; 405 interrupts = <78 0>, <79 0>, <80 0>, <81 0>; 406 interrupt-names = "warning", "error", "wake-up", 407 "mb-0-15"; 408 clocks = <&scg KINETIS_SCG_BUS_CLK>; 409 clk-source = <1>; 410 status = "disabled"; 411 }; 412 413 flexcan1: can@40025000 { 414 compatible = "nxp,flexcan"; 415 reg = <0x40025000 0x1000>; 416 interrupts = <85 0>, <86 0>, <87 0>, <88 0>; 417 interrupt-names = "warning", "error", "wake-up", 418 "mb-0-15"; 419 clocks = <&scg KINETIS_SCG_BUS_CLK>; 420 clk-source = <1>; 421 status = "disabled"; 422 }; 423 424 porta: pinmux@40049000 { 425 compatible = "nxp,port-pinmux"; 426 reg = <0x40049000 0x1000>; 427 clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>; 428 }; 429 430 portb: pinmux@4004a000 { 431 compatible = "nxp,port-pinmux"; 432 reg = <0x4004a000 0x1000>; 433 clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>; 434 }; 435 436 portc: pinmux@4004b000 { 437 compatible = "nxp,port-pinmux"; 438 reg = <0x4004b000 0x1000>; 439 clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>; 440 }; 441 442 portd: pinmux@4004c000 { 443 compatible = "nxp,port-pinmux"; 444 reg = <0x4004c000 0x1000>; 445 clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>; 446 }; 447 448 porte: pinmux@4004d000 { 449 compatible = "nxp,port-pinmux"; 450 reg = <0x4004d000 0x1000>; 451 clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>; 452 }; 453 454 gpioa: gpio@400ff000 { 455 compatible = "nxp,kinetis-gpio"; 456 status = "disabled"; 457 reg = <0x400ff000 0x40>; 458 interrupts = <59 2>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 nxp,kinetis-port = <&porta>; 462 }; 463 464 gpiob: gpio@400ff040 { 465 compatible = "nxp,kinetis-gpio"; 466 status = "disabled"; 467 reg = <0x400ff040 0x40>; 468 interrupts = <60 2>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 nxp,kinetis-port = <&portb>; 472 }; 473 474 gpioc: gpio@400ff080 { 475 compatible = "nxp,kinetis-gpio"; 476 status = "disabled"; 477 reg = <0x400ff080 0x40>; 478 interrupts = <61 2>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 nxp,kinetis-port = <&portc>; 482 }; 483 484 gpiod: gpio@400ff0c0 { 485 compatible = "nxp,kinetis-gpio"; 486 status = "disabled"; 487 reg = <0x400ff0c0 0x40>; 488 interrupts = <62 2>; 489 gpio-controller; 490 #gpio-cells = <2>; 491 nxp,kinetis-port = <&portd>; 492 }; 493 494 gpioe: gpio@400ff100 { 495 compatible = "nxp,kinetis-gpio"; 496 status = "disabled"; 497 reg = <0x400ff100 0x40>; 498 interrupts = <63 2>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 nxp,kinetis-port = <&porte>; 502 }; 503 504 adc0: adc@4003b000 { 505 compatible = "nxp,adc12"; 506 reg = <0x4003b000 0x1000>; 507 interrupts = <39 0>; 508 clocks = <&pcc 0xec KINETIS_PCC_SRC_FIRC_ASYNC>; 509 clk-source = <0>; 510 clk-divider = <1>; 511 status = "disabled"; 512 #io-channel-cells = <1>; 513 }; 514 515 adc1: adc@40027000 { 516 compatible = "nxp,adc12"; 517 reg = <0x40027000 0x1000>; 518 interrupts = <73 0>; 519 clocks = <&pcc 0x9c KINETIS_PCC_SRC_FIRC_ASYNC>; 520 clk-source = <0>; 521 clk-divider = <1>; 522 status = "disabled"; 523 #io-channel-cells = <1>; 524 }; 525 526 adc2: adc@4003c000 { 527 compatible = "nxp,adc12"; 528 reg = <0x4003c000 0x1000>; 529 interrupts = <74 0>; 530 clocks = <&pcc 0xf0 KINETIS_PCC_SRC_FIRC_ASYNC>; 531 clk-source = <0>; 532 clk-divider = <1>; 533 status = "disabled"; 534 #io-channel-cells = <1>; 535 }; 536 537 ftm0: ftm@40038000 { 538 compatible = "nxp,ftm"; 539 reg = <0x40038000 0x1000>; 540 interrupts = <42 0>; 541 clocks = <&pcc 0xe0 KINETIS_PCC_SRC_FIRC_ASYNC>; 542 prescaler = <16>; 543 status = "disabled"; 544 }; 545 546 ftm1: ftm@40039000 { 547 compatible = "nxp,ftm"; 548 reg = <0x40039000 0x1000>; 549 interrupts = <43 0>; 550 clocks = <&pcc 0xe4 KINETIS_PCC_SRC_FIRC_ASYNC>; 551 prescaler = <16>; 552 status = "disabled"; 553 }; 554 555 ftm2: ftm@4003a000 { 556 compatible = "nxp,ftm"; 557 reg = <0x4003a000 0x1000>; 558 interrupts = <44 0>; 559 clocks = <&pcc 0xe8 KINETIS_PCC_SRC_FIRC_ASYNC>; 560 prescaler = <16>; 561 status = "disabled"; 562 }; 563 564 ftm3: ftm@40026000 { 565 compatible = "nxp,ftm"; 566 reg = <0x40026000 0x1000>; 567 interrupts = <71 0>; 568 clocks = <&pcc 0x98 KINETIS_PCC_SRC_FIRC_ASYNC>; 569 prescaler = <16>; 570 status = "disabled"; 571 }; 572 573 cmp0: cmp@40073000 { 574 compatible = "nxp,kinetis-acmp"; 575 reg = <0x40073000 0x1000>; 576 interrupts = <40 0>; 577 clocks = <&scg KINETIS_SCG_BUS_CLK>; 578 status = "disabled"; 579 }; 580 581 cmp1: cmp@40074000 { 582 compatible = "nxp,kinetis-acmp"; 583 reg = <0x40074000 0x1000>; 584 interrupts = <41 0>; 585 clocks = <&scg KINETIS_SCG_BUS_CLK>; 586 status = "disabled"; 587 }; 588 589 cmp2: cmp@40075000 { 590 compatible = "nxp,kinetis-acmp"; 591 reg = <0x40075000 0x1000>; 592 interrupts = <70 0>; 593 clocks = <&scg KINETIS_SCG_BUS_CLK>; 594 status = "disabled"; 595 }; 596 597 flexio1: flexio@4005a000 { 598 compatible = "nxp,flexio"; 599 reg = <0x4005a000 0x1000>; 600 status = "disabled"; 601 interrupts = <69 0>; 602 clocks = <&pcc 0x168 KINETIS_PCC_SRC_FIRC_ASYNC>; 603 }; 604 }; 605}; 606 607&nvic { 608 arm,num-irq-priority-bits = <4>; 609}; 610
