1 /*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <common/debug.h>
11 #include <common/tbbr/tbbr_img_def.h>
12 #include <drivers/cadence/cdns_nand.h>
13 #include <drivers/cadence/cdns_sdmmc.h>
14 #include <drivers/io/io_block.h>
15 #include <drivers/io/io_driver.h>
16 #include <drivers/io/io_fip.h>
17 #include <drivers/io/io_memmap.h>
18 #include <drivers/io/io_mtd.h>
19 #include <drivers/io/io_storage.h>
20 #include <drivers/mmc.h>
21 #include <drivers/partition/partition.h>
22 #include <lib/mmio.h>
23 #include <tools_share/firmware_image_package.h>
24
25 #include "drivers/sdmmc/sdmmc.h"
26 #include "socfpga_private.h"
27
28
29 #define PLAT_FIP_BASE (0)
30 #define PLAT_FIP_MAX_SIZE (0x1000000)
31 #define PLAT_MMC_DATA_BASE (0xffe3c000)
32 #define PLAT_MMC_DATA_SIZE (0x2000)
33 #define PLAT_QSPI_DATA_BASE (0x3C00000)
34 #define PLAT_QSPI_DATA_SIZE (0x1000000)
35 #define PLAT_NAND_DATA_BASE (0x0200000)
36 #define PLAT_NAND_DATA_SIZE (0x1000000)
37
38 static const io_dev_connector_t *fip_dev_con;
39 static const io_dev_connector_t *boot_dev_con;
40
41 static io_mtd_dev_spec_t nand_dev_spec;
42
43 static uintptr_t fip_dev_handle;
44 static uintptr_t boot_dev_handle;
45
46 static const io_uuid_spec_t bl2_uuid_spec = {
47 .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
48 };
49
50 static const io_uuid_spec_t bl31_uuid_spec = {
51 .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
52 };
53
54 static const io_uuid_spec_t bl33_uuid_spec = {
55 .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
56 };
57
58 uintptr_t a2_lba_offset;
59 const char a2[] = {0xa2, 0x0};
60
61 static const io_block_spec_t gpt_block_spec = {
62 .offset = 0,
63 .length = MMC_BLOCK_SIZE
64 };
65
66 static int check_fip(const uintptr_t spec);
67 static int check_dev(const uintptr_t spec);
68
69 static io_block_dev_spec_t boot_dev_spec;
70 static int (*register_io_dev)(const io_dev_connector_t **);
71
72 static io_block_spec_t fip_spec = {
73 .offset = PLAT_FIP_BASE,
74 .length = PLAT_FIP_MAX_SIZE,
75 };
76
77 struct plat_io_policy {
78 uintptr_t *dev_handle;
79 uintptr_t image_spec;
80 int (*check)(const uintptr_t spec);
81 };
82
83 static const struct plat_io_policy policies[] = {
84 [FIP_IMAGE_ID] = {
85 &boot_dev_handle,
86 (uintptr_t)&fip_spec,
87 check_dev
88 },
89 [BL2_IMAGE_ID] = {
90 &fip_dev_handle,
91 (uintptr_t)&bl2_uuid_spec,
92 check_fip
93 },
94 [BL31_IMAGE_ID] = {
95 &fip_dev_handle,
96 (uintptr_t)&bl31_uuid_spec,
97 check_fip
98 },
99 [BL33_IMAGE_ID] = {
100 &fip_dev_handle,
101 (uintptr_t) &bl33_uuid_spec,
102 check_fip
103 },
104 [GPT_IMAGE_ID] = {
105 &boot_dev_handle,
106 (uintptr_t) &gpt_block_spec,
107 check_dev
108 },
109 };
110
check_dev(const uintptr_t spec)111 static int check_dev(const uintptr_t spec)
112 {
113 int result;
114 uintptr_t local_handle;
115
116 result = io_dev_init(boot_dev_handle, (uintptr_t)NULL);
117 if (result == 0) {
118 result = io_open(boot_dev_handle, spec, &local_handle);
119 if (result == 0)
120 io_close(local_handle);
121 }
122 return result;
123 }
124
check_fip(const uintptr_t spec)125 static int check_fip(const uintptr_t spec)
126 {
127 int result;
128 uintptr_t local_image_handle;
129
130 result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
131 if (result == 0) {
132 result = io_open(fip_dev_handle, spec, &local_image_handle);
133 if (result == 0)
134 io_close(local_image_handle);
135 }
136 return result;
137 }
138
socfpga_io_setup(int boot_source)139 void socfpga_io_setup(int boot_source)
140 {
141 int result;
142
143 switch (boot_source) {
144 case BOOT_SOURCE_SDMMC:
145 register_io_dev = ®ister_io_dev_block;
146 boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE;
147 boot_dev_spec.buffer.length = SOCFPGA_MMC_BLOCK_SIZE;
148 boot_dev_spec.ops.read = SDMMC_READ_BLOCKS;
149 boot_dev_spec.ops.write = SDMMC_WRITE_BLOCKS;
150 boot_dev_spec.block_size = MMC_BLOCK_SIZE;
151 break;
152
153 case BOOT_SOURCE_QSPI:
154 register_io_dev = ®ister_io_dev_memmap;
155 fip_spec.offset = PLAT_QSPI_DATA_BASE;
156 break;
157
158 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
159 case BOOT_SOURCE_NAND:
160 register_io_dev = ®ister_io_dev_mtd;
161 nand_dev_spec.ops.init = cdns_nand_init_mtd;
162 nand_dev_spec.ops.read = cdns_nand_read;
163 nand_dev_spec.ops.write = NULL;
164 fip_spec.offset = PLAT_NAND_DATA_BASE;
165 break;
166 #endif
167
168 default:
169 ERROR("Unsupported boot source\n");
170 panic();
171 break;
172 }
173
174 result = (*register_io_dev)(&boot_dev_con);
175 assert(result == 0);
176
177 result = register_io_dev_fip(&fip_dev_con);
178 assert(result == 0);
179
180 if (boot_source == BOOT_SOURCE_NAND) {
181 result = io_dev_open(boot_dev_con, (uintptr_t)&nand_dev_spec,
182 &boot_dev_handle);
183 } else {
184 result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec,
185 &boot_dev_handle);
186 }
187 assert(result == 0);
188
189 result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
190 assert(result == 0);
191
192 if (boot_source == BOOT_SOURCE_SDMMC) {
193 partition_init(GPT_IMAGE_ID);
194 fip_spec.offset = get_partition_entry(a2)->start;
195 }
196
197 (void)result;
198 }
199
plat_get_image_source(unsigned int image_id,uintptr_t * dev_handle,uintptr_t * image_spec)200 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
201 uintptr_t *image_spec)
202 {
203 int result;
204 const struct plat_io_policy *policy;
205
206 assert(image_id < ARRAY_SIZE(policies));
207
208 policy = &policies[image_id];
209 result = policy->check(policy->image_spec);
210 assert(result == 0);
211
212 *image_spec = policy->image_spec;
213 *dev_handle = *(policy->dev_handle);
214
215 return result;
216 }
217
