1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _FSL_MISC_SOC_H_ 8 #define _FSL_MISC_SOC_H_ 9 #include "fsl_common.h" 10 /*! 11 * @addtogroup misc_soc 12 * @{ 13 */ 14 15 /******************************************************************************* 16 * Definitions 17 ******************************************************************************/ 18 /*! @name Driver version */ 19 /*@{*/ 20 /*! @brief Driver version 2.0.0. */ 21 #define FSL_MISC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 22 /*@}*/ 23 24 #ifndef BIT 25 #define BIT(x) (1U << x) 26 #endif 27 28 #define SOC_SRC_IPS_BASE_ADDR (0x44460000) 29 #define SOC_SRC_GLOBAL_RBASE (SOC_SRC_IPS_BASE_ADDR + 0x0000) 30 31 typedef enum 32 { 33 SOC_MIX_PD_MEDIAMIX, 34 SOC_MIX_PD_MLMIX, 35 SOC_MIX_PD_DDRMIX, 36 } soc_mix_power_domain_e; 37 38 typedef enum 39 { 40 SOC_SRC_MIX_EDGELOCK = 0, 41 SOC_SRC_MIX_AONMIX = 1, 42 SOC_SRC_MIX_WAKEUPMIX = 2, 43 SOC_SRC_MIX_DDRMIX = 3, 44 SOC_SRC_MIX_DDRPHY = 4, 45 SOC_SRC_MIX_ML = 5, 46 SOC_SRC_MIX_NIC = 6, 47 SOC_SRC_MIX_HSIO = 7, 48 SOC_SRC_MIX_MEDIA = 8, 49 SOC_SRC_MIX_CM33 = 9, 50 SOC_SRC_MIX_CA55C0 = 10, 51 SOC_SRC_MIX_CA55C1 = 11, 52 SOC_SRC_MIX_CA55CLUSTER = 12, 53 } soc_src_mix_slice_id_e; 54 55 typedef enum 56 { 57 SOC_SRC_MEM_AONMIX = 0, 58 SOC_SRC_MEM_WAKEUPMIX = 1, 59 SOC_SRC_MEM_DDRMIX = 2, 60 SOC_SRC_MEM_DDRPHY = 3, 61 SOC_SRC_MEM_ML = 4, 62 SOC_SRC_MEM_NIC = 5, 63 SOC_SRC_MEM_OCRAM = 6, 64 SOC_SRC_MEM_HSIO = 7, 65 SOC_SRC_MEM_MEDIA = 8, 66 SOC_SRC_MEM_CA55C0 = 9, 67 SOC_SRC_MEM_CA55C1 = 10, 68 SOC_SRC_MEM_CA55CLUSTER = 11, 69 SOC_SRC_MEM_L3 = 12, 70 } soc_src_mem_slice_id_e; 71 72 typedef struct 73 { 74 uint32_t reserved[1]; 75 uint32_t authen_ctrl; 76 uint32_t reserved1[2]; 77 uint32_t scr; 78 uint32_t srtmr; 79 uint32_t srmask; 80 uint32_t reserved2[1]; 81 uint32_t srmr[6]; 82 uint32_t reserved3[2]; 83 uint32_t sbmr[2]; 84 uint32_t reserved4[2]; 85 uint32_t srsr; 86 uint32_t gpr[19]; 87 uint32_t reserved5[24]; 88 uint32_t gpr20; 89 uint32_t cm_quiesce; 90 uint32_t cold_reset_ssar_ack_ctrl; 91 uint32_t sp_iso_ctrl; 92 uint32_t rom_lp_ctrl; 93 uint32_t a55_deny_stat; 94 } soc_src_general_regs_t; 95 96 typedef struct 97 { 98 uint32_t reserved[1]; 99 uint32_t mem_ctrl; 100 uint32_t memlp_ctrl_0; 101 uint32_t reserved1[1]; 102 uint32_t memlp_ctrl_1; 103 uint32_t memlp_ctrl_2; 104 uint32_t mem_stat; 105 } soc_src_mem_slice_regs_t; 106 #endif /* _FSL_CLOCK_H_ */ 107 108 /******************************************************************************* 109 * API 110 ******************************************************************************/ 111 #if defined(__cplusplus) 112 extern "C" { 113 #endif /* __cplusplus */ 114 int SOC_MixPowerInit(soc_mix_power_domain_e pwr_dom); 115 void SOC_DisableIsolation(void); 116 #if defined(__cplusplus) 117 } 118 #endif /* __cplusplus */ 119
