1 /* 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 /* 13 ************************* ESP32C6 Root Clock Source **************************** 14 * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description) 15 * 16 * This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK. 17 * 18 * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. 19 * 20 * 2) External 40MHz Crystal Clock: XTAL 21 * 22 * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) 23 * 24 * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock 25 * can be computed in runtime through calibration. 26 * 27 * 4) Internal 32kHz RC Oscillator: RC32K [NOT RECOMMENDED TO USE] 28 * 29 * The exact frequency of this clock can be computed in runtime through calibration. 30 * 31 * 5) External 32kHz Crystal Clock (optional): XTAL32K 32 * 33 * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N 34 * pins. 35 * 36 * XTAL32K_CLK can also be calibrated to get its exact frequency. 37 * 38 * 6) External Slow Clock (optional): OSC_SLOW 39 * 40 * A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the 41 * RTC_SLOW_CLK. 42 * 43 * OSC_SLOW_CLK can also be calibrated to get its exact frequency. 44 */ 45 46 /* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */ 47 #define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ 48 #define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ 49 #define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ 50 #define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ 51 #define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ 52 53 // Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] 54 // {loc}: EXT, INT 55 // {type}: XTAL, RC 56 // [attr] - optional: [frequency], FAST, SLOW 57 /** 58 * @brief Root clock 59 */ 60 typedef enum { 61 SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ 62 SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ 63 SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ 64 SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */ 65 SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */ 66 SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ 67 } soc_root_clk_t; 68 69 /** 70 * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK 71 * @note Enum values are matched with the register field values on purpose 72 */ 73 typedef enum { 74 SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ 75 SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ 76 SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ 77 SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ 78 } soc_cpu_clk_src_t; 79 80 /** 81 * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK 82 * @note Enum values are matched with the register field values on purpose 83 */ 84 typedef enum { 85 SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ 86 SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ 87 SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ 88 SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ 89 SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ 90 } soc_rtc_slow_clk_src_t; 91 92 /** 93 * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK 94 * @note Enum values are matched with the register field values on purpose 95 */ 96 typedef enum { 97 SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ 98 SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ 99 SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ 100 SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ 101 } soc_rtc_fast_clk_src_t; 102 103 // Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] 104 // {[upstream]clock_name}: XTAL, (BB)PLL, etc. 105 // [attr] - optional: FAST, SLOW, D<divider>, F<freq> 106 /** 107 * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) 108 * 109 * @note enum starts from 1, to save 0 for special purpose 110 */ 111 typedef enum { 112 // For CPU domain 113 SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ 114 // For RTC domain 115 SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ 116 SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ 117 // For digital domain: peripherals, WIFI, BLE 118 SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ 119 SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ 120 SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ 121 SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ 122 SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ 123 SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ 124 // For LP peripherals 125 SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */ 126 127 SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ 128 } soc_module_clk_t; 129 130 //////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// 131 132 /** 133 * @brief Type of SYSTIMER clock source 134 */ 135 typedef enum { 136 SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ 137 SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ 138 SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ 139 } soc_periph_systimer_clk_src_t; 140 141 //////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// 142 143 /** 144 * @brief Array initializer for all supported clock sources of GPTimer 145 * 146 * The following code can be used to iterate all possible clocks: 147 * @code{c} 148 * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; 149 * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { 150 * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; 151 * // Test GPTimer with the clock `clk` 152 * } 153 * @endcode 154 */ 155 #define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} 156 157 /** 158 * @brief Type of GPTimer clock source 159 */ 160 typedef enum { 161 GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ 162 GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 163 GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 164 GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ 165 } soc_periph_gptimer_clk_src_t; 166 167 /** 168 * @brief Type of Timer Group clock source, reserved for the legacy timer group driver 169 */ 170 typedef enum { 171 TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ 172 TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ 173 TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ 174 } soc_periph_tg_clk_src_legacy_t; 175 176 //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// 177 178 /** 179 * @brief Array initializer for all supported clock sources of RMT 180 */ 181 #define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} 182 183 /** 184 * @brief Type of RMT clock source 185 */ 186 typedef enum { 187 RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ 188 RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 189 RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 190 RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ 191 } soc_periph_rmt_clk_src_t; 192 193 /** 194 * @brief Type of RMT clock source, reserved for the legacy RMT driver 195 */ 196 typedef enum { 197 RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */ 198 RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ 199 RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */ 200 } soc_periph_rmt_clk_src_legacy_t; 201 202 //////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// 203 204 /** 205 * @brief Array initializer for all supported clock sources of Temperature Sensor 206 */ 207 #define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 208 209 /** 210 * @brief Type of Temp Sensor clock source 211 */ 212 typedef enum { 213 TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 214 TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 215 TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ 216 } soc_periph_temperature_sensor_clk_src_t; 217 218 ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// 219 220 /** 221 * @brief Type of UART clock source, reserved for the legacy UART driver 222 */ 223 typedef enum { 224 UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ 225 UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ 226 UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ 227 UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ 228 } soc_periph_uart_clk_src_legacy_t; 229 230 /** 231 * @brief Type of LP_UART clock source 232 */ 233 typedef enum { 234 LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */ 235 LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ 236 LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */ 237 } soc_periph_lp_uart_clk_src_t; 238 239 //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// 240 241 /** 242 * @brief Array initializer for all supported clock sources of MCPWM Timer 243 */ 244 #define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} 245 246 /** 247 * @brief Type of MCPWM timer clock source 248 */ 249 typedef enum { 250 MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 251 MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 252 MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ 253 } soc_periph_mcpwm_timer_clk_src_t; 254 255 /** 256 * @brief Array initializer for all supported clock sources of MCPWM Capture Timer 257 */ 258 #define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} 259 260 /** 261 * @brief Type of MCPWM capture clock source 262 */ 263 typedef enum { 264 MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 265 MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 266 MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ 267 } soc_periph_mcpwm_capture_clk_src_t; 268 269 /** 270 * @brief Array initializer for all supported clock sources of MCPWM Carrier 271 */ 272 #define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL} 273 274 /** 275 * @brief Type of MCPWM carrier clock source 276 */ 277 typedef enum { 278 MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 279 MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 280 MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */ 281 } soc_periph_mcpwm_carrier_clk_src_t; 282 283 ///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// 284 285 /** 286 * @brief Array initializer for all supported clock sources of I2S 287 */ 288 #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} 289 290 /** 291 * @brief I2S clock source enum 292 */ 293 typedef enum { 294 I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ 295 I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ 296 I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 297 I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ 298 } soc_periph_i2s_clk_src_t; 299 300 /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// 301 302 /** 303 * @brief Array initializer for all supported clock sources of I2C 304 */ 305 #define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 306 307 /** 308 * @brief Type of I2C clock source. 309 */ 310 typedef enum { 311 I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 312 I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 313 I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */ 314 } soc_periph_i2c_clk_src_t; 315 316 ///////////////////////////////////////////////LP_I2C/////////////////////////////////////////////////////////////////// 317 318 /** 319 * @brief Array initializer for all supported clock sources of LP_I2C 320 */ 321 #define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2} 322 323 /** 324 * @brief Type of LP_I2C clock source. 325 */ 326 typedef enum { 327 LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */ 328 LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */ 329 LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */ 330 } soc_periph_lp_i2c_clk_src_t; 331 332 /////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// 333 334 /** 335 * @brief Array initializer for all supported clock sources of SPI 336 */ 337 #define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} 338 339 /** 340 * @brief Type of SPI clock source. 341 */ 342 typedef enum { 343 SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ 344 SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */ 345 SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ 346 SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ 347 } soc_periph_spi_clk_src_t; 348 349 //////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// 350 351 /** 352 * @brief Array initializer for all supported clock sources of SDM 353 */ 354 #define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} 355 356 /** 357 * @brief Sigma Delta Modulator clock source 358 */ 359 typedef enum { 360 SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ 361 SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ 362 SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ 363 } soc_periph_sdm_clk_src_t; 364 365 //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// 366 367 /** 368 * @brief Array initializer for all supported clock sources of Glitch Filter 369 */ 370 #define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL} 371 372 /** 373 * @brief Glitch filter clock source 374 */ 375 376 typedef enum { 377 GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ 378 GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ 379 GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ 380 } soc_periph_glitch_filter_clk_src_t; 381 382 //////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// 383 384 /** 385 * @brief Array initializer for all supported clock sources of TWAI 386 */ 387 #define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} 388 389 /** 390 * @brief TWAI clock source 391 */ 392 typedef enum { 393 TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 394 TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ 395 } soc_periph_twai_clk_src_t; 396 397 //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// 398 399 /** 400 * @brief Array initializer for all supported clock sources of ADC digital controller 401 */ 402 #define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} 403 404 /** 405 * @brief ADC digital controller clock source 406 */ 407 typedef enum { 408 ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 409 ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ 410 ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 411 ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ 412 } soc_periph_adc_digi_clk_src_t; 413 414 //////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// 415 416 /** 417 * @brief Array initializer for all supported clock sources of MWDT 418 */ 419 #define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} 420 421 /** 422 * @brief MWDT clock source 423 */ 424 typedef enum { 425 MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 426 MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ 427 MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ 428 MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */ 429 } soc_periph_mwdt_clk_src_t; 430 431 //////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// 432 433 /** 434 * @brief Array initializer for all supported clock sources of LEDC 435 */ 436 #define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} 437 438 /** 439 * @brief Type of LEDC clock source, reserved for the legacy LEDC driver 440 */ 441 typedef enum { 442 LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ 443 LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ 444 LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ 445 LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 446 447 LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ 448 } soc_periph_ledc_clk_src_legacy_t; 449 450 //////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// 451 452 /** 453 * @brief Array initializer for all supported clock sources of PARLIO 454 */ 455 #define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M} 456 457 /** 458 * @brief PARLIO clock source 459 */ 460 typedef enum { 461 PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ 462 PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */ 463 PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ 464 } soc_periph_parlio_clk_src_t; 465 466 //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// 467 typedef enum { 468 CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ 469 CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ 470 CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */ 471 CLKOUT_SIG_CPU = 16, /*!< CPU clock */ 472 CLKOUT_SIG_AHB = 17, /*!< AHB clock */ 473 CLKOUT_SIG_APB = 18, /*!< APB clock */ 474 CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ 475 CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ 476 CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ 477 CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ 478 CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ 479 CLKOUT_SIG_INVALID = 0xFF, 480 } soc_clkout_sig_id_t; 481 482 #ifdef __cplusplus 483 } 484 #endif 485
