1 /*
2  * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stddef.h>
8 #include <string.h>
9 #include <sys/lock.h>
10 #include <sys/param.h>
11 
12 #include "esp_attr.h"
13 #include "esp_sleep.h"
14 #include "esp_log.h"
15 #include "freertos/FreeRTOS.h"
16 #include "freertos/task.h"
17 #include "esp_heap_caps.h"
18 #include "soc/soc_caps.h"
19 #include "hal/rtc_hal.h"
20 #include "esp_private/sleep_retention.h"
21 #include "sdkconfig.h"
22 
23 #ifdef CONFIG_IDF_TARGET_ESP32S3
24 #include "esp32s3/rom/cache.h"
25 #endif
26 
27 static __attribute__((unused)) const char *TAG = "sleep";
28 
29 /**
30  * Internal structure which holds all requested light sleep memory retention parameters
31  */
32 typedef struct {
33     rtc_cntl_sleep_retent_t retent;
34 } sleep_retention_t;
35 
36 static DRAM_ATTR sleep_retention_t s_retention;
37 
38 #if SOC_PM_SUPPORT_TAGMEM_PD
39 
40 #define TAGMEM_PD_MEM_TYPE_CAPS     (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT)
41 
42 #if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
cache_tagmem_retention_setup(uint32_t code_seg_vaddr,uint32_t code_seg_size,uint32_t data_seg_vaddr,uint32_t data_seg_size)43 static int cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t code_seg_size, uint32_t data_seg_vaddr, uint32_t data_seg_size)
44 {
45     int sets;   /* i/d-cache total set counts */
46     int index;  /* virtual address mapping i/d-cache row offset */
47     int waysgrp;
48     int icache_tagmem_blk_gs, dcache_tagmem_blk_gs;
49     struct cache_mode imode = { .icache = 1 };
50     struct cache_mode dmode = { .icache = 0 };
51 
52     /* calculate/prepare i-cache tag memory retention parameters */
53     Cache_Get_Mode(&imode);
54     sets = imode.cache_size / imode.cache_ways / imode.cache_line_size;
55     index = (code_seg_vaddr / imode.cache_line_size) % sets;
56     waysgrp = imode.cache_ways >> 2;
57 
58     code_seg_size = ALIGNUP(imode.cache_line_size, code_seg_size);
59 
60     s_retention.retent.tagmem.icache.start_point = index;
61     s_retention.retent.tagmem.icache.size = (sets * waysgrp) & 0xff;
62     s_retention.retent.tagmem.icache.vld_size = s_retention.retent.tagmem.icache.size;
63     if (code_seg_size < imode.cache_size / imode.cache_ways) {
64         s_retention.retent.tagmem.icache.vld_size = (code_seg_size / imode.cache_line_size) * waysgrp;
65     }
66     s_retention.retent.tagmem.icache.enable = (code_seg_size != 0) ? 1 : 0;
67     icache_tagmem_blk_gs = s_retention.retent.tagmem.icache.vld_size ? s_retention.retent.tagmem.icache.vld_size : sets * waysgrp;
68     icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs);
69     ESP_LOGD(TAG, "I-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (imode.cache_size>>10),
70             imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs);
71 
72     /* calculate/prepare d-cache tag memory retention parameters */
73     Cache_Get_Mode(&dmode);
74     sets = dmode.cache_size / dmode.cache_ways / dmode.cache_line_size;
75     index = (data_seg_vaddr / dmode.cache_line_size) % sets;
76     waysgrp = dmode.cache_ways >> 2;
77 
78     data_seg_size = ALIGNUP(dmode.cache_line_size, data_seg_size);
79 
80     s_retention.retent.tagmem.dcache.start_point = index;
81     s_retention.retent.tagmem.dcache.size = (sets * waysgrp) & 0x1ff;
82     s_retention.retent.tagmem.dcache.vld_size = s_retention.retent.tagmem.dcache.size;
83 #ifndef CONFIG_ESP32S3_DATA_CACHE_16KB
84     if (data_seg_size < dmode.cache_size / dmode.cache_ways) {
85         s_retention.retent.tagmem.dcache.vld_size = (data_seg_size / dmode.cache_line_size) * waysgrp;
86     }
87     s_retention.retent.tagmem.dcache.enable = (data_seg_size != 0) ? 1 : 0;
88 #else
89     s_retention.retent.tagmem.dcache.enable = 1;
90 #endif
91     dcache_tagmem_blk_gs = s_retention.retent.tagmem.dcache.vld_size ? s_retention.retent.tagmem.dcache.vld_size : sets * waysgrp;
92     dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs);
93     ESP_LOGD(TAG, "D-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (dmode.cache_size>>10),
94             dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs);
95 
96     /* For I or D cache tagmem retention, backup and restore are performed through
97      * RTC DMA (its bus width is 128 bits), For I/D Cache tagmem blocks (i-cache
98      * tagmem blocks = 92 bits, d-cache tagmem blocks = 88 bits), RTC DMA automatically
99      * aligns its bit width to 96 bits, therefore, 3 times RTC DMA can transfer 4
100      * i/d-cache tagmem blocks (128 bits * 3 = 96 bits * 4) */
101     return (((icache_tagmem_blk_gs + dcache_tagmem_blk_gs) << 2) * 3);
102 }
103 #endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
104 
esp_sleep_tagmem_pd_low_init(bool enable)105 static esp_err_t esp_sleep_tagmem_pd_low_init(bool enable)
106 {
107     if (enable) {
108 #if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
109         if (s_retention.retent.tagmem.link_addr == NULL) {
110             extern char _stext[], _etext[];
111             uint32_t code_start = (uint32_t)_stext;
112             uint32_t code_size = (uint32_t)(_etext - _stext);
113 #if !CONFIG_ESP32S3_SPIRAM_SUPPORT
114             extern char _rodata_start[], _rodata_reserved_end[];
115             uint32_t data_start = (uint32_t)_rodata_start;
116             uint32_t data_size = (uint32_t)(_rodata_reserved_end - _rodata_start);
117 #else
118             uint32_t data_start = SOC_DROM_LOW;
119             uint32_t data_size = (SOC_EXTRAM_DATA_HIGH-SOC_EXTRAM_DATA_LOW) + (SOC_DROM_HIGH-SOC_DROM_LOW);
120 #endif
121             ESP_LOGI(TAG, "Code start at %08x, total %.2f KiB, data start at %08x, total %.2f KiB",
122                     code_start, (float)code_size/1024, data_start, (float)data_size/1024);
123             int tagmem_sz = cache_tagmem_retention_setup(code_start, code_size, data_start, data_size);
124             void *buf = heap_caps_aligned_alloc(SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN,
125                                                 tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE,
126                                                 TAGMEM_PD_MEM_TYPE_CAPS);
127             if (buf) {
128                 memset(buf, 0, tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE);
129                 s_retention.retent.tagmem.link_addr = rtc_cntl_hal_dma_link_init(buf,
130                                       buf + RTC_HAL_DMA_LINK_NODE_SIZE, tagmem_sz, NULL);
131             } else {
132                 s_retention.retent.tagmem.icache.enable = 0;
133                 s_retention.retent.tagmem.dcache.enable = 0;
134                 s_retention.retent.tagmem.link_addr = NULL;
135                 return ESP_ERR_NO_MEM;
136             }
137         }
138 #else // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
139         s_retention.retent.tagmem.icache.enable = 0;
140         s_retention.retent.tagmem.dcache.enable = 0;
141         s_retention.retent.tagmem.link_addr = NULL;
142 #endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
143     } else {
144 #if SOC_PM_SUPPORT_TAGMEM_PD
145         if (s_retention.retent.tagmem.link_addr) {
146             heap_caps_free(s_retention.retent.tagmem.link_addr);
147             s_retention.retent.tagmem.icache.enable = 0;
148             s_retention.retent.tagmem.dcache.enable = 0;
149             s_retention.retent.tagmem.link_addr = NULL;
150         }
151 #endif
152     }
153     return ESP_OK;
154 }
155 
156 #endif // SOC_PM_SUPPORT_TAGMEM_PD
157 
158 #if SOC_PM_SUPPORT_CPU_PD
159 
160 #if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
161 #define CPU_PD_MEM_TYPE_CAPS        (MALLOC_CAP_RETENTION | MALLOC_CAP_DEFAULT)
162 #else
163 #define CPU_PD_MEM_TYPE_CAPS        (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT)
164 #endif
165 
esp_sleep_cpu_pd_low_init(bool enable)166 esp_err_t esp_sleep_cpu_pd_low_init(bool enable)
167 {
168     if (enable) {
169         if (s_retention.retent.cpu_pd_mem == NULL) {
170             void *buf = heap_caps_aligned_alloc(SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN,
171                                                 SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE,
172                                                 CPU_PD_MEM_TYPE_CAPS);
173             if (buf) {
174                 memset(buf, 0, SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE);
175                 s_retention.retent.cpu_pd_mem = rtc_cntl_hal_dma_link_init(buf,
176                                       (uint32_t *)buf + RTC_HAL_DMA_LINK_NODE_SIZE, SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE, NULL);
177             } else {
178                 return ESP_ERR_NO_MEM;
179             }
180         }
181     } else {
182         if (s_retention.retent.cpu_pd_mem) {
183             heap_caps_free(s_retention.retent.cpu_pd_mem);
184             s_retention.retent.cpu_pd_mem = NULL;
185         }
186     }
187 #if SOC_PM_SUPPORT_TAGMEM_PD
188     if (esp_sleep_tagmem_pd_low_init(enable) != ESP_OK) {
189 #ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
190         esp_sleep_cpu_pd_low_init(false);
191         return ESP_ERR_NO_MEM;
192 #endif
193     }
194 #endif
195     return ESP_OK;
196 }
197 
cpu_domain_pd_allowed(void)198 bool cpu_domain_pd_allowed(void)
199 {
200     return (s_retention.retent.cpu_pd_mem != NULL);
201 }
202 
203 #endif // SOC_PM_SUPPORT_CPU_PD
204 
205 #if SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD
206 
sleep_enable_memory_retention(void)207 void sleep_enable_memory_retention(void)
208 {
209 #if SOC_PM_SUPPORT_CPU_PD
210     rtc_cntl_hal_enable_cpu_retention(&s_retention.retent);
211 #endif
212 #if SOC_PM_SUPPORT_TAGMEM_PD
213     rtc_cntl_hal_enable_tagmem_retention(&s_retention.retent);
214 #endif
215 }
216 
sleep_disable_memory_retention(void)217 void IRAM_ATTR sleep_disable_memory_retention(void)
218 {
219 #if SOC_PM_SUPPORT_CPU_PD
220     rtc_cntl_hal_disable_cpu_retention(&s_retention.retent);
221 #endif
222 #if SOC_PM_SUPPORT_TAGMEM_PD
223     rtc_cntl_hal_disable_tagmem_retention(&s_retention.retent);
224 #endif
225 }
226 
227 #endif // SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD
228