1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2c_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_I2C_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_I2C_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2c 67 * @defgroup i2c_registers I2C_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup i2c_registers 74 * Structure type to access the I2C Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cn; /**< <tt>\b 0x00:</tt> I2C CN Register */ 78 __IO uint32_t st; /**< <tt>\b 0x04:</tt> I2C ST Register */ 79 __IO uint32_t int0; /**< <tt>\b 0x08:</tt> I2C INT0 Register */ 80 __IO uint32_t inten0; /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */ 81 __IO uint32_t int1; /**< <tt>\b 0x10:</tt> I2C INT1 Register */ 82 __IO uint32_t inten1; /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */ 83 __IO uint32_t fifo; /**< <tt>\b 0x18:</tt> I2C FIFO Register */ 84 __IO uint32_t rxcfg; /**< <tt>\b 0x1C:</tt> I2C RXCFG Register */ 85 __IO uint32_t rx; /**< <tt>\b 0x20:</tt> I2C RX Register */ 86 __IO uint32_t txcfg; /**< <tt>\b 0x24:</tt> I2C TXCFG Register */ 87 __IO uint32_t tx; /**< <tt>\b 0x28:</tt> I2C TX Register */ 88 __IO uint32_t data; /**< <tt>\b 0x2C:</tt> I2C DATA Register */ 89 __IO uint32_t mcn; /**< <tt>\b 0x30:</tt> I2C MCN Register */ 90 __IO uint32_t ckl; /**< <tt>\b 0x34:</tt> I2C CKL Register */ 91 __IO uint32_t ckh; /**< <tt>\b 0x38:</tt> I2C CKH Register */ 92 __R uint32_t rsv_0x3c; 93 __IO uint32_t to; /**< <tt>\b 0x40:</tt> I2C TO Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 96 __IO uint32_t sla; /**< <tt>\b 0x4C:</tt> I2C SLA Register */ 97 } mxc_i2c_regs_t; 98 99 /* Register offsets for module I2C */ 100 /** 101 * @ingroup i2c_registers 102 * @defgroup I2C_Register_Offsets Register Offsets 103 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 104 * @{ 105 */ 106 #define MXC_R_I2C_CN ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 107 #define MXC_R_I2C_ST ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_I2C_INT0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_I2C_INT1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 111 #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 112 #define MXC_R_I2C_FIFO ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 113 #define MXC_R_I2C_RXCFG ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 114 #define MXC_R_I2C_RX ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 115 #define MXC_R_I2C_TXCFG ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 116 #define MXC_R_I2C_TX ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 117 #define MXC_R_I2C_DATA ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 118 #define MXC_R_I2C_MCN ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 119 #define MXC_R_I2C_CKL ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 120 #define MXC_R_I2C_CKH ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 121 #define MXC_R_I2C_TO ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 122 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 123 #define MXC_R_I2C_SLA ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */ 124 /**@} end of group i2c_registers */ 125 126 /** 127 * @ingroup i2c_registers 128 * @defgroup I2C_CN I2C_CN 129 * @brief Control Register0. 130 * @{ 131 */ 132 #define MXC_F_I2C_CN_I2CEN_POS 0 /**< CN_I2CEN Position */ 133 #define MXC_F_I2C_CN_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CN_I2CEN_POS)) /**< CN_I2CEN Mask */ 134 135 #define MXC_F_I2C_CN_MST_POS 1 /**< CN_MST Position */ 136 #define MXC_F_I2C_CN_MST ((uint32_t)(0x1UL << MXC_F_I2C_CN_MST_POS)) /**< CN_MST Mask */ 137 138 #define MXC_F_I2C_CN_GCEN_POS 2 /**< CN_GCEN Position */ 139 #define MXC_F_I2C_CN_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CN_GCEN_POS)) /**< CN_GCEN Mask */ 140 141 #define MXC_F_I2C_CN_IRXM_POS 3 /**< CN_IRXM Position */ 142 #define MXC_F_I2C_CN_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CN_IRXM_POS)) /**< CN_IRXM Mask */ 143 144 #define MXC_F_I2C_CN_ACK_POS 4 /**< CN_ACK Position */ 145 #define MXC_F_I2C_CN_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CN_ACK_POS)) /**< CN_ACK Mask */ 146 147 #define MXC_F_I2C_CN_SCLO_POS 6 /**< CN_SCLO Position */ 148 #define MXC_F_I2C_CN_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CN_SCLO_POS)) /**< CN_SCLO Mask */ 149 150 #define MXC_F_I2C_CN_SDAO_POS 7 /**< CN_SDAO Position */ 151 #define MXC_F_I2C_CN_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CN_SDAO_POS)) /**< CN_SDAO Mask */ 152 153 #define MXC_F_I2C_CN_SCL_POS 8 /**< CN_SCL Position */ 154 #define MXC_F_I2C_CN_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CN_SCL_POS)) /**< CN_SCL Mask */ 155 156 #define MXC_F_I2C_CN_SDA_POS 9 /**< CN_SDA Position */ 157 #define MXC_F_I2C_CN_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CN_SDA_POS)) /**< CN_SDA Mask */ 158 159 #define MXC_F_I2C_CN_SWOE_POS 10 /**< CN_SWOE Position */ 160 #define MXC_F_I2C_CN_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CN_SWOE_POS)) /**< CN_SWOE Mask */ 161 162 #define MXC_F_I2C_CN_READ_POS 11 /**< CN_READ Position */ 163 #define MXC_F_I2C_CN_READ ((uint32_t)(0x1UL << MXC_F_I2C_CN_READ_POS)) /**< CN_READ Mask */ 164 165 #define MXC_F_I2C_CN_SCLSTRD_POS 12 /**< CN_SCLSTRD Position */ 166 #define MXC_F_I2C_CN_SCLSTRD ((uint32_t)(0x1UL << MXC_F_I2C_CN_SCLSTRD_POS)) /**< CN_SCLSTRD Mask */ 167 168 #define MXC_F_I2C_CN_SCLPPM_POS 13 /**< CN_SCLPPM Position */ 169 #define MXC_F_I2C_CN_SCLPPM ((uint32_t)(0x1UL << MXC_F_I2C_CN_SCLPPM_POS)) /**< CN_SCLPPM Mask */ 170 171 /**@} end of group I2C_CN_Register */ 172 173 /** 174 * @ingroup i2c_registers 175 * @defgroup I2C_ST I2C_ST 176 * @brief Status Register. 177 * @{ 178 */ 179 #define MXC_F_I2C_ST_BUS_POS 0 /**< ST_BUS Position */ 180 #define MXC_F_I2C_ST_BUS ((uint32_t)(0x1UL << MXC_F_I2C_ST_BUS_POS)) /**< ST_BUS Mask */ 181 182 #define MXC_F_I2C_ST_RXE_POS 1 /**< ST_RXE Position */ 183 #define MXC_F_I2C_ST_RXE ((uint32_t)(0x1UL << MXC_F_I2C_ST_RXE_POS)) /**< ST_RXE Mask */ 184 185 #define MXC_F_I2C_ST_RXF_POS 2 /**< ST_RXF Position */ 186 #define MXC_F_I2C_ST_RXF ((uint32_t)(0x1UL << MXC_F_I2C_ST_RXF_POS)) /**< ST_RXF Mask */ 187 188 #define MXC_F_I2C_ST_TXE_POS 3 /**< ST_TXE Position */ 189 #define MXC_F_I2C_ST_TXE ((uint32_t)(0x1UL << MXC_F_I2C_ST_TXE_POS)) /**< ST_TXE Mask */ 190 191 #define MXC_F_I2C_ST_TXF_POS 4 /**< ST_TXF Position */ 192 #define MXC_F_I2C_ST_TXF ((uint32_t)(0x1UL << MXC_F_I2C_ST_TXF_POS)) /**< ST_TXF Mask */ 193 194 #define MXC_F_I2C_ST_CKMD_POS 5 /**< ST_CKMD Position */ 195 #define MXC_F_I2C_ST_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_ST_CKMD_POS)) /**< ST_CKMD Mask */ 196 197 #define MXC_F_I2C_ST_ST_POS 8 /**< ST_ST Position */ 198 #define MXC_F_I2C_ST_ST ((uint32_t)(0xFUL << MXC_F_I2C_ST_ST_POS)) /**< ST_ST Mask */ 199 200 /**@} end of group I2C_ST_Register */ 201 202 /** 203 * @ingroup i2c_registers 204 * @defgroup I2C_INT0 I2C_INT0 205 * @brief Interrupt Status Register. 206 * @{ 207 */ 208 #define MXC_F_I2C_INT0_DONEI_POS 0 /**< INT0_DONEI Position */ 209 #define MXC_F_I2C_INT0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_DONEI_POS)) /**< INT0_DONEI Mask */ 210 211 #define MXC_F_I2C_INT0_IRXMI_POS 1 /**< INT0_IRXMI Position */ 212 #define MXC_F_I2C_INT0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_IRXMI_POS)) /**< INT0_IRXMI Mask */ 213 214 #define MXC_F_I2C_INT0_GCI_POS 2 /**< INT0_GCI Position */ 215 #define MXC_F_I2C_INT0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_GCI_POS)) /**< INT0_GCI Mask */ 216 217 #define MXC_F_I2C_INT0_AMI_POS 3 /**< INT0_AMI Position */ 218 #define MXC_F_I2C_INT0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_AMI_POS)) /**< INT0_AMI Mask */ 219 220 #define MXC_F_I2C_INT0_RXTHI_POS 4 /**< INT0_RXTHI Position */ 221 #define MXC_F_I2C_INT0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_RXTHI_POS)) /**< INT0_RXTHI Mask */ 222 223 #define MXC_F_I2C_INT0_TXTHI_POS 5 /**< INT0_TXTHI Position */ 224 #define MXC_F_I2C_INT0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_TXTHI_POS)) /**< INT0_TXTHI Mask */ 225 226 #define MXC_F_I2C_INT0_STOPI_POS 6 /**< INT0_STOPI Position */ 227 #define MXC_F_I2C_INT0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_STOPI_POS)) /**< INT0_STOPI Mask */ 228 229 #define MXC_F_I2C_INT0_ADRACKI_POS 7 /**< INT0_ADRACKI Position */ 230 #define MXC_F_I2C_INT0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_ADRACKI_POS)) /**< INT0_ADRACKI Mask */ 231 232 #define MXC_F_I2C_INT0_ARBERI_POS 8 /**< INT0_ARBERI Position */ 233 #define MXC_F_I2C_INT0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_ARBERI_POS)) /**< INT0_ARBERI Mask */ 234 235 #define MXC_F_I2C_INT0_TOERI_POS 9 /**< INT0_TOERI Position */ 236 #define MXC_F_I2C_INT0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_TOERI_POS)) /**< INT0_TOERI Mask */ 237 238 #define MXC_F_I2C_INT0_ADRERI_POS 10 /**< INT0_ADRERI Position */ 239 #define MXC_F_I2C_INT0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_ADRERI_POS)) /**< INT0_ADRERI Mask */ 240 241 #define MXC_F_I2C_INT0_DATERI_POS 11 /**< INT0_DATERI Position */ 242 #define MXC_F_I2C_INT0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_DATERI_POS)) /**< INT0_DATERI Mask */ 243 244 #define MXC_F_I2C_INT0_DNRERI_POS 12 /**< INT0_DNRERI Position */ 245 #define MXC_F_I2C_INT0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_DNRERI_POS)) /**< INT0_DNRERI Mask */ 246 247 #define MXC_F_I2C_INT0_STRTERI_POS 13 /**< INT0_STRTERI Position */ 248 #define MXC_F_I2C_INT0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_STRTERI_POS)) /**< INT0_STRTERI Mask */ 249 250 #define MXC_F_I2C_INT0_STOPERI_POS 14 /**< INT0_STOPERI Position */ 251 #define MXC_F_I2C_INT0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_STOPERI_POS)) /**< INT0_STOPERI Mask */ 252 253 #define MXC_F_I2C_INT0_TXLOI_POS 15 /**< INT0_TXLOI Position */ 254 #define MXC_F_I2C_INT0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_TXLOI_POS)) /**< INT0_TXLOI Mask */ 255 256 #define MXC_F_I2C_INT0_RDAMI_POS 22 /**< INT0_RDAMI Position */ 257 #define MXC_F_I2C_INT0_RDAMI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_RDAMI_POS)) /**< INT0_RDAMI Mask */ 258 259 #define MXC_F_I2C_INT0_WRAMI_POS 23 /**< INT0_WRAMI Position */ 260 #define MXC_F_I2C_INT0_WRAMI ((uint32_t)(0x1UL << MXC_F_I2C_INT0_WRAMI_POS)) /**< INT0_WRAMI Mask */ 261 262 /**@} end of group I2C_INT0_Register */ 263 264 /** 265 * @ingroup i2c_registers 266 * @defgroup I2C_INTEN0 I2C_INTEN0 267 * @brief Interrupt Enable Register. 268 * @{ 269 */ 270 #define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */ 271 #define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */ 272 273 #define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */ 274 #define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */ 275 276 #define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */ 277 #define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */ 278 279 #define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */ 280 #define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */ 281 282 #define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */ 283 #define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */ 284 285 #define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */ 286 #define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */ 287 288 #define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */ 289 #define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */ 290 291 #define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */ 292 #define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */ 293 294 #define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */ 295 #define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */ 296 297 #define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */ 298 #define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */ 299 300 #define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */ 301 #define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */ 302 303 #define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */ 304 #define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */ 305 306 #define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */ 307 #define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */ 308 309 #define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */ 310 #define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */ 311 312 #define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */ 313 #define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */ 314 315 #define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */ 316 #define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */ 317 318 /**@} end of group I2C_INTEN0_Register */ 319 320 /** 321 * @ingroup i2c_registers 322 * @defgroup I2C_INT1 I2C_INT1 323 * @brief Interrupt Status Register 1. 324 * @{ 325 */ 326 #define MXC_F_I2C_INT1_RXOFI_POS 0 /**< INT1_RXOFI Position */ 327 #define MXC_F_I2C_INT1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INT1_RXOFI_POS)) /**< INT1_RXOFI Mask */ 328 329 #define MXC_F_I2C_INT1_TXUFI_POS 1 /**< INT1_TXUFI Position */ 330 #define MXC_F_I2C_INT1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INT1_TXUFI_POS)) /**< INT1_TXUFI Mask */ 331 332 /**@} end of group I2C_INT1_Register */ 333 334 /** 335 * @ingroup i2c_registers 336 * @defgroup I2C_INTEN1 I2C_INTEN1 337 * @brief Interrupt Staus Register 1. 338 * @{ 339 */ 340 #define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */ 341 #define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */ 342 343 #define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */ 344 #define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */ 345 346 /**@} end of group I2C_INTEN1_Register */ 347 348 /** 349 * @ingroup i2c_registers 350 * @defgroup I2C_FIFO I2C_FIFO 351 * @brief FIFO Configuration Register. 352 * @{ 353 */ 354 #define MXC_F_I2C_FIFO_RXLEN_POS 0 /**< FIFO_RXLEN Position */ 355 #define MXC_F_I2C_FIFO_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_RXLEN_POS)) /**< FIFO_RXLEN Mask */ 356 357 #define MXC_F_I2C_FIFO_TXLEN_POS 8 /**< FIFO_TXLEN Position */ 358 #define MXC_F_I2C_FIFO_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_TXLEN_POS)) /**< FIFO_TXLEN Mask */ 359 360 /**@} end of group I2C_FIFO_Register */ 361 362 /** 363 * @ingroup i2c_registers 364 * @defgroup I2C_RXCFG I2C_RXCFG 365 * @brief Receive Control Register 0. 366 * @{ 367 */ 368 #define MXC_F_I2C_RXCFG_DNR_POS 0 /**< RXCFG_DNR Position */ 369 #define MXC_F_I2C_RXCFG_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCFG_DNR_POS)) /**< RXCFG_DNR Mask */ 370 371 #define MXC_F_I2C_RXCFG_RXFSH_POS 7 /**< RXCFG_RXFSH Position */ 372 #define MXC_F_I2C_RXCFG_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCFG_RXFSH_POS)) /**< RXCFG_RXFSH Mask */ 373 374 #define MXC_F_I2C_RXCFG_RXTH_POS 8 /**< RXCFG_RXTH Position */ 375 #define MXC_F_I2C_RXCFG_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCFG_RXTH_POS)) /**< RXCFG_RXTH Mask */ 376 377 /**@} end of group I2C_RXCFG_Register */ 378 379 /** 380 * @ingroup i2c_registers 381 * @defgroup I2C_RX I2C_RX 382 * @brief Receive Control Register 1. 383 * @{ 384 */ 385 #define MXC_F_I2C_RX_RXCNT_POS 0 /**< RX_RXCNT Position */ 386 #define MXC_F_I2C_RX_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_RXCNT_POS)) /**< RX_RXCNT Mask */ 387 388 #define MXC_F_I2C_RX_RXFIFO_POS 8 /**< RX_RXFIFO Position */ 389 #define MXC_F_I2C_RX_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_RXFIFO_POS)) /**< RX_RXFIFO Mask */ 390 391 /**@} end of group I2C_RX_Register */ 392 393 /** 394 * @ingroup i2c_registers 395 * @defgroup I2C_TXCFG I2C_TXCFG 396 * @brief Transmit Control Register 0. 397 * @{ 398 */ 399 #define MXC_F_I2C_TXCFG_TXPRELD_POS 0 /**< TXCFG_TXPRELD Position */ 400 #define MXC_F_I2C_TXCFG_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCFG_TXPRELD_POS)) /**< TXCFG_TXPRELD Mask */ 401 402 #define MXC_F_I2C_TXCFG_TXRDYMMODE_POS 1 /**< TXCFG_TXRDYMMODE Position */ 403 #define MXC_F_I2C_TXCFG_TXRDYMMODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCFG_TXRDYMMODE_POS)) /**< TXCFG_TXRDYMMODE Mask */ 404 405 #define MXC_F_I2C_TXCFG_TXFSH_POS 7 /**< TXCFG_TXFSH Position */ 406 #define MXC_F_I2C_TXCFG_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCFG_TXFSH_POS)) /**< TXCFG_TXFSH Mask */ 407 408 #define MXC_F_I2C_TXCFG_TXTH_POS 8 /**< TXCFG_TXTH Position */ 409 #define MXC_F_I2C_TXCFG_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCFG_TXTH_POS)) /**< TXCFG_TXTH Mask */ 410 411 /**@} end of group I2C_TXCFG_Register */ 412 413 /** 414 * @ingroup i2c_registers 415 * @defgroup I2C_TX I2C_TX 416 * @brief Transmit Control Register 1. 417 * @{ 418 */ 419 #define MXC_F_I2C_TX_TXRDY_POS 0 /**< TX_TXRDY Position */ 420 #define MXC_F_I2C_TX_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TX_TXRDY_POS)) /**< TX_TXRDY Mask */ 421 422 #define MXC_F_I2C_TX_TXLAST_POS 1 /**< TX_TXLAST Position */ 423 #define MXC_F_I2C_TX_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_TXLAST_POS)) /**< TX_TXLAST Mask */ 424 425 #define MXC_F_I2C_TX_TXFIFO_POS 8 /**< TX_TXFIFO Position */ 426 #define MXC_F_I2C_TX_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_TXFIFO_POS)) /**< TX_TXFIFO Mask */ 427 428 /**@} end of group I2C_TX_Register */ 429 430 /** 431 * @ingroup i2c_registers 432 * @defgroup I2C_DATA I2C_DATA 433 * @brief Data Register. 434 * @{ 435 */ 436 #define MXC_F_I2C_DATA_DATA_POS 0 /**< DATA_DATA Position */ 437 #define MXC_F_I2C_DATA_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_DATA_DATA_POS)) /**< DATA_DATA Mask */ 438 439 /**@} end of group I2C_DATA_Register */ 440 441 /** 442 * @ingroup i2c_registers 443 * @defgroup I2C_MCN I2C_MCN 444 * @brief Master Control Register. 445 * @{ 446 */ 447 #define MXC_F_I2C_MCN_START_POS 0 /**< MCN_START Position */ 448 #define MXC_F_I2C_MCN_START ((uint32_t)(0x1UL << MXC_F_I2C_MCN_START_POS)) /**< MCN_START Mask */ 449 450 #define MXC_F_I2C_MCN_RESTART_POS 1 /**< MCN_RESTART Position */ 451 #define MXC_F_I2C_MCN_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MCN_RESTART_POS)) /**< MCN_RESTART Mask */ 452 453 #define MXC_F_I2C_MCN_STOP_POS 2 /**< MCN_STOP Position */ 454 #define MXC_F_I2C_MCN_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MCN_STOP_POS)) /**< MCN_STOP Mask */ 455 456 #define MXC_F_I2C_MCN_SEA_POS 7 /**< MCN_SEA Position */ 457 #define MXC_F_I2C_MCN_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MCN_SEA_POS)) /**< MCN_SEA Mask */ 458 459 /**@} end of group I2C_MCN_Register */ 460 461 /** 462 * @ingroup i2c_registers 463 * @defgroup I2C_CKL I2C_CKL 464 * @brief Clock Low Register. 465 * @{ 466 */ 467 #define MXC_F_I2C_CKL_CKL_POS 0 /**< CKL_CKL Position */ 468 #define MXC_F_I2C_CKL_CKL ((uint32_t)(0x1FFUL << MXC_F_I2C_CKL_CKL_POS)) /**< CKL_CKL Mask */ 469 470 /**@} end of group I2C_CKL_Register */ 471 472 /** 473 * @ingroup i2c_registers 474 * @defgroup I2C_CKH I2C_CKH 475 * @brief Clock high Register. 476 * @{ 477 */ 478 #define MXC_F_I2C_CKH_CKH_POS 0 /**< CKH_CKH Position */ 479 #define MXC_F_I2C_CKH_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CKH_CKH_POS)) /**< CKH_CKH Mask */ 480 481 /**@} end of group I2C_CKH_Register */ 482 483 /** 484 * @ingroup i2c_registers 485 * @defgroup I2C_TO I2C_TO 486 * @brief Timeout Register 487 * @{ 488 */ 489 #define MXC_F_I2C_TO_TO_POS 0 /**< TO_TO Position */ 490 #define MXC_F_I2C_TO_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TO_TO_POS)) /**< TO_TO Mask */ 491 492 /**@} end of group I2C_TO_Register */ 493 494 /** 495 * @ingroup i2c_registers 496 * @defgroup I2C_DMA I2C_DMA 497 * @brief DMA Register. 498 * @{ 499 */ 500 #define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */ 501 #define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ 502 503 #define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */ 504 #define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ 505 506 /**@} end of group I2C_DMA_Register */ 507 508 /** 509 * @ingroup i2c_registers 510 * @defgroup I2C_SLA I2C_SLA 511 * @brief Slave Address Register. 512 * @{ 513 */ 514 #define MXC_F_I2C_SLA_SLA_POS 0 /**< SLA_SLA Position */ 515 #define MXC_F_I2C_SLA_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLA_SLA_POS)) /**< SLA_SLA Mask */ 516 #define MXC_V_I2C_SLA_SLA_DIS ((uint32_t)0x0UL) /**< SLA_SLA_DIS Value */ 517 #define MXC_S_I2C_SLA_SLA_DIS (MXC_V_I2C_SLA_SLA_DIS << MXC_F_I2C_SLA_SLA_POS) /**< SLA_SLA_DIS Setting */ 518 #define MXC_V_I2C_SLA_SLA_EN ((uint32_t)0x1UL) /**< SLA_SLA_EN Value */ 519 #define MXC_S_I2C_SLA_SLA_EN (MXC_V_I2C_SLA_SLA_EN << MXC_F_I2C_SLA_SLA_POS) /**< SLA_SLA_EN Setting */ 520 521 #define MXC_F_I2C_SLA_EA_POS 15 /**< SLA_EA Position */ 522 #define MXC_F_I2C_SLA_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLA_EA_POS)) /**< SLA_EA Mask */ 523 524 /**@} end of group I2C_SLA_Register */ 525 526 #ifdef __cplusplus 527 } 528 #endif 529 530 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_I2C_REGS_H_ 531
