1 /*!
2 \file gd32e50x_shrtimer.c
3 \brief SHRTIMER driver
4
5 \version 2020-03-10, V1.0.0, firmware for GD32E50x
6 \version 2020-08-26, V1.1.0, firmware for GD32E50x
7 \version 2020-09-16, V1.1.1, firmware for GD32E50x
8 \version 2021-03-23, V1.2.0, firmware for GD32E50x
9 */
10
11 /*
12 Copyright (c) 2021, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38 #include "gd32e50x_shrtimer.h"
39
40 #ifndef GD32EPRT
41
42 /* SHRTIMER related parameter mask */
43 #define CNTCKDIV2_0_MASK (uint32_t)(0x00000007)
44 #define CNTCKDIV3_MASK (uint32_t)(0x00000008)
45 #define STX_UPDATESOURCE_MASK (SHRTIMER_STXCTL0_UPBST0 | SHRTIMER_STXCTL0_UPBST1 | SHRTIMER_STXCTL0_UPBST2 | SHRTIMER_STXCTL0_UPBST3 | SHRTIMER_STXCTL0_UPBST4 | SHRTIMER_STXCTL0_UPBMT)
46 #define STX_FAULTCH_MASK (SHRTIMER_STXFLTCTL_FLT0EN | SHRTIMER_STXFLTCTL_FLT1EN | SHRTIMER_STXFLTCTL_FLT2EN | SHRTIMER_STXFLTCTL_FLT3EN | SHRTIMER_STXFLTCTL_FLT4EN)
47
48 /* configure Master_TIMER timer base */
49 static void master_timer_base_config(uint32_t shrtimer_periph, shrtimer_baseinit_parameter_struct* master_baseinit);
50 /* configure Master_TIMER in waveform mode */
51 static void master_timer_waveform_config(uint32_t shrtimer_periph, shrtimer_timerinit_parameter_struct * master_timerinit);
52 /* configure Slave_TIMER timer base */
53 static void slave_timer_base_config(uint32_t shrtimer_periph, uint32_t slave_id, shrtimer_baseinit_parameter_struct* slave_baseinit);
54 /* configure Slave_TIMER in waveform mode */
55 static void slave_timer_waveform_config(uint32_t shrtimer_periph, uint32_t slave_id, shrtimer_timerinit_parameter_struct * slave_timerinit);
56 /* configure the an external event channel */
57 static void external_event_config(uint32_t shrtimer_periph, uint32_t event_id, shrtimer_exeventcfg_parameter_struct* eventcfg);
58 /* configure the channel output */
59 static void channel_output_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel, shrtimer_channel_outputcfg_parameter_struct * outcfg);
60
61 /*!
62 \brief deinit a SHRTIMER
63 \param[in] shrtimer_periph: SHRTIMER0
64 \param[out] none
65 \retval none
66 */
shrtimer_deinit(uint32_t shrtimer_periph)67 void shrtimer_deinit(uint32_t shrtimer_periph)
68 {
69 switch(shrtimer_periph){
70 case SHRTIMER0:
71 /* reset SHRTIMER0 */
72 rcu_periph_reset_enable(RCU_SHRTIMERRST);
73 rcu_periph_reset_disable(RCU_SHRTIMERRST);
74 break;
75 default:
76 break;
77 }
78 }
79
80 /*!
81 \brief configure and start DLL calibration
82 \param[in] shrtimer_periph: SHRTIMER0
83 \param[in] calform: specify the calibration form
84 only one can be selected which is shown as below:
85 \arg SHRTIMER_CALIBRATION_ONCE: DLL calibration start once
86 \arg SHRTIMER_CALIBRATION_1048576_PERIOD: DLL periodic calibration, the length of the DLL calibration cycle is 1048576 * tSHRTIMER_CK
87 \arg SHRTIMER_CALIBRATION_131072_PERIOD: DLL periodic calibration, the length of the DLL calibration cycle is 131072 * tSHRTIMER_CK
88 \arg SHRTIMER_CALIBRATION_16384_PERIOD: DLL periodic calibration, the length of the DLL calibration cycle is 16384 * tSHRTIMER_CK
89 \arg SHRTIMER_CALIBRATION_2048_PERIOD: DLL periodic calibration, the length of the DLL calibration cycle is 2048 * tSHRTIMER_CK
90 \param[out] none
91 \retval none
92 */
shrtimer_dll_calibration_start(uint32_t shrtimer_periph,uint32_t calform)93 void shrtimer_dll_calibration_start(uint32_t shrtimer_periph, uint32_t calform)
94 {
95 uint32_t dllcctl_reg;
96
97 /* configure DLL calibration */
98 dllcctl_reg = SHRTIMER_DLLCCTL(shrtimer_periph);
99
100 if (SHRTIMER_CALIBRATION_ONCE == calform){
101 /* DLL periodic calibration disable */
102 dllcctl_reg &= ~(SHRTIMER_DLLCCTL_CLBPEREN);
103 dllcctl_reg |= SHRTIMER_DLLCCTL_CLBSTRT;
104 }else{
105 /* DLL periodic calibration enable */
106 dllcctl_reg &= ~(SHRTIMER_DLLCCTL_CLBPER | SHRTIMER_DLLCCTL_CLBSTRT);
107 dllcctl_reg |= (calform | SHRTIMER_DLLCCTL_CLBPEREN);
108 }
109
110 SHRTIMER_DLLCCTL(shrtimer_periph) = dllcctl_reg;
111 }
112
113 /*!
114 \brief initialize SHRTIMER time base parameters struct with a default value
115 \param[in] baseinit: SHRTIMER time base parameters struct
116 \param[out] none
117 \retval none
118 */
shrtimer_baseinit_struct_para_init(shrtimer_baseinit_parameter_struct * baseinit)119 void shrtimer_baseinit_struct_para_init(shrtimer_baseinit_parameter_struct* baseinit)
120 {
121 baseinit->counter_mode = SHRTIMER_COUNTER_MODE_SINGLEPULSE;
122 baseinit->period = 0xFFDFU;
123 baseinit->prescaler = SHRTIMER_PRESCALER_MUL32;
124 baseinit->repetitioncounter = 0x00U;
125 }
126
127 /*!
128 \brief initialize Master_TIMER and Slave_TIMER timerbase
129 \param[in] shrtimer_periph: SHRTIMER0
130 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
131 \param[in] baseinit: SHRTIMER time base parameters struct
132 period: period value, min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
133 repetitioncounter: the counter repetition value, 0x00~0xFF
134 prescaler: SHRTIMER_PRESCALER_MULy(y=64,32,16,8,4,2), SHRTIMER_PRESCALER_DIVy(y=1,2,4)
135 counter_mode: SHRTIMER_COUNTER_MODE_CONTINOUS, SHRTIMER_COUNTER_MODE_SINGLEPULSE, SHRTIMER_COUNTER_MODE_SINGLEPULSE_RETRIGGERABLE
136 \param[out] none
137 \retval none
138 */
shrtimer_timers_base_init(uint32_t shrtimer_periph,uint32_t timer_id,shrtimer_baseinit_parameter_struct * baseinit)139 void shrtimer_timers_base_init(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_baseinit_parameter_struct* baseinit)
140 {
141 if(SHRTIMER_MASTER_TIMER == timer_id)
142 {
143 /* configure Master_TIMER timer base */
144 master_timer_base_config(shrtimer_periph, baseinit);
145 }else{
146 /* configure Slave_TIMER timer base */
147 slave_timer_base_config(shrtimer_periph, timer_id, baseinit);
148 }
149 }
150
151 /*!
152 \brief enable a counter
153 \param[in] shrtimer_periph: SHRTIMER0
154 \param[in] cntid: specify the counter to configure
155 only one can be selected which is shown as below:
156 \arg SHRTIMER_MT_COUNTER: the counter of Master_TIMER
157 \arg SHRTIMER_ST0_COUNTER: the counter of Slave_TIMER0
158 \arg SHRTIMER_ST1_COUNTER: the counter of Slave_TIMER1
159 \arg SHRTIMER_ST2_COUNTER: the counter of Slave_TIMER2
160 \arg SHRTIMER_ST3_COUNTER: the counter of Slave_TIMER3
161 \arg SHRTIMER_ST4_COUNTER: the counter of Slave_TIMER4
162 \param[out] none
163 \retval none
164 */
shrtimer_timers_counter_enable(uint32_t shrtimer_periph,uint32_t cntid)165 void shrtimer_timers_counter_enable(uint32_t shrtimer_periph, uint32_t cntid)
166 {
167 SHRTIMER_MTCTL0(shrtimer_periph) |= cntid;
168 }
169
170 /*!
171 \brief disable a counter
172 \param[in] shrtimer_periph: SHRTIMER0
173 \param[in] cntid: specify the counter to configure
174 only one can be selected which is shown as below:
175 \arg SHRTIMER_MT_COUNTER: the counter of Master_TIMER
176 \arg SHRTIMER_ST0_COUNTER: the counter of Slave_TIMER0
177 \arg SHRTIMER_ST1_COUNTER: the counter of Slave_TIMER1
178 \arg SHRTIMER_ST2_COUNTER: the counter of Slave_TIMER2
179 \arg SHRTIMER_ST3_COUNTER: the counter of Slave_TIMER3
180 \arg SHRTIMER_ST4_COUNTER: the counter of Slave_TIMER4
181 \param[out] none
182 \retval none
183 */
shrtimer_timers_counter_disable(uint32_t shrtimer_periph,uint32_t cntid)184 void shrtimer_timers_counter_disable(uint32_t shrtimer_periph, uint32_t cntid)
185 {
186 SHRTIMER_MTCTL0(shrtimer_periph) &= ~(cntid);
187 }
188
189 /*!
190 \brief enable the Master_TIMER or Slave_TIMER update event
191 \param[in] shrtimer_periph: SHRTIMER0
192 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
193 \param[out] none
194 \retval none
195 */
shrtimer_timers_update_event_enable(uint32_t shrtimer_periph,uint32_t timer_id)196 void shrtimer_timers_update_event_enable(uint32_t shrtimer_periph, uint32_t timer_id)
197 {
198 switch(timer_id)
199 {
200 case SHRTIMER_MASTER_TIMER:
201 /* enable the Master_TIMER update event */
202 SHRTIMER_CTL0(shrtimer_periph) &= ~SHRTIMER_CTL0_MTUPDIS;
203 break;
204 case SHRTIMER_SLAVE_TIMER0:
205 /* enable the Slave_TIMER0 update event */
206 SHRTIMER_CTL0(shrtimer_periph) &= ~SHRTIMER_CTL0_ST0UPDIS;
207 break;
208 case SHRTIMER_SLAVE_TIMER1:
209 /* enable the Slave_TIMER1 update event */
210 SHRTIMER_CTL0(shrtimer_periph) &= ~SHRTIMER_CTL0_ST1UPDIS;
211 break;
212 case SHRTIMER_SLAVE_TIMER2:
213 /* enable the Slave_TIMER2 update event */
214 SHRTIMER_CTL0(shrtimer_periph) &= ~SHRTIMER_CTL0_ST2UPDIS;
215 break;
216 case SHRTIMER_SLAVE_TIMER3:
217 /* enable the Slave_TIMER3 update event */
218 SHRTIMER_CTL0(shrtimer_periph) &= ~SHRTIMER_CTL0_ST3UPDIS;
219 break;
220 case SHRTIMER_SLAVE_TIMER4:
221 /* enable the Slave_TIMER4 update event */
222 SHRTIMER_CTL0(shrtimer_periph) &= ~SHRTIMER_CTL0_ST4UPDIS;
223 break;
224 default:
225 break;
226 }
227 }
228
229 /*!
230 \brief disable the Master_TIMER or Slave_TIMER update event
231 \param[in] shrtimer_periph: SHRTIMER0
232 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
233 \param[out] none
234 \retval none
235 */
shrtimer_timers_update_event_disable(uint32_t shrtimer_periph,uint32_t timer_id)236 void shrtimer_timers_update_event_disable(uint32_t shrtimer_periph, uint32_t timer_id)
237 {
238 switch(timer_id)
239 {
240 case SHRTIMER_MASTER_TIMER:
241 /* disable the Master_TIMER update event */
242 SHRTIMER_CTL0(shrtimer_periph) |= SHRTIMER_CTL0_MTUPDIS;
243 break;
244 case SHRTIMER_SLAVE_TIMER0:
245 /* disable the Slave_TIMER0 update event */
246 SHRTIMER_CTL0(shrtimer_periph) |= SHRTIMER_CTL0_ST0UPDIS;
247 break;
248 case SHRTIMER_SLAVE_TIMER1:
249 /* disable the Slave_TIMER1 update event */
250 SHRTIMER_CTL0(shrtimer_periph) |= SHRTIMER_CTL0_ST1UPDIS;
251 break;
252 case SHRTIMER_SLAVE_TIMER2:
253 /* disable the Slave_TIMER2 update event */
254 SHRTIMER_CTL0(shrtimer_periph) |= SHRTIMER_CTL0_ST2UPDIS;
255 break;
256 case SHRTIMER_SLAVE_TIMER3:
257 /* disable the Slave_TIMER3 update event */
258 SHRTIMER_CTL0(shrtimer_periph) |= SHRTIMER_CTL0_ST3UPDIS;
259 break;
260 case SHRTIMER_SLAVE_TIMER4:
261 /* disable the Slave_TIMER4 update event */
262 SHRTIMER_CTL0(shrtimer_periph) |= SHRTIMER_CTL0_ST4UPDIS;
263 break;
264 default:
265 break;
266 }
267 }
268
269 /*!
270 \brief trigger the Master_TIMER and Slave_TIMER registers update by software
271 \param[in] shrtimer_periph: SHRTIMER0
272 \param[in] timersrc: which timer to be update by software
273 only one can be selected which is shown as below:
274 \arg SHRTIMER_UPDATE_SW_MT: Master_TIMER software update
275 \arg SHRTIMER_UPDATE_SW_ST0: Slave_TIMER0 software update
276 \arg SHRTIMER_UPDATE_SW_ST1: Slave_TIMER1 software update
277 \arg SHRTIMER_UPDATE_SW_ST2: Slave_TIMER2 software update
278 \arg SHRTIMER_UPDATE_SW_ST3: Slave_TIMER3 software update
279 \arg SHRTIMER_UPDATE_SW_ST4: Slave_TIMER4 software update
280 \param[out] none
281 \retval none
282 */
shrtimer_software_update(uint32_t shrtimer_periph,uint32_t timersrc)283 void shrtimer_software_update(uint32_t shrtimer_periph, uint32_t timersrc)
284 {
285 SHRTIMER_CTL1(shrtimer_periph) |= timersrc;
286 }
287
288 /*!
289 \brief reset the Master_TIMER and Slave_TIMER counter by software
290 \param[in] shrtimer_periph: SHRTIMER0
291 \param[in] timerrst: which timer to be reset by software
292 only one can be selected which is shown as below:
293 \arg SHRTIMER_COUNTER_RESET_SW_MT: Master_TIMER software reset
294 \arg SHRTIMER_COUNTER_RESET_SW_ST0: Slave_TIMER0 software reset
295 \arg SHRTIMER_COUNTER_RESET_SW_ST1: Slave_TIMER1 software reset
296 \arg SHRTIMER_COUNTER_RESET_SW_ST2: Slave_TIMER2 software reset
297 \arg SHRTIMER_COUNTER_RESET_SW_ST3: Slave_TIMER3 software reset
298 \arg SHRTIMER_COUNTER_RESET_SW_ST4: Slave_TIMER4 software reset
299 \param[out] none
300 \retval none
301 */
shrtimer_software_counter_reset(uint32_t shrtimer_periph,uint32_t timerrst)302 void shrtimer_software_counter_reset(uint32_t shrtimer_periph, uint32_t timerrst)
303 {
304 SHRTIMER_CTL1(shrtimer_periph) |= timerrst;
305 }
306
307 /*!
308 \brief initialize waveform mode initialization parameters struct with a default value
309 \param[in] timerinitpara: SHRTIMER waveform mode initialization parameters
310 \param[out] none
311 \retval none
312 */
shrtimer_timerinit_struct_para_init(shrtimer_timerinit_parameter_struct * timerinit)313 void shrtimer_timerinit_struct_para_init(shrtimer_timerinit_parameter_struct* timerinit)
314 {
315 timerinit->cnt_bunch = SHRTIMER_TIMERBUNCHNMODE_MAINTAINCLOCK;
316 timerinit->dac_trigger = SHRTIMER_DAC_TRIGGER_NONE;
317 timerinit->half_mode = SHRTIMER_HALFMODE_DISABLED;
318 timerinit->repetition_update = SHRTIMER_UPDATEONREPETITION_DISABLED;
319 timerinit->reset_sync = SHRTIMER_SYNCRESET_DISABLED;
320 timerinit->shadow = SHRTIMER_SHADOW_DISABLED;
321 timerinit->start_sync = SHRTIMER_SYNISTART_DISABLED;
322 timerinit->update_selection = SHRTIMER_MT_ST_UPDATE_SELECTION_INDEPENDENT;
323 }
324
325 /*!
326 \brief initialize a timer to work in waveform mode
327 \param[in] shrtimer_periph: SHRTIMER0
328 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
329 \param[in] timerinitpara: SHRTIMER waveform mode initialization parameters
330 half_mode: SHRTIMER_HALFMODE_DISABLED, SHRTIMER_HALFMODE_ENABLED
331 start_sync: SHRTIMER_SYNISTART_DISABLED, SHRTIMER_SYNISTART_ENABLED
332 reset_sync: SHRTIMER_SYNCRESET_DISABLED, SHRTIMER_SYNCRESET_ENABLED
333 dac_trigger: SHRTIMER_DAC_TRIGGER_NONE, SHRTIMER_DAC_TRIGGER_DACTRIGy(y=0..2)
334 shadow: SHRTIMER_SHADOW_DISABLED, SHRTIMER_SHADOW_ENABLED
335 update_selection: SHRTIMER_MT_ST_UPDATE_SELECTION_INDEPENDENT, for Master_TIMER and Slave_TIMER
336 SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE, for Master_TIMER and Slave_TIMER
337 SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE_UPDATE, for Master_TIMER and Slave_TIMER
338 SHRTIMER_ST_UPDATE_SELECTION_STXUPINy(y=2), for Slave_TIMER
339 SHRTIMER_ST_UPDATE_SELECTION_STXUPINy_UPDATE(y=2), for Slave_TIMER
340 cnt_bunch: SHRTIMER_TIMERBUNCHNMODE_MAINTAINCLOCK, SHRTIMER_TIMERBUNCHMODE_RESETCOUNTER
341 repetition_update: SHRTIMER_UPDATEONREPETITION_DISABLED, SHRTIMER_UPDATEONREPETITION_ENABLED
342 \param[out] none
343 \retval none
344 */
shrtimer_timers_waveform_init(uint32_t shrtimer_periph,uint32_t timer_id,shrtimer_timerinit_parameter_struct * timerinitpara)345 void shrtimer_timers_waveform_init(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_timerinit_parameter_struct* timerinitpara)
346 {
347 if(SHRTIMER_MASTER_TIMER == timer_id)
348 {
349 /* configure Master_TIMER in waveform mode */
350 master_timer_waveform_config(shrtimer_periph, timerinitpara);
351 }else{
352 /* configure Slave_TIMER in waveform mode */
353 slave_timer_waveform_config(shrtimer_periph, timer_id, timerinitpara);
354 }
355 }
356
357 /*!
358 \brief initialize Slave_TIMER general behavior configuration struct with a default value
359 \param[in] timercfg: Slave_TIMER general behavior configuration struct
360 \param[out] none
361 \retval none
362 */
shrtimer_timercfg_struct_para_init(shrtimer_timercfg_parameter_struct * timercgf)363 void shrtimer_timercfg_struct_para_init(shrtimer_timercfg_parameter_struct* timercgf)
364 {
365 timercgf->balanced_mode = SHRTIMER_STXBALANCEDMODE_DISABLED;
366 timercgf->cnt_reset = SHRTIMER_STXCNT_RESET_NONE;
367 timercgf->deadtime_enable = SHRTIMER_STXDEADTIME_DISABLED;
368 timercgf->delayed_idle = SHRTIMER_STXDELAYED_IDLE_DISABLED;
369 timercgf->fault_enable = SHRTIMER_STXFAULTENABLE_NONE;
370 timercgf->fault_protect = SHRTIMER_STXFAULT_PROTECT_READWRITE;
371 timercgf->reset_update = SHRTIMER_STXUPDATEONRESET_DISABLED;
372 timercgf->update_source = SHRTIMER_STXUPDATETRIGGER_NONE;
373 }
374
375 /*!
376 \brief configure the general behavior of a Slave_TIMER which work in waveform mode
377 \param[in] shrtimer_periph: SHRTIMER0
378 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
379 \param[in] timercfg: Slave_TIMER general behavior configuration struct
380 balanced_mode: SHRTIMER_STXBALANCEDMODE_DISABLED, SHRTIMER_STXBALANCEDMODE_ENABLED
381 fault_enable: SHRTIMER_STXFAULTENABLE_NONE, SHRTIMER_STXFAULTENABLE_FAULT0, SHRTIMER_STXFAULTENABLE_FAULT1, SHRTIMER_STXFAULTENABLE_FAULT2, SHRTIMER_STXFAULTENABLE_FAULT3 ,SHRTIMER_STXFAULTENABLE_FAULT4
382 fault_protect: SHRTIMER_STXFAULT_PROTECT_READWRITE, SHRTIMER_STXFAULT_PROTECT_READONLY
383 deadtime_enable: SHRTIMER_STXDEADTIME_DISABLED, SHRTIMER_STXDEADTIME_ENABLED
384 delayed_idle: SHRTIMER_STXDELAYED_IDLE_DISABLED,SHRTIMER_STXDELAYED_IDLE_CH0_EEV57,SHRTIMER_STXDELAYED_IDLE_CH1_EEV57,SHRTIMER_STXDELAYED_IDLE_BOTH_EEV57,SHRTIMER_STXDELAYED_IDLE_BALANCED_EEV57,
385 SHRTIMER_STXDELAYED_IDLE_CH0_DEEV68,SHRTIMER_STXDELAYED_IDLE_CH1_DEEV68,SHRTIMER_STXDELAYED_IDLE_BOTH_EEV68,SHRTIMER_STXDELAYED_IDLE_BALANCED_EEV68
386 update_source: SHRTIMER_STXUPDATETRIGGER_NONE, SHRTIMER_STXUPDATETRIGGER_MASTER, SHRTIMER_STXUPDATETRIGGER_STx(x=0..4)
387 cnt_reset: SHRTIMER_STXCNT_RESET_NONE, SHRTIMER_STXCNT_RESET_UPDATE, SHRTIMER_STXCNT_RESET_CMP1, SHRTIMER_STXCNT_RESET_CMP3, SHRTIMER_STXCNT_RESET_MASTER_PER, SHRTIMER_STXCNT_RESET_MASTER_CMPy(y=0..3),
388 SHRTIMER_STXCNT_RESET_EEV_y(y=0..9), SHRTIMER_STXCNT_RESET_OTHERx_CMPy(x=0..3, y=0,1,3)
389 reset_update: SHRTIMER_STXUPDATEONRESET_DISABLED, SHRTIMER_STXUPDATEONRESET_ENABLED
390 \param[out] none
391 \retval none
392 */
shrtimer_slavetimer_waveform_config(uint32_t shrtimer_periph,uint32_t timer_id,shrtimer_timercfg_parameter_struct * timercfg)393 void shrtimer_slavetimer_waveform_config(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_timercfg_parameter_struct * timercfg)
394 {
395 uint32_t stxctl0_reg;
396 uint32_t stxfltctl_reg;
397 uint32_t stxchoctl_reg;
398 uint32_t stxcntrst_reg;
399
400 /* get the value of registers */
401 stxctl0_reg = SHRTIMER_STXCTL0(shrtimer_periph, timer_id);
402 stxfltctl_reg = SHRTIMER_STXFLTCTL(shrtimer_periph, timer_id);
403 stxchoctl_reg = SHRTIMER_STXCHOCTL(shrtimer_periph, timer_id);
404 stxcntrst_reg = SHRTIMER_STXCNTRST(shrtimer_periph, timer_id);
405
406 /* set the balanced mode */
407 stxctl0_reg &= ~(SHRTIMER_STXCTL0_BLNMEN);
408 stxctl0_reg |= timercfg->balanced_mode;
409
410 /* update event generated by reset event */
411 stxctl0_reg &= ~(SHRTIMER_STXCTL0_UPRST);
412 stxctl0_reg |= timercfg->reset_update;
413
414 /* set the timer update source */
415 stxctl0_reg &= ~(STX_UPDATESOURCE_MASK);
416 stxctl0_reg |= timercfg->update_source;
417
418 /* enable/disable the fault channel (at Slave_TIMER level) */
419 stxfltctl_reg &= ~(STX_FAULTCH_MASK);
420 stxfltctl_reg |= (timercfg->fault_enable & STX_FAULTCH_MASK);
421
422 /* protect fault enable (at Slave_TIMER level) */
423 stxfltctl_reg &= ~(SHRTIMER_STXFLTCTL_FLTENPROT);
424 stxfltctl_reg |= timercfg->fault_protect;
425
426 /* enable/disable dead time insertion (at Slave_TIMER level) */
427 stxchoctl_reg &= ~(SHRTIMER_STXCHOCTL_DTEN);
428 stxchoctl_reg |= timercfg->deadtime_enable;
429
430 /* enable/disable delayed IDLE (at Slave_TIMER level) */
431 stxchoctl_reg &= ~(SHRTIMER_STXCHOCTL_DLYISCH| SHRTIMER_STXCHOCTL_DLYISMEN);
432 stxchoctl_reg |= timercfg->delayed_idle;
433
434 /* resets Slave_TIMER counter */
435 stxcntrst_reg = timercfg->cnt_reset;
436
437 SHRTIMER_STXCTL0(shrtimer_periph, timer_id) = stxctl0_reg;
438 SHRTIMER_STXFLTCTL(shrtimer_periph, timer_id) = stxfltctl_reg;
439 SHRTIMER_STXCHOCTL(shrtimer_periph, timer_id) = stxchoctl_reg;
440 SHRTIMER_STXCNTRST(shrtimer_periph, timer_id) = stxcntrst_reg;
441 }
442
443
444 /*!
445 \brief initialize compare unit configuration struct with a default value
446 \param[in] cmpcfg: compare unit configuration struct definitions
447 \param[out] none
448 \retval none
449 */
shrtimer_comparecfg_struct_para_init(shrtimer_comparecfg_parameter_struct * comparecfg)450 void shrtimer_comparecfg_struct_para_init(shrtimer_comparecfg_parameter_struct* comparecfg)
451 {
452 comparecfg->compare_value = 0x0000U;
453 comparecfg->delayed_mode = SHRTIMER_DELAYEDMODE_DISABLE;
454 comparecfg->timeout_value = 0x0U;
455 }
456
457 /*!
458 \brief configure the compare unit of a Slave_TIMER which work in waveform mode
459 \param[in] shrtimer_periph: SHRTIMER0
460 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
461 \param[in] comparex: SHRTIMER_COMPAREy(y=0..3)
462 \param[in] cmpcfg: compare unit configuration struct definitions
463 compare_value: min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
464 delayed_mode: SHRTIMER_DELAYEDMODE_DISABLE, SHRTIMER_DELAYEDMODE_NOTIMEOUT, SHRTIMER_DELAYEDMODE_TIMEOUTCMP0, SHRTIMER_DELAYEDMODE_TIMEOUTCMP2
465 timeout_value: 0x0000~((timeout_value + compare_value) < 0xFFFF)
466 \param[out] none
467 \retval none
468 */
shrtimer_slavetimer_waveform_compare_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t comparex,shrtimer_comparecfg_parameter_struct * cmpcfg)469 void shrtimer_slavetimer_waveform_compare_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t comparex, shrtimer_comparecfg_parameter_struct* cmpcfg)
470 {
471 uint32_t stxctl0_reg;
472
473 /* configure the compare unit */
474 switch (comparex)
475 {
476 case SHRTIMER_COMPARE0:
477 {
478 /* set the compare value */
479 SHRTIMER_STXCMP0V(shrtimer_periph, timer_id) = cmpcfg->compare_value;
480 }
481 break;
482
483 case SHRTIMER_COMPARE1:
484 {
485 /* set the compare value */
486 SHRTIMER_STXCMP1V(shrtimer_periph, timer_id) = cmpcfg->compare_value;
487
488 if(SHRTIMER_DELAYEDMODE_DISABLE != cmpcfg->delayed_mode){
489 /* configure delayed mode */
490 stxctl0_reg = SHRTIMER_STXCTL0(shrtimer_periph, timer_id);
491 stxctl0_reg &= ~SHRTIMER_STXCTL0_DELCMP1M;
492 stxctl0_reg |= cmpcfg->delayed_mode;
493 SHRTIMER_STXCTL0(shrtimer_periph, timer_id) = stxctl0_reg;
494
495 /* set the compare value for timeout compare unit */
496 if(SHRTIMER_DELAYEDMODE_TIMEOUTCMP0 == cmpcfg->delayed_mode){
497 SHRTIMER_STXCMP0V(shrtimer_periph, timer_id) = cmpcfg->timeout_value;
498 }else if(SHRTIMER_DELAYEDMODE_TIMEOUTCMP2 == cmpcfg->delayed_mode){
499 SHRTIMER_STXCMP2V(shrtimer_periph, timer_id) = cmpcfg->timeout_value;
500 }else{
501 }
502 }
503 }
504 break;
505
506 case SHRTIMER_COMPARE2:
507 {
508 /* set the compare value */
509 SHRTIMER_STXCMP2V(shrtimer_periph, timer_id) = cmpcfg->compare_value;
510 }
511 break;
512 case SHRTIMER_COMPARE3:
513 {
514 /* set the compare value */
515 SHRTIMER_STXCMP3V(shrtimer_periph, timer_id) = cmpcfg->compare_value;
516
517 if(SHRTIMER_DELAYEDMODE_DISABLE != cmpcfg->delayed_mode){
518 /* configure delayed mode */
519 stxctl0_reg = SHRTIMER_STXCTL0(shrtimer_periph, timer_id);
520 stxctl0_reg &= ~SHRTIMER_STXCTL0_DELCMP3M;
521 stxctl0_reg |= (cmpcfg->delayed_mode << 2);
522 SHRTIMER_STXCTL0(shrtimer_periph, timer_id) = stxctl0_reg;
523
524 /* set the compare value for timeout compare unit */
525 if(SHRTIMER_DELAYEDMODE_TIMEOUTCMP0 == cmpcfg->delayed_mode){
526 SHRTIMER_STXCMP0V(shrtimer_periph, timer_id) = cmpcfg->timeout_value;
527 }else if(SHRTIMER_DELAYEDMODE_TIMEOUTCMP2 == cmpcfg->delayed_mode){
528 SHRTIMER_STXCMP2V(shrtimer_periph, timer_id) = cmpcfg->timeout_value;
529 }else{
530 }
531 }
532 }
533 break;
534
535 default:
536 break;
537 }
538 }
539
540 /*!
541 \brief initialize channel output configuration struct with a default value
542 \param[in] channelcfg: channel output configuration struct definitions
543 \param[out] none
544 \retval none
545 */
shrtimer_channel_outputcfg_struct_para_init(shrtimer_channel_outputcfg_parameter_struct * channelcfg)546 void shrtimer_channel_outputcfg_struct_para_init(shrtimer_channel_outputcfg_parameter_struct * channelcfg)
547 {
548 channelcfg->carrier_mode = SHRTIMER_CHANNEL_CARRIER_DISABLED;
549 channelcfg->deadtime_bunch = SHRTIMER_CHANNEL_BUNCH_ENTRY_REGULAR;
550 channelcfg->fault_state = SHRTIMER_CHANNEL_FAULTSTATE_NONE;
551 channelcfg->idle_bunch = SHRTIMER_CHANNEL_BUNCH_IDLE_DISABLE;
552 channelcfg->idle_state = SHRTIMER_CHANNEL_IDLESTATE_INACTIVE;
553 channelcfg->polarity = SHRTIMER_CHANNEL_POLARITY_HIGH;
554 channelcfg->reset_request = SHRTIMER_CHANNEL_RESET_NONE;
555 channelcfg->set_request = SHRTIMER_CHANNEL_SET_NONE;
556 }
557
558 /*!
559 \brief configure the channel output of a Slave_TIMER work in waveform mode
560 \param[in] shrtimer_periph: SHRTIMER0
561 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
562 \param[in] channel: SHRTIMER_STx_CHy(x=0..4,y=0,1)
563 \param[in] channelcfg: channel output configuration struct definitions
564 polarity: SHRTIMER_CHANNEL_POLARITY_HIGH, SHRTIMER_CHANNEL_POLARITY_LOW
565 set_request: SHRTIMER_CHANNEL_SET_NONE, SHRTIMER_CHANNEL_SET_RSTSYNI, SHRTIMER_CHANNEL_SET_PER, SHRTIMER_CHANNEL_SET_CMPy(y=0..3),
566 SHRTIMER_CHANNEL_SET_MTPER, SHRTIMER_CHANNEL_SET_MTCMPy(y=0..3), SHRTIMER_CHANNEL_SET_STEVy(y=0..8),
567 SHRTIMER_CHANNEL_SET_EXEVy(y=0..9), SHRTIMER_CHANNEL_SET_UPDATE
568 reset_request: SHRTIMER_CHANNEL_RESET_NONE, SHRTIMER_CHANNEL_RESET_RSTSYNI, SHRTIMER_CHANNEL_RESET_PER, SHRTIMER_CHANNEL_RESET_CMPy(y=0..3),
569 SHRTIMER_CHANNEL_RESET_MTPER, SHRTIMER_CHANNEL_RESET_MTCMPy(y=0..3), SHRTIMER_CHANNEL_RESET_STEVy(y=0..8),
570 SHRTIMER_CHANNEL_RESET_EXEVy(y=0..9), SHRTIMER_CHANNEL_RESET_UPDATE
571 idle_bunch: SHRTIMER_CHANNEL_BUNCH_IDLE_DISABLE, SHRTIMER_CHANNEL_BUNCH_IDLE_ENABLE
572 idle_state: SHRTIMER_CHANNEL_IDLESTATE_INACTIVE, SHRTIMER_CHANNEL_IDLESTATE_ACTIVE
573 fault_state: SHRTIMER_CHANNEL_FAULTSTATE_NONE, SHRTIMER_CHANNEL_FAULTSTATE_ACTIVE, SHRTIMER_CHANNEL_FAULTSTATE_INACTIVE, SHRTIMER_CHANNEL_FAULTSTATE_HIGHZ
574 carrier_mode: SHRTIMER_CHANNEL_CARRIER_DISABLED, SHRTIMER_CHANNEL_CARRIER_ENABLED
575 deadtime_bunch: SHRTIMER_CHANNEL_BUNCH_ENTRY_REGULAR, SHRTIMER_CHANNEL_BUNCH_ENTRY_DEADTIME
576 \param[out] none
577 \retval none
578 */
shrtimer_slavetimer_waveform_channel_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t channel,shrtimer_channel_outputcfg_parameter_struct * channelcfg)579 void shrtimer_slavetimer_waveform_channel_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel, shrtimer_channel_outputcfg_parameter_struct * channelcfg)
580 {
581 channel_output_config(shrtimer_periph, timer_id, channel, channelcfg);
582 }
583
584 /*!
585 \brief software generates channel "set request" or "reset request"
586 \param[in] shrtimer_periph: SHRTIMER0
587 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
588 \param[in] channel: SHRTIMER_STx_CHy(x=0..4,y=0,1)
589 \param[in] request: "set request" or "reset request"
590 only one parameter can be selected which is shown as below:
591 \arg SHRTIMER_CHANNEL_SOFTWARE_SET: software event cannot generate request
592 \arg SHRTIMER_CHANNEL_SOFTWARE_RESET: software event can generate request
593 \param[out] none
594 \retval none
595 */
shrtimer_slavetimer_waveform_channel_software_request(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t channel,uint32_t request)596 void shrtimer_slavetimer_waveform_channel_software_request(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel, uint32_t request)
597 {
598 /* configure the output set/reset crossbar */
599 switch (channel)
600 {
601 /* configure the channel 0 output set/reset crossbar */
602 case SHRTIMER_ST0_CH0:
603 case SHRTIMER_ST1_CH0:
604 case SHRTIMER_ST2_CH0:
605 case SHRTIMER_ST3_CH0:
606 case SHRTIMER_ST4_CH0:
607 {
608 if(SHRTIMER_CHANNEL_SOFTWARE_SET == request){
609 /* software generates channel "set request" */
610 SHRTIMER_STXCH0SET(shrtimer_periph, timer_id) |= SHRTIMER_STXCH0SET_CH0SSEV;
611 }else{
612 /* software generates channel "reset request" */
613 SHRTIMER_STXCH0RST(shrtimer_periph, timer_id) |= SHRTIMER_STXCH0RST_CH0RSSEV;
614 }
615 }
616 break;
617 /* configure the channel 1 output set/reset crossbar */
618 case SHRTIMER_ST0_CH1:
619 case SHRTIMER_ST1_CH1:
620 case SHRTIMER_ST2_CH1:
621 case SHRTIMER_ST3_CH1:
622 case SHRTIMER_ST4_CH1:
623 {
624 if(SHRTIMER_CHANNEL_SOFTWARE_SET == request){
625 /* software generates channel "set request" */
626 SHRTIMER_STXCH1SET(shrtimer_periph, timer_id) |= SHRTIMER_STXCH1SET_CH1SSEV;
627 }else{
628 /* software generates channel "reset request" */
629 SHRTIMER_STXCH1RST(shrtimer_periph, timer_id) |= SHRTIMER_STXCH1RST_CH1RSSEV;
630 }
631 }
632 break;
633 default:
634 break;
635 }
636 }
637
638 /*!
639 \brief get Slave_TIMER channel output level
640 \param[in] shrtimer_periph: SHRTIMER0
641 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
642 \param[in] channel: SHRTIMER_STx_CHy(x=0..4,y=0,1)
643 \param[out] none
644 \retval channel output level
645 */
shrtimer_slavetimer_waveform_channel_output_level_get(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t channel)646 uint32_t shrtimer_slavetimer_waveform_channel_output_level_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel)
647 {
648 uint32_t output_level = SHRTIMER_CHANNEL_OUTPUT_INACTIVE;
649
650 switch (channel)
651 {
652 /* get Slave_TIMER channel 0 output level */
653 case SHRTIMER_ST0_CH0:
654 case SHRTIMER_ST1_CH0:
655 case SHRTIMER_ST2_CH0:
656 case SHRTIMER_ST3_CH0:
657 case SHRTIMER_ST4_CH0:
658 {
659 if(RESET != (SHRTIMER_STXINTF(shrtimer_periph, timer_id) & SHRTIMER_STXINTF_CH0F)){
660 output_level = SHRTIMER_CHANNEL_OUTPUT_ACTIVE;
661 }else{
662 output_level = SHRTIMER_CHANNEL_OUTPUT_INACTIVE;
663 }
664 }
665 break;
666 /* get Slave_TIMER channel 1 output level */
667 case SHRTIMER_ST0_CH1:
668 case SHRTIMER_ST1_CH1:
669 case SHRTIMER_ST2_CH1:
670 case SHRTIMER_ST3_CH1:
671 case SHRTIMER_ST4_CH1:
672 {
673 if(RESET != (SHRTIMER_STXINTF(shrtimer_periph, timer_id) & SHRTIMER_STXINTF_CH1F)){
674 output_level = SHRTIMER_CHANNEL_OUTPUT_ACTIVE;
675 }else{
676 output_level = SHRTIMER_CHANNEL_OUTPUT_INACTIVE;
677 }
678 }
679 break;
680 default:
681 break;
682 }
683 return output_level;
684 }
685
686 /*!
687 \brief get Slave_TIMER channel run state
688 \param[in] shrtimer_periph: SHRTIMER0
689 \param[in] channel: SHRTIMER_STx_CHy(x=0..4,y=0,1)
690 \param[out] none
691 \retval channel state
692 */
shrtimer_slavetimer_waveform_channel_state_get(uint32_t shrtimer_periph,uint32_t channel)693 uint32_t shrtimer_slavetimer_waveform_channel_state_get(uint32_t shrtimer_periph, uint32_t channel)
694 {
695 uint32_t enbit = 0U;
696 uint32_t state = SHRTIMER_CHANNEL_STATE_IDLE;
697
698 switch (channel)
699 {
700 /* get Slave_TIMER0 channel 0 run state */
701 case SHRTIMER_ST0_CH0:
702 enbit = SHRTIMER_CHOUTEN_ST0CH0EN;
703 break;
704 /* get Slave_TIMER0 channel 1 run state */
705 case SHRTIMER_ST0_CH1:
706 enbit = SHRTIMER_CHOUTEN_ST0CH1EN;
707 break;
708 /* get Slave_TIMER1 channel 0 run state */
709 case SHRTIMER_ST1_CH0:
710 enbit = SHRTIMER_CHOUTEN_ST1CH0EN;
711 break;
712 /* get Slave_TIMER1 channel 1 run state */
713 case SHRTIMER_ST1_CH1:
714 enbit = SHRTIMER_CHOUTEN_ST1CH1EN;
715 break;
716 /* get Slave_TIMER2 channel 0 run state */
717 case SHRTIMER_ST2_CH0:
718 enbit = SHRTIMER_CHOUTEN_ST2CH0EN;
719 break;
720 /* get Slave_TIMER2 channel 1 run state */
721 case SHRTIMER_ST2_CH1:
722 enbit = SHRTIMER_CHOUTEN_ST2CH1EN;
723 break;
724 /* get Slave_TIMER3 channel 0 run state */
725 case SHRTIMER_ST3_CH0:
726 enbit = SHRTIMER_CHOUTEN_ST3CH0EN;
727 break;
728 /* get Slave_TIMER3 channel 1 run state */
729 case SHRTIMER_ST3_CH1:
730 enbit = SHRTIMER_CHOUTEN_ST3CH1EN;
731 break;
732 /* get Slave_TIMER4 channel 0 run state */
733 case SHRTIMER_ST4_CH0:
734 enbit = SHRTIMER_CHOUTEN_ST4CH0EN;
735 break;
736 /* get Slave_TIMER4 channel 1 run state */
737 case SHRTIMER_ST4_CH1:
738 enbit = SHRTIMER_CHOUTEN_ST4CH1EN;
739 break;
740 default:
741 break;
742 }
743 if ( RESET != (SHRTIMER_CHOUTEN(shrtimer_periph) & enbit)){
744 /* Run state*/
745 state = SHRTIMER_CHANNEL_STATE_RUN;
746 }else{
747 if (RESET != (SHRTIMER_CHOUTDISF(shrtimer_periph) & enbit)){
748 /* Fault state */
749 state = SHRTIMER_CHANNEL_STATE_FAULT;
750 }else{
751 /* Idle state */
752 state = SHRTIMER_CHANNEL_STATE_IDLE;
753 }
754 }
755 return state;
756 }
757
758 /*!
759 \brief initialize dead time configuration struct with a default value
760 \param[in] dtcfg: dead time configuration struct
761 \param[out] none
762 \retval none
763 */
shrtimer_deadtimercfg_struct_para_init(shrtimer_deadtimecfg_parameter_struct * dtcfg)764 void shrtimer_deadtimercfg_struct_para_init(shrtimer_deadtimecfg_parameter_struct * dtcfg)
765 {
766 dtcfg->fallingsign_protect = SHRTIMER_DEADTIME_FALLINGSIGN_PROTECT_DISABLE;
767 dtcfg->falling_protect = SHRTIMER_DEADTIME_FALLING_PROTECT_DISABLE;
768 dtcfg->falling_sign = SHRTIMER_DEADTIME_FALLINGSIGN_POSITIVE;
769 dtcfg->falling_value = 0U;
770 dtcfg->prescaler = SHRTIMER_DEADTIME_PRESCALER_MUL8;
771 dtcfg->risingsign_protect = SHRTIMER_DEADTIME_RISINGSIGN_PROTECT_DISABLE;
772 dtcfg->rising_protect = SHRTIMER_DEADTIME_RISING_PROTECT_DISABLE;
773 dtcfg->rising_sign = SHRTIMER_DEADTIME_RISINGSIGN_POSITIVE;
774 dtcfg->rising_value = 0U;
775 }
776
777 /*!
778 \brief configure the dead time for Slave_TIMER
779 \param[in] shrtimer_periph: SHRTIMER0
780 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
781 \param[in] dtcfg: dead time configuration struct
782 prescaler: SHRTIMER_DEADTIME_PRESCALER_MULy(y=64,32,16,8,4,2), SHRTIMER_DEADTIME_PRESCALER_DIVy(y=1,2,4,8,16)
783 rising_value: 0x0000~0xFFFF
784 rising_sign: SHRTIMER_DEADTIME_RISINGSIGN_POSITIVE, SHRTIMER_DEADTIME_RISINGSIGN_NEGATIVE
785 rising_protect: SHRTIMER_DEADTIME_RISING_PROTECT_DISABLE, SHRTIMER_DEADTIME_RISING_PROTECT_ENABLE
786 risingsign_protect: SHRTIMER_DEADTIME_RISINGSIGN_PROTECT_DISABLE, SHRTIMER_DEADTIME_RISINGSIGN_PROTECT_ENABLE
787 falling_value: 0x0000~0xFFFF
788 falling_sign: SHRTIMER_DEADTIME_FALLINGSIGN_POSITIVE, SHRTIMER_DEADTIME_FALLINGSIGN_NEGATIVE
789 falling_protect: SHRTIMER_DEADTIME_FALLING_PROTECT_DISABLE, SHRTIMER_DEADTIME_FALLING_PROTECT_ENABLE
790 fallingsign_protect: SHRTIMER_DEADTIME_FALLINGSIGN_PROTECT_DISABLE, SHRTIMER_DEADTIME_FALLINGSIGN_PROTECT_ENABLE
791 \param[out] none
792 \retval none
793 */
shrtimer_slavetimer_deadtime_config(uint32_t shrtimer_periph,uint32_t timer_id,shrtimer_deadtimecfg_parameter_struct * dtcfg)794 void shrtimer_slavetimer_deadtime_config(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_deadtimecfg_parameter_struct* dtcfg)
795 {
796 uint32_t dtctl_reg;
797 uint32_t stxactl;
798
799 dtctl_reg = SHRTIMER_STXDTCTL(shrtimer_periph, timer_id);
800 stxactl = SHRTIMER_STXACTL(shrtimer_periph, timer_id);
801
802 /* clear dead time configuration */
803 dtctl_reg &= ~(SHRTIMER_STXDTCTL_DTRCFG8_0 | SHRTIMER_STXDTCTL_DTRS | SHRTIMER_STXDTCTL_DTGCKDIV |
804 SHRTIMER_STXDTCTL_DTRSPROT | SHRTIMER_STXDTCTL_DTRSVPROT | SHRTIMER_STXDTCTL_DTFCFG8_0 |
805 SHRTIMER_STXDTCTL_DTFS | SHRTIMER_STXDTCTL_DTFSPROT | SHRTIMER_STXDTCTL_DTFSVPROT);
806 stxactl &= ~(SHRTIMER_STXACTL_DTRCFG15_9 | SHRTIMER_STXACTL_DTFCFG15_9);
807
808 /* set dead time configuration */
809 dtctl_reg |= (dtcfg->prescaler << 10);
810 dtctl_reg |= ((dtcfg->rising_value) & SHRTIMER_STXDTCTL_DTRCFG8_0);
811 stxactl |= (((dtcfg->rising_value) & (~SHRTIMER_STXDTCTL_DTRCFG8_0)));
812 dtctl_reg |= dtcfg->rising_sign;
813 dtctl_reg |= dtcfg->risingsign_protect;
814 dtctl_reg |= dtcfg->rising_protect;
815 dtctl_reg |= (((dtcfg->falling_value) & SHRTIMER_STXDTCTL_DTRCFG8_0) << 16);
816 stxactl |= ((dtcfg->falling_value) & (~SHRTIMER_STXDTCTL_DTRCFG8_0)) << 16;
817 dtctl_reg |= dtcfg->falling_sign;
818 dtctl_reg |= dtcfg->fallingsign_protect;
819 dtctl_reg |= dtcfg->falling_protect;
820
821 SHRTIMER_STXACTL(shrtimer_periph, timer_id) = stxactl;
822 SHRTIMER_STXDTCTL(shrtimer_periph, timer_id) = dtctl_reg;
823 }
824
825 /*!
826 \brief initialize carrier signal configuration struct with a default value
827 \param[in] carriercfg: carrier signal configuration struct
828 \param[out] none
829 \retval none
830 */
shrtimer_carriersignalcfg_struct_para_init(shrtimer_carriersignalcfg_parameter_struct * carriercfg)831 void shrtimer_carriersignalcfg_struct_para_init(shrtimer_carriersignalcfg_parameter_struct* carriercfg)
832 {
833 carriercfg->duty_cycle = 0U;
834 carriercfg->first_pulse = 0U;
835 carriercfg->period = 0U;
836 }
837
838 /*!
839 \brief configure the carrier signal mode for Slave_TIMER
840 \param[in] shrtimer_periph: SHRTIMER0
841 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
842 \param[in] carriercfg: carrier signal configuration struct
843 period: 0x0~0xF. specifies carrier signal period: (period + 1) * 16 * tSHRTIMER_CK
844 duty_cycle: 0x0~0x7. specifies Carrier signal duty cycle: duty_cycle/8
845 first_pulse: 0x0~0xF. specifies first carrier-signal pulse width: (first_pulse+1) * 16 * tSHRTIMER_CK
846 \param[out] none
847 \retval none
848 */
shrtimer_slavetimer_carriersignal_config(uint32_t shrtimer_periph,uint32_t timer_id,shrtimer_carriersignalcfg_parameter_struct * carriercfg)849 void shrtimer_slavetimer_carriersignal_config(uint32_t shrtimer_periph, uint32_t timer_id, shrtimer_carriersignalcfg_parameter_struct* carriercfg)
850 {
851 uint32_t csctl_reg;
852
853 csctl_reg = SHRTIMER_STXCSCTL(shrtimer_periph, timer_id);
854
855 /* clear timer chopper mode configuration */
856 csctl_reg &= ~(SHRTIMER_STXCSCTL_CSPRD | SHRTIMER_STXCSCTL_CSDTY | SHRTIMER_STXCSCTL_CSFSTPW);
857
858 /* set timer chopper mode configuration */
859 csctl_reg |= carriercfg->period;
860 csctl_reg |= (carriercfg->duty_cycle << 4);
861 csctl_reg |= (carriercfg->first_pulse << 7);
862
863 SHRTIMER_STXCSCTL(shrtimer_periph, timer_id) = csctl_reg;
864 }
865
866 /*!
867 \brief enable a output channel
868 \param[in] shrtimer_periph: SHRTIMER0
869 \param[in] chid: specify the channel to configure
870 only one can be selected which is shown as below:
871 \arg SHRTIMER_ST0_CH0: ST0CH0_O output channel
872 \arg SHRTIMER_ST0_CH1: ST0CH1_O output channel
873 \arg SHRTIMER_ST1_CH0: ST1CH0_O output channel
874 \arg SHRTIMER_ST1_CH1: ST1CH1_O output channel
875 \arg SHRTIMER_ST2_CH0: ST2CH0_O output channel
876 \arg SHRTIMER_ST2_CH1: ST2CH1_O output channel
877 \arg SHRTIMER_ST3_CH0: ST3CH0_O output channel
878 \arg SHRTIMER_ST3_CH1: ST3CH1_O output channel
879 \arg SHRTIMER_ST4_CH0: ST4CH0_O output channel
880 \arg SHRTIMER_ST4_CH1: ST4CH1_O output channel
881 \param[out] none
882 \retval none
883 */
shrtimer_output_channel_enable(uint32_t shrtimer_periph,uint32_t chid)884 void shrtimer_output_channel_enable(uint32_t shrtimer_periph, uint32_t chid)
885 {
886 SHRTIMER_CHOUTEN(shrtimer_periph) = chid;
887 }
888
889 /*!
890 \brief disable a output channel
891 \param[in] shrtimer_periph: SHRTIMER0
892 \param[in] chid: specify the channel to configure
893 only one can be selected which is shown as below:
894 \arg SHRTIMER_ST0_CH0: ST0CH0_O output channel
895 \arg SHRTIMER_ST0_CH1: ST0CH1_O output channel
896 \arg SHRTIMER_ST1_CH0: ST1CH0_O output channel
897 \arg SHRTIMER_ST1_CH1: ST1CH1_O output channel
898 \arg SHRTIMER_ST2_CH0: ST2CH0_O output channel
899 \arg SHRTIMER_ST2_CH1: ST2CH1_O output channel
900 \arg SHRTIMER_ST3_CH0: ST3CH0_O output channel
901 \arg SHRTIMER_ST3_CH1: ST3CH1_O output channel
902 \arg SHRTIMER_ST4_CH0: ST4CH0_O output channel
903 \arg SHRTIMER_ST4_CH1: ST4CH1_O output channel
904 \param[out] none
905 \retval none
906 */
shrtimer_output_channel_disable(uint32_t shrtimer_periph,uint32_t chid)907 void shrtimer_output_channel_disable(uint32_t shrtimer_periph, uint32_t chid)
908 {
909 SHRTIMER_CHOUTDIS(shrtimer_periph) = chid;
910 }
911
912 /*!
913 \brief configure the compare value in Slave_TIMER
914 \param[in] shrtimer_periph: SHRTIMER0
915 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
916 \param[in] comparex: SHRTIMER_COMPAREy(y=0..3), SHRTIMER_COMPARE0_COMPOSITE
917 \param[in] cmpvalue: min value: 3 tSHRTIMER_CK clock, max value: 0xFFFF �C (1 tSHRTIMER_CK)
918 \param[out] none
919 \retval none
920 */
shrtimer_slavetimer_compare_value_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t comparex,uint32_t cmpvalue)921 void shrtimer_slavetimer_compare_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t comparex, uint32_t cmpvalue)
922 {
923 /* configure the compare unit */
924 switch (comparex)
925 {
926 case SHRTIMER_COMPARE0:
927 {
928 /* set the compare 0 value */
929 SHRTIMER_STXCMP0V(shrtimer_periph, timer_id) = cmpvalue;
930 }
931 break;
932 case SHRTIMER_COMPARE1:
933 {
934 /* set the compare 1 value */
935 SHRTIMER_STXCMP1V(shrtimer_periph, timer_id) = cmpvalue;
936 }
937 break;
938 case SHRTIMER_COMPARE2:
939 {
940 /* set the compare 2 value */
941 SHRTIMER_STXCMP2V(shrtimer_periph, timer_id) = cmpvalue;
942 }
943 break;
944 case SHRTIMER_COMPARE3:
945 {
946 /* set the compare 3 value */
947 SHRTIMER_STXCMP3V(shrtimer_periph, timer_id) = cmpvalue;
948 }
949 break;
950 case SHRTIMER_COMPARE0_COMPOSITE:
951 {
952 /* set the compare 0 composite value */
953 SHRTIMER_STXCMP0CP(shrtimer_periph, timer_id) = cmpvalue;
954 }
955 break;
956 default:
957 break;
958 }
959 }
960
961 /*!
962 \brief get the compare value in Slave_TIMER
963 \param[in] shrtimer_periph: SHRTIMER0
964 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
965 \param[in] comparex: SHRTIMER_COMPAREy(y=0..3), SHRTIMER_COMPARE0_COMPOSITE
966 \param[out] none
967 \retval the compare value
968 */
shrtimer_slavetimer_compare_value_get(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t comparex)969 uint32_t shrtimer_slavetimer_compare_value_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t comparex)
970 {
971 uint32_t cmpval = 0U;
972 /* configure the compare unit */
973 switch (comparex)
974 {
975 case SHRTIMER_COMPARE0:
976 {
977 /* get the compare 0 value */
978 cmpval = SHRTIMER_STXCMP0V(shrtimer_periph, timer_id);
979 }
980 break;
981 case SHRTIMER_COMPARE1:
982 {
983 /* get the compare 1 value */
984 cmpval = SHRTIMER_STXCMP1V(shrtimer_periph, timer_id);
985 }
986 break;
987 case SHRTIMER_COMPARE2:
988 {
989 /* get the compare 2 value */
990 cmpval = SHRTIMER_STXCMP2V(shrtimer_periph, timer_id);
991 }
992 break;
993 case SHRTIMER_COMPARE3:
994 {
995 /* get the compare 3 value */
996 cmpval = SHRTIMER_STXCMP3V(shrtimer_periph, timer_id);
997 }
998 break;
999 case SHRTIMER_COMPARE0_COMPOSITE:
1000 {
1001 /* get the compare 0 composite value */
1002 cmpval = SHRTIMER_STXCMP0CP(shrtimer_periph, timer_id);
1003 }
1004 break;
1005 default:
1006 break;
1007 }
1008 return cmpval;
1009 }
1010
1011 /*!
1012 \brief configure the compare value in Master_TIMER
1013 \param[in] shrtimer_periph: SHRTIMER0
1014 \param[in] comparex: SHRTIMER_COMPAREy(y=0..3)
1015 \param[in] cmpvalue: min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
1016 \param[out] none
1017 \retval none
1018 */
shrtimer_mastertimer_compare_value_config(uint32_t shrtimer_periph,uint32_t comparex,uint32_t cmpvalue)1019 void shrtimer_mastertimer_compare_value_config(uint32_t shrtimer_periph, uint32_t comparex, uint32_t cmpvalue)
1020 {
1021 /* configure the compare unit */
1022 switch (comparex)
1023 {
1024 case SHRTIMER_COMPARE0:
1025 {
1026 /* set the compare 0 value */
1027 SHRTIMER_MTCMP0V(shrtimer_periph) = cmpvalue;
1028 }
1029 break;
1030 case SHRTIMER_COMPARE1:
1031 {
1032 /* set the compare 1 value */
1033 SHRTIMER_MTCMP1V(shrtimer_periph) = cmpvalue;
1034 }
1035 break;
1036 case SHRTIMER_COMPARE2:
1037 {
1038 /* set the compare 2 value */
1039 SHRTIMER_MTCMP2V(shrtimer_periph) = cmpvalue;
1040 }
1041 break;
1042 case SHRTIMER_COMPARE3:
1043 {
1044 /* set the compare 3 value */
1045 SHRTIMER_MTCMP3V(shrtimer_periph) = cmpvalue;
1046 }
1047 break;
1048 default:
1049 break;
1050 }
1051 }
1052
1053 /*!
1054 \brief get the compare value in Master_TIMER
1055 \param[in] shrtimer_periph: SHRTIMER0
1056 \param[in] comparex: SHRTIMER_COMPAREy(y=0..3)
1057 \param[out] none
1058 \retval the compare value
1059 */
shrtimer_mastertimer_compare_value_get(uint32_t shrtimer_periph,uint32_t comparex)1060 uint32_t shrtimer_mastertimer_compare_value_get(uint32_t shrtimer_periph, uint32_t comparex)
1061 {
1062 uint32_t cmpval = 0U;
1063 switch (comparex)
1064 {
1065 case SHRTIMER_COMPARE0:
1066 {
1067 /* get the compare 0 value */
1068 cmpval = SHRTIMER_MTCMP0V(shrtimer_periph);
1069 }
1070 break;
1071 case SHRTIMER_COMPARE1:
1072 {
1073 /* get the compare 1 value */
1074 cmpval = SHRTIMER_MTCMP1V(shrtimer_periph);
1075 }
1076 break;
1077 case SHRTIMER_COMPARE2:
1078 {
1079 /* get the compare 2 value */
1080 cmpval = SHRTIMER_MTCMP2V(shrtimer_periph);
1081 }
1082 break;
1083 case SHRTIMER_COMPARE3:
1084 {
1085 /* get the compare 3 value */
1086 cmpval = SHRTIMER_MTCMP3V(shrtimer_periph);
1087 }
1088 break;
1089 default:
1090 break;
1091 }
1092 return cmpval;
1093 }
1094
1095 /*!
1096 \brief configure the counter value in Master_TIMER and Slave_TIMER
1097 \param[in] shrtimer_periph: SHRTIMER0
1098 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1099 \param[in] cntvalue: min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
1100 \param[out] none
1101 \retval none
1102 */
shrtimer_timers_counter_value_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t cntvalue)1103 void shrtimer_timers_counter_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t cntvalue)
1104 {
1105 /* configure the counter */
1106 switch (timer_id)
1107 {
1108 case SHRTIMER_MASTER_TIMER:
1109 {
1110 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_MTCEN)){
1111 /* set the Master_TIMER counter value */
1112 SHRTIMER_MTCNT(shrtimer_periph) = cntvalue;
1113 }
1114 }
1115 break;
1116 case SHRTIMER_SLAVE_TIMER0:
1117 {
1118 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST0CEN)){
1119 /* set the Slave_TIMER0 compare value */
1120 SHRTIMER_STXCNT(shrtimer_periph, timer_id) = cntvalue;
1121 }
1122 }
1123 break;
1124 case SHRTIMER_SLAVE_TIMER1:
1125 {
1126 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST1CEN)){
1127 /* set the Slave_TIMER1 compare value */
1128 SHRTIMER_STXCNT(shrtimer_periph, timer_id) = cntvalue;
1129 }
1130 }
1131 break;
1132 case SHRTIMER_SLAVE_TIMER2:
1133 {
1134 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST2CEN)){
1135 /* set the Slave_TIMER2 compare value */
1136 SHRTIMER_STXCNT(shrtimer_periph, timer_id) = cntvalue;
1137 }
1138 }
1139 break;
1140 case SHRTIMER_SLAVE_TIMER3:
1141 {
1142 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST3CEN)){
1143 /* set the Slave_TIMER3 compare value */
1144 SHRTIMER_STXCNT(shrtimer_periph, timer_id) = cntvalue;
1145 }
1146 }
1147 break;
1148 case SHRTIMER_SLAVE_TIMER4:
1149 {
1150 if(RESET == (SHRTIMER_MTCTL0(shrtimer_periph) & SHRTIMER_MTCTL0_ST4CEN)){
1151 /* set the Slave_TIMER4 counter value */
1152 SHRTIMER_STXCNT(shrtimer_periph, timer_id) = cntvalue;
1153 }
1154 }
1155 break;
1156 default:
1157 break;
1158 }
1159 }
1160
1161 /*!
1162 \brief get the counter value in Master_TIMER and Slave_TIMER
1163 \param[in] shrtimer_periph: SHRTIMER0
1164 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1165 \param[out] none
1166 \retval the counter value
1167 */
shrtimer_timers_counter_value_get(uint32_t shrtimer_periph,uint32_t timer_id)1168 uint32_t shrtimer_timers_counter_value_get(uint32_t shrtimer_periph, uint32_t timer_id)
1169 {
1170 uint32_t cunval = 0U;
1171
1172 switch (timer_id)
1173 {
1174 case SHRTIMER_MASTER_TIMER:
1175 {
1176 /* get the Master_TIMER counter value */
1177 cunval = SHRTIMER_MTCNT(shrtimer_periph);
1178 }
1179 break;
1180 case SHRTIMER_SLAVE_TIMER0:
1181 case SHRTIMER_SLAVE_TIMER1:
1182 case SHRTIMER_SLAVE_TIMER2:
1183 case SHRTIMER_SLAVE_TIMER3:
1184 case SHRTIMER_SLAVE_TIMER4:
1185 {
1186 /* get the Slave_TIMER counter value */
1187 cunval = SHRTIMER_STXCNT(shrtimer_periph, timer_id);
1188 }
1189 break;
1190 default:
1191 break;
1192 }
1193 return cunval;
1194 }
1195
1196 /*!
1197 \brief configure the counter auto reload value in Master_TIMER and Slave_TIMER
1198 \param[in] shrtimer_periph: SHRTIMER0
1199 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1200 \param[in] carlvalue: min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
1201 \param[out] none
1202 \retval none
1203 */
shrtimer_timers_autoreload_value_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t carlvalue)1204 void shrtimer_timers_autoreload_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t carlvalue)
1205 {
1206 /* configure the counter auto reload value */
1207 switch (timer_id)
1208 {
1209 case SHRTIMER_MASTER_TIMER:
1210 {
1211 /* set the Master_TIMER counter value */
1212 SHRTIMER_MTCAR(shrtimer_periph) = carlvalue;
1213 }
1214 break;
1215 case SHRTIMER_SLAVE_TIMER0:
1216 case SHRTIMER_SLAVE_TIMER1:
1217 case SHRTIMER_SLAVE_TIMER2:
1218 case SHRTIMER_SLAVE_TIMER3:
1219 case SHRTIMER_SLAVE_TIMER4:
1220 {
1221 /* set the Slave_TIMER compare value */
1222 SHRTIMER_STXCAR(shrtimer_periph, timer_id) = carlvalue;
1223 }
1224 break;
1225 default:
1226 break;
1227 }
1228 }
1229 /*!
1230 \brief get the counter auto reload value in Master_TIMER and Slave_TIMER
1231 \param[in] shrtimer_periph: SHRTIMER0
1232 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1233 \param[out] none
1234 \retval the counter auto reload value
1235 */
shrtimer_timers_autoreload_value_get(uint32_t shrtimer_periph,uint32_t timer_id)1236 uint32_t shrtimer_timers_autoreload_value_get(uint32_t shrtimer_periph, uint32_t timer_id)
1237 {
1238 uint32_t cralval = 0U;
1239
1240 switch (timer_id)
1241 {
1242 case SHRTIMER_MASTER_TIMER:
1243 {
1244 /* get the Master_TIMER counter auto reload value value */
1245 cralval = SHRTIMER_MTCAR(shrtimer_periph);
1246 }
1247 break;
1248 case SHRTIMER_SLAVE_TIMER0:
1249 case SHRTIMER_SLAVE_TIMER1:
1250 case SHRTIMER_SLAVE_TIMER2:
1251 case SHRTIMER_SLAVE_TIMER3:
1252 case SHRTIMER_SLAVE_TIMER4:
1253 {
1254 /* get the Slave_TIMER counter auto reload value value */
1255 cralval = SHRTIMER_STXCAR(shrtimer_periph, timer_id);
1256 }
1257 break;
1258 default:
1259 break;
1260 }
1261 return cralval;
1262 }
1263
1264 /*!
1265 \brief configure the counter repetition value in Master_TIMER and Slave_TIMER
1266 \param[in] shrtimer_periph: SHRTIMER0
1267 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1268 \param[in] replvalue: 0~255
1269 \param[out] none
1270 \retval none
1271 */
shrtimer_timers_repetition_value_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t replvalue)1272 void shrtimer_timers_repetition_value_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t replvalue)
1273 {
1274 /* configure the counter repetition value */
1275 switch (timer_id)
1276 {
1277 case SHRTIMER_MASTER_TIMER:
1278 {
1279 /* set the Master_TIMER repetition value */
1280 SHRTIMER_MTCREP(shrtimer_periph) = replvalue;
1281 }
1282 break;
1283 case SHRTIMER_SLAVE_TIMER0:
1284 case SHRTIMER_SLAVE_TIMER1:
1285 case SHRTIMER_SLAVE_TIMER2:
1286 case SHRTIMER_SLAVE_TIMER3:
1287 case SHRTIMER_SLAVE_TIMER4:
1288 {
1289 /* set the Slave_TIMER repetition value */
1290 SHRTIMER_STXCREP(shrtimer_periph, timer_id) = replvalue;
1291 }
1292 break;
1293 default:
1294 break;
1295 }
1296 }
1297
1298 /*!
1299 \brief get the counter repetition value in Master_TIMER and Slave_TIMER
1300 \param[in] shrtimer_periph: SHRTIMER0
1301 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1302 \param[out] none
1303 \retval the counter repetition value
1304 */
shrtimer_timers_repetition_value_get(uint32_t shrtimer_periph,uint32_t timer_id)1305 uint32_t shrtimer_timers_repetition_value_get(uint32_t shrtimer_periph, uint32_t timer_id)
1306 {
1307 uint32_t repval = 0U;
1308
1309 switch (timer_id)
1310 {
1311 case SHRTIMER_MASTER_TIMER:
1312 {
1313 /* get the Master_TIMER counter repetition value value */
1314 repval = SHRTIMER_MTCREP(shrtimer_periph);
1315 }
1316 break;
1317 case SHRTIMER_SLAVE_TIMER0:
1318 case SHRTIMER_SLAVE_TIMER1:
1319 case SHRTIMER_SLAVE_TIMER2:
1320 case SHRTIMER_SLAVE_TIMER3:
1321 case SHRTIMER_SLAVE_TIMER4:
1322 {
1323 /* get the Slave_TIMER counter repetition value value */
1324 repval = SHRTIMER_STXCREP(shrtimer_periph, timer_id);
1325 }
1326 break;
1327 default:
1328 break;
1329 }
1330 return repval;
1331 }
1332
1333 /*!
1334 \brief initialize external event filtering for Slave_TIMER configuration struct with a default value
1335 \param[in] exevfilter: external event filtering for Slave_TIMER struct definitions
1336 \param[out] none
1337 \retval none
1338 */
shrtimer_exevfilter_struct_para_init(shrtimer_exevfilter_parameter_struct * exevfilter)1339 void shrtimer_exevfilter_struct_para_init(shrtimer_exevfilter_parameter_struct * exevfilter)
1340 {
1341 exevfilter->filter_mode = SHRTIMER_EXEVFILTER_DISABLE;
1342 exevfilter->memorized = SHRTIMER_EXEVMEMORIZED_DISABLE;
1343 }
1344
1345 /*!
1346 \brief configure the external event filtering for Slave_TIMER (blanking, windowing)
1347 \param[in] shrtimer_periph: SHRTIMER0
1348 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
1349 \param[in] event_id: SHRTIMER_EXEVENT_NONE, SHRTIMER_EXEVENT_y(y=0..9)
1350 \param[in] exevfilter: external event filtering for Slave_TIMER struct definitions
1351 filter_mode: SHRTIMER_EXEVFILTER_DISABLE, SHRTIMER_EXEVFILTER_BLANKINGCMPy(y=0..3), SHRTIMER_EXEVFILTER_BLANKINGSRCy(y=0..7), SHRTIMER_EXEVFILTER_WINDOWINGCMPy(y=1,2), SHRTIMER_EXEVFILTER_WINDOWINGSRC
1352 memorized: SHRTIMER_EXEVMEMORIZED_DISABLE, SHRTIMER_EXEVMEMORIZED_ENABLE
1353 \param[out] none
1354 \retval none
1355 */
shrtimer_slavetimer_exevent_filtering_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t event_id,shrtimer_exevfilter_parameter_struct * exevfilter)1356 void shrtimer_slavetimer_exevent_filtering_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t event_id, shrtimer_exevfilter_parameter_struct *exevfilter)
1357 {
1358 uint32_t exevfcfg_reg;
1359
1360 switch (event_id)
1361 {
1362 /* reset external event filtering */
1363 case SHRTIMER_EXEVENT_NONE:
1364 {
1365 SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id) = 0U;
1366 SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id) = 0U;
1367 }
1368 break;
1369 /* configure external event 0 filtering */
1370 case SHRTIMER_EXEVENT_0:
1371 {
1372 exevfcfg_reg = SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id);
1373 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG0_EXEV0FM | SHRTIMER_STXEXEVFCFG0_EXEV0MEEN);
1374 exevfcfg_reg |= (exevfilter->filter_mode | exevfilter->memorized);
1375 SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id) = exevfcfg_reg;
1376 }
1377 break;
1378 /* configure external event 1 filtering */
1379 case SHRTIMER_EXEVENT_1:
1380 {
1381 exevfcfg_reg = SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id);
1382 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG0_EXEV1FM | SHRTIMER_STXEXEVFCFG0_EXEV1MEEN);
1383 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 6);
1384 SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id) = exevfcfg_reg;
1385 }
1386 break;
1387 /* configure external event 2 filtering */
1388 case SHRTIMER_EXEVENT_2:
1389 {
1390 exevfcfg_reg = SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id);
1391 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG0_EXEV2FM | SHRTIMER_STXEXEVFCFG0_EXEV2MEEN);
1392 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 12);
1393 SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id) = exevfcfg_reg;
1394 }
1395 break;
1396 /* configure external event 3 filtering */
1397 case SHRTIMER_EXEVENT_3:
1398 {
1399 exevfcfg_reg = SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id);
1400 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG0_EXEV3FM | SHRTIMER_STXEXEVFCFG0_EXEV3MEEN);
1401 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 18);
1402 SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id) = exevfcfg_reg;
1403 }
1404 break;
1405 /* configure external event 4 filtering */
1406 case SHRTIMER_EXEVENT_4:
1407 {
1408 exevfcfg_reg = SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id);
1409 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG0_EXEV4FM | SHRTIMER_STXEXEVFCFG0_EXEV4MEEN);
1410 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 24);
1411 SHRTIMER_STXEXEVFCFG0(shrtimer_periph, timer_id) = exevfcfg_reg;
1412 }
1413 break;
1414 /* configure external event 5 filtering */
1415 case SHRTIMER_EXEVENT_5:
1416 {
1417 exevfcfg_reg = SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id);
1418 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG1_EXEV5FM | SHRTIMER_STXEXEVFCFG1_EXEV5MEEN);
1419 exevfcfg_reg |= (exevfilter->filter_mode | exevfilter->memorized);
1420 SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id) = exevfcfg_reg;
1421 }
1422 break;
1423 /* configure external event 6 filtering */
1424 case SHRTIMER_EXEVENT_6:
1425 {
1426 exevfcfg_reg = SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id);
1427 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG1_EXEV6FM | SHRTIMER_STXEXEVFCFG1_EXEV6MEEN);
1428 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 6);
1429 SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id) = exevfcfg_reg;
1430 }
1431 break;
1432 /* configure external event 7 filtering */
1433 case SHRTIMER_EXEVENT_7:
1434 {
1435 exevfcfg_reg = SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id);
1436 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG1_EXEV7FM | SHRTIMER_STXEXEVFCFG1_EXEV7MEEN);
1437 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 12);
1438 SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id) = exevfcfg_reg;
1439 }
1440 break;
1441 /* configure external event 8 filtering */
1442 case SHRTIMER_EXEVENT_8:
1443 {
1444 exevfcfg_reg = SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id);
1445 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG1_EXEV8FM | SHRTIMER_STXEXEVFCFG1_EXEV8MEEN);
1446 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 18);
1447 SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id) = exevfcfg_reg;
1448 }
1449 break;
1450 /* configure external event 9 filtering */
1451 case SHRTIMER_EXEVENT_9:
1452 {
1453 exevfcfg_reg = SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id);
1454 exevfcfg_reg &= ~(SHRTIMER_STXEXEVFCFG1_EXEV9FM | SHRTIMER_STXEXEVFCFG1_EXEV9MEEN);
1455 exevfcfg_reg |= ((exevfilter->filter_mode | exevfilter->memorized) << 24);
1456 SHRTIMER_STXEXEVFCFG1(shrtimer_periph, timer_id) = exevfcfg_reg;
1457 }
1458 break;
1459 default:
1460 break;
1461 }
1462 }
1463
1464 /*!
1465 \brief initialize external event configuration struct with a default value
1466 \param[in] exevcfg: external event configuration struct
1467 \param[out] none
1468 \retval none
1469 */
shrtimer_exeventcfg_struct_para_init(shrtimer_exeventcfg_parameter_struct * exevcfg)1470 void shrtimer_exeventcfg_struct_para_init(shrtimer_exeventcfg_parameter_struct * exevcfg)
1471 {
1472 exevcfg->digital_filter = 0U;
1473 exevcfg->edge = SHRTIMER_EXEV_EDGE_LEVEL;
1474 exevcfg->polarity = SHRTIMER_EXEV_POLARITY_HIGH;
1475 exevcfg->source = SHRTIMER_EXEV_SRC0;
1476 }
1477
1478 /*!
1479 \brief configure the an external event
1480 \param[in] shrtimer_periph: SHRTIMER0
1481 \param[in] event_id: SHRTIMER_EXEVENT_NONE, SHRTIMER_EXEVENT_y(y=0..9)
1482 \param[in] exevcfg: external event configuration struct
1483 source: SHRTIMER_EXEV_SRCy(y=0..3)
1484 polarity: SHRTIMER_EXEV_POLARITY_HIGH, SHRTIMER_EXEV_POLARITY_LOW
1485 edge: SHRTIMER_EXEV_EDGE_LEVEL, SHRTIMER_EXEV_EDGE_RISING, SHRTIMER_EXEV_EDGE_FALLING, SHRTIMER_EXEV_EDGE_BOTH
1486 digital_filter: 0x0~0xF
1487 \param[out] none
1488 \retval none
1489 */
shrtimer_exevent_config(uint32_t shrtimer_periph,uint32_t event_id,shrtimer_exeventcfg_parameter_struct * exevcfg)1490 void shrtimer_exevent_config(uint32_t shrtimer_periph, uint32_t event_id, shrtimer_exeventcfg_parameter_struct* exevcfg)
1491 {
1492 /* configure the an external event channel */
1493 external_event_config(shrtimer_periph, event_id, exevcfg);
1494 }
1495
1496 /*!
1497 \brief configure external event digital filter clock division
1498 \param[in] shrtimer_periph: SHRTIMER0
1499 \param[in] prescaler: clock division value
1500 only one parameter can be selected which is shown as below:
1501 \arg SHRTIMER_EXEV_PRESCALER_DIV1: fSHRTIMER_EXEVFCK = fSHRTIMER_CK
1502 \arg SHRTIMER_EXEV_PRESCALER_DIV2: fSHRTIMER_EXEVFCK = fSHRTIMER_CK / 2
1503 \arg SHRTIMER_EXEV_PRESCALER_DIV4: fSHRTIMER_EXEVFCK = fSHRTIMER_CK / 4
1504 \arg SHRTIMER_EXEV_PRESCALER_DIV8: fSHRTIMER_EXEVFCK = fSHRTIMER_CK / 8
1505 \param[out] none
1506 \retval none
1507 */
shrtimer_exevent_prescaler(uint32_t shrtimer_periph,uint32_t prescaler)1508 void shrtimer_exevent_prescaler(uint32_t shrtimer_periph, uint32_t prescaler)
1509 {
1510 uint32_t exevdfctl_reg;
1511
1512 /* set the external event digital filter clock division */
1513 exevdfctl_reg = SHRTIMER_EXEVDFCTL(shrtimer_periph);
1514 exevdfctl_reg &= ~(SHRTIMER_EXEVDFCTL_EXEVFDIV);
1515 exevdfctl_reg |= prescaler;
1516
1517 SHRTIMER_EXEVDFCTL(shrtimer_periph) = exevdfctl_reg;
1518 }
1519
1520 /*!
1521 \brief initialize synchronization configuration struct with a default value
1522 \param[in] synccfg: synchronization configuration struct
1523 \param[out] none
1524 \retval none
1525 */
shrtimer_synccfg_struct_para_init(shrtimer_synccfg_parameter_struct * synccfg)1526 void shrtimer_synccfg_struct_para_init(shrtimer_synccfg_parameter_struct* synccfg)
1527 {
1528 synccfg->input_source = SHRTIMER_SYNCINPUTSOURCE_DISABLE;
1529 synccfg->output_polarity = SHRTIMER_SYNCOUTPUTPOLARITY_DISABLE;
1530 synccfg->output_source = SHRTIMER_SYNCOUTPUTSOURCE_MTSTART;
1531 }
1532
1533 /*!
1534 \brief configure the synchronization input/output of the SHRTIMER
1535 \param[in] shrtimer_periph: SHRTIMER0
1536 \param[in] synccfg: synchronization configuration struct
1537 input_source: SHRTIMER_SYNCINPUTSOURCE_DISABLE, SHRTIMER_SYNCINPUTSOURCE_INTERNAL, SHRTIMER_SYNCINPUTSOURCE_EXTERNAL
1538 output_source: SHRTIMER_SYNCOUTPUTSOURCE_MTSTART, SHRTIMER_SYNCOUTPUTSOURCE_MTCMP0, SHRTIMER_SYNCOUTPUTSOURCE_ST0START, SHRTIMER_SYNCOUTPUTSOURCE_ST0CMP0
1539 output_polarity: SHRTIMER_SYNCOUTPUTPOLARITY_DISABLE, SHRTIMER_SYNCOUTPUTPOLARITY_POSITIVE, SHRTIMER_SYNCOUTPUTPOLARITY_NEGATIVE
1540 \param[out] none
1541 \retval none
1542 */
shrtimer_synchronization_config(uint32_t shrtimer_periph,shrtimer_synccfg_parameter_struct * synccfg)1543 void shrtimer_synchronization_config(uint32_t shrtimer_periph, shrtimer_synccfg_parameter_struct* synccfg)
1544 {
1545 uint32_t mtctl0_reg;
1546
1547 mtctl0_reg = SHRTIMER_MTCTL0(shrtimer_periph);
1548
1549 /* set the synchronization input source */
1550 mtctl0_reg &= ~(SHRTIMER_MTCTL0_SYNISRC);
1551 mtctl0_reg |= synccfg->input_source;
1552
1553 /* set the event to be sent on the synchronization output */
1554 mtctl0_reg &= ~(SHRTIMER_MTCTL0_SYNOSRC);
1555 mtctl0_reg |= synccfg->output_source;
1556
1557 /* set the polarity of the synchronization output */
1558 mtctl0_reg &= ~(SHRTIMER_MTCTL0_SYNOPLS);
1559 mtctl0_reg |= synccfg->output_polarity;
1560
1561 SHRTIMER_MTCTL0(shrtimer_periph) = mtctl0_reg;
1562 }
1563
1564 /*!
1565 \brief initialize fault input configuration struct with a default value
1566 \param[in] faultcfg: fault input configuration struct
1567 \param[out] none
1568 \retval none
1569 */
shrtimer_faultcfg_struct_para_init(shrtimer_faultcfg_parameter_struct * faultcfg)1570 void shrtimer_faultcfg_struct_para_init(shrtimer_faultcfg_parameter_struct * faultcfg)
1571 {
1572 faultcfg->filter = 0x0U;
1573 faultcfg->polarity = SHRTIMER_FAULT_POLARITY_LOW;
1574 faultcfg->protect = SHRTIMER_FAULT_PROTECT_DISABLE;
1575 faultcfg->source = SHRTIMER_FAULT_SOURCE_PIN;
1576 faultcfg->control = SHRTIMER_FAULT_CHANNEL_DISABLE;
1577 }
1578
1579 /*!
1580 \brief configure the fault input
1581 \param[in] shrtimer_periph: SHRTIMER0
1582 \param[in] fault_id: SHRTIMER_FAULT_y(y=0..4)
1583 \param[in] faultcfg: fault input configuration struct
1584 source: SHRTIMER_FAULT_SOURCE_PIN, SHRTIMER_FAULT_SOURCE_INTERNAL
1585 polarity: SHRTIMER_FAULT_POLARITY_LOW, SHRTIMER_FAULT_POLARITY_HIGH
1586 control: SHRTIMER_FAULT_CHANNEL_DISABLE, SHRTIMER_FAULT_CHANNEL_ENABLE
1587 filter: 0x0~0xF
1588 protect: SHRTIMER_FAULT_PROTECT_DISABLE, SHRTIMER_FAULT_PROTECT_ENABLE
1589 \param[out] none
1590 \retval none
1591 */
shrtimer_fault_config(uint32_t shrtimer_periph,uint32_t fault_id,shrtimer_faultcfg_parameter_struct * faultcfg)1592 void shrtimer_fault_config(uint32_t shrtimer_periph, uint32_t fault_id, shrtimer_faultcfg_parameter_struct* faultcfg)
1593 {
1594 uint32_t fltincfg0;
1595 uint32_t fltincfg1;
1596
1597 fltincfg0 = SHRTIMER_FLTINCFG0(shrtimer_periph);
1598 fltincfg1 = SHRTIMER_FLTINCFG1(shrtimer_periph);
1599
1600 switch (fault_id)
1601 {
1602 case SHRTIMER_FAULT_0:
1603 {
1604 /* configure fault input 0 */
1605 fltincfg0 &= ~( SHRTIMER_FLTINCFG0_FLT0INP | SHRTIMER_FLTINCFG0_FLT0INSRC | SHRTIMER_FLTINCFG0_FLT0INFC | SHRTIMER_FLTINCFG0_FLT0INPROT | SHRTIMER_FLTINCFG0_FLT0INEN);
1606 fltincfg0 |= faultcfg->source;
1607 fltincfg0 |= faultcfg->polarity;
1608 fltincfg0 |= ((faultcfg->filter) << 3);
1609 fltincfg0 |= faultcfg->control;
1610 fltincfg0 |= faultcfg->protect;
1611 }
1612 break;
1613 case SHRTIMER_FAULT_1:
1614 {
1615 /* configure fault input 1 */
1616 fltincfg0 &= ~( SHRTIMER_FLTINCFG0_FLT1INP | SHRTIMER_FLTINCFG0_FLT1INSRC | SHRTIMER_FLTINCFG0_FLT1INFC | SHRTIMER_FLTINCFG0_FLT1INPROT | SHRTIMER_FLTINCFG0_FLT1INEN );
1617 fltincfg0 |= ((faultcfg->source) << 8);
1618 fltincfg0 |= ((faultcfg->polarity) << 8);
1619 fltincfg0 |= ((faultcfg->filter) << 11);
1620 fltincfg0 |= ((faultcfg->control) << 8);
1621 fltincfg0 |= ((faultcfg->protect) << 8);
1622 }
1623 break;
1624 case SHRTIMER_FAULT_2:
1625 {
1626 /* configure fault input 2 */
1627 fltincfg0 &= ~( SHRTIMER_FLTINCFG0_FLT2INP | SHRTIMER_FLTINCFG0_FLT2INSRC | SHRTIMER_FLTINCFG0_FLT2INFC | SHRTIMER_FLTINCFG0_FLT2INPROT | SHRTIMER_FLTINCFG0_FLT2INEN);
1628 fltincfg0 |= ((faultcfg->source) << 16);
1629 fltincfg0 |= ((faultcfg->polarity) << 16);
1630 fltincfg0 |= ((faultcfg->filter) << 19);
1631 fltincfg0 |= ((faultcfg->control) << 16);
1632 fltincfg0 |= ((faultcfg->protect) << 16);
1633 }
1634 break;
1635 case SHRTIMER_FAULT_3:
1636 {
1637 /* configure fault input 3 */
1638 fltincfg0 &= ~( SHRTIMER_FLTINCFG0_FLT3INP | SHRTIMER_FLTINCFG0_FLT3INSRC | SHRTIMER_FLTINCFG0_FLT3INFC | SHRTIMER_FLTINCFG0_FLT3INPROT | SHRTIMER_FLTINCFG0_FLT3INEN);
1639 fltincfg0 |= ((faultcfg->source) << 24);
1640 fltincfg0 |= ((faultcfg->polarity) << 24);
1641 fltincfg0 |= ((faultcfg->filter) << 27);
1642 fltincfg0 |= ((faultcfg->control) << 24);
1643 fltincfg0 |= ((faultcfg->protect) << 24);
1644 }
1645 break;
1646 case SHRTIMER_FAULT_4:
1647 {
1648 /* configure fault input 4 */
1649 fltincfg1 &= ~( SHRTIMER_FLTINCFG1_FLT4INP | SHRTIMER_FLTINCFG1_FLT4INSRC | SHRTIMER_FLTINCFG1_FLT4INFC | SHRTIMER_FLTINCFG1_FLT4INPROT | SHRTIMER_FLTINCFG1_FLT4INEN);
1650 fltincfg1 |= faultcfg->source;
1651 fltincfg1 |= faultcfg->polarity;
1652 fltincfg1 |= ((faultcfg->filter) << 3);
1653 fltincfg1 |= (faultcfg->control);
1654 fltincfg1 |= faultcfg->protect;
1655 }
1656 break;
1657 default:
1658 break;
1659 }
1660
1661 SHRTIMER_FLTINCFG0(shrtimer_periph) = fltincfg0;
1662 SHRTIMER_FLTINCFG1(shrtimer_periph) = fltincfg1;
1663 }
1664
1665 /*!
1666 \brief configure the fault input digital filter clock division
1667 \param[in] shrtimer_periph: SHRTIMER0
1668 \param[in] prescaler: clock division value
1669 only one parameter can be selected which is shown as below:
1670 \arg SHRTIMER_FAULT_PRESCALER_DIV1: fSHRTIMER_FLTFCK = fSHRTIMER_CK
1671 \arg SHRTIMER_FAULT_PRESCALER_DIV2: fSHRTIMER_FLTFCK = fSHRTIMER_CK / 2
1672 \arg SHRTIMER_EFAULT_PRESCALER_DIV4: fSHRTIMER_FLTFCK = fSHRTIMER_CK / 4
1673 \arg SHRTIMER_FAULT_PRESCALER_DIV8: fSHRTIMER_FLTFCK = fSHRTIMER_CK / 8
1674 \param[out] none
1675 \retval none
1676 */
shrtimer_fault_prescaler_config(uint32_t shrtimer_periph,uint32_t prescaler)1677 void shrtimer_fault_prescaler_config(uint32_t shrtimer_periph, uint32_t prescaler)
1678 {
1679 uint32_t fltincfg1;
1680
1681 /* configure digital filter clock division */
1682 fltincfg1 = SHRTIMER_FLTINCFG1(shrtimer_periph);
1683 fltincfg1 &= ~(SHRTIMER_FLTINCFG1_FLTFDIV);
1684 fltincfg1 |= prescaler;
1685 SHRTIMER_FLTINCFG1(shrtimer_periph) = fltincfg1;
1686 }
1687
1688 /*!
1689 \brief fault input enable
1690 \param[in] shrtimer_periph: SHRTIMER0
1691 \param[in] fault_id: SHRTIMER_FAULT_y(y=0..4)
1692 \param[out] none
1693 \retval none
1694 */
shrtimer_fault_input_enable(uint32_t shrtimer_periph,uint32_t fault_id)1695 void shrtimer_fault_input_enable(uint32_t shrtimer_periph, uint32_t fault_id)
1696 {
1697 uint32_t fltincfg0;
1698 uint32_t fltincfg1;
1699
1700 fltincfg0 = SHRTIMER_FLTINCFG0(shrtimer_periph);
1701 fltincfg1 = SHRTIMER_FLTINCFG1(shrtimer_periph);
1702
1703 switch (fault_id)
1704 {
1705 case SHRTIMER_FAULT_0:
1706 {
1707 /* configure fault input 0 */
1708 fltincfg0 |= SHRTIMER_FLTINCFG0_FLT0INEN;
1709 }
1710 break;
1711 case SHRTIMER_FAULT_1:
1712 {
1713 /* configure fault input 1 */
1714 fltincfg0 |= SHRTIMER_FLTINCFG0_FLT1INEN;
1715 }
1716 break;
1717 case SHRTIMER_FAULT_2:
1718 {
1719 /* configure fault input 2 */
1720 fltincfg0 |= SHRTIMER_FLTINCFG0_FLT2INEN;
1721 }
1722 break;
1723 case SHRTIMER_FAULT_3:
1724 {
1725 /* configure fault input 3 */
1726 fltincfg0 |= SHRTIMER_FLTINCFG0_FLT3INEN;
1727 }
1728 break;
1729 case SHRTIMER_FAULT_4:
1730 {
1731 /* configure fault input 4 */
1732 fltincfg1 |= SHRTIMER_FLTINCFG1_FLT4INEN;
1733 }
1734 break;
1735 default:
1736 break;
1737 }
1738
1739 SHRTIMER_FLTINCFG0(shrtimer_periph) = fltincfg0;
1740 SHRTIMER_FLTINCFG1(shrtimer_periph) = fltincfg1;
1741 }
1742
1743 /*!
1744 \brief fault input disable
1745 \param[in] shrtimer_periph: SHRTIMER0
1746 \param[in] fault_id: SHRTIMER_FAULT_y(y=0..4)
1747 \param[out] none
1748 \retval none
1749 */
shrtimer_fault_input_disable(uint32_t shrtimer_periph,uint32_t fault_id)1750 void shrtimer_fault_input_disable(uint32_t shrtimer_periph, uint32_t fault_id)
1751 {
1752 uint32_t fltincfg0;
1753 uint32_t fltincfg1;
1754
1755 fltincfg0 = SHRTIMER_FLTINCFG0(shrtimer_periph);
1756 fltincfg1 = SHRTIMER_FLTINCFG1(shrtimer_periph);
1757
1758 switch (fault_id)
1759 {
1760 case SHRTIMER_FAULT_0:
1761 {
1762 /* configure fault input 0 */
1763 fltincfg0 &= ~SHRTIMER_FLTINCFG0_FLT0INEN;
1764 }
1765 break;
1766 case SHRTIMER_FAULT_1:
1767 {
1768 /* configure fault input 1 */
1769 fltincfg0 &= ~SHRTIMER_FLTINCFG0_FLT1INEN;
1770 }
1771 break;
1772 case SHRTIMER_FAULT_2:
1773 {
1774 /* configure fault input 2 */
1775 fltincfg0 &= ~SHRTIMER_FLTINCFG0_FLT2INEN;
1776 }
1777 break;
1778 case SHRTIMER_FAULT_3:
1779 {
1780 /* configure fault input 3 */
1781 fltincfg0 &= ~SHRTIMER_FLTINCFG0_FLT3INEN;
1782 }
1783 break;
1784 case SHRTIMER_FAULT_4:
1785 {
1786 /* configure fault input 4 */
1787 fltincfg1 &= ~SHRTIMER_FLTINCFG1_FLT4INEN;
1788 }
1789 break;
1790 default:
1791 break;
1792 }
1793
1794 SHRTIMER_FLTINCFG0(shrtimer_periph) = fltincfg0;
1795 SHRTIMER_FLTINCFG1(shrtimer_periph) = fltincfg1;
1796 }
1797
1798 /*!
1799 \brief enable the Master_TIMER and Slave_TIMER DMA request
1800 \param[in] shrtimer_periph: SHRTIMER0
1801 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1802 \param[in] dmareq: DMA request source
1803 only one parameter can be selected which is shown as below:
1804 \arg SHRTIMER_MT_ST_DMA_CMP0: compare 0 DMA request, for Master_TIMER and Slave_TIMER
1805 \arg SHRTIMER_MT_ST_DMA_CMP1: compare 1 DMA request, for Master_TIMER and Slave_TIMER
1806 \arg SHRTIMER_MT_ST_DMA_CMP2: compare 2 DMA request, for Master_TIMER and Slave_TIMER
1807 \arg SHRTIMER_MT_ST_DMA_CMP3: compare 3 DMA request, for Master_TIMER and Slave_TIMER
1808 \arg SHRTIMER_MT_ST_DMA_REP: repetition DMA request, for Master_TIMER and Slave_TIMER
1809 \arg SHRTIMER_MT_DMA_SYNID: synchronization input DMA request, for Master_TIMER
1810 \arg SHRTIMER_MT_ST_DMA_UPD: update DMA request, for Master_TIMER and Slave_TIMER
1811 \arg SHRTIMER_ST_DMA_CAP0: capture 0 DMA request, for Slave_TIMER
1812 \arg SHRTIMER_ST_DMA_CAP0: capture 1 DMA request, for Slave_TIMER
1813 \arg SHRTIMER_ST_DMA_CH0OA: channel 0 output active DMA request, for Slave_TIMER
1814 \arg SHRTIMER_ST_DMA_CH0ONA: channel 0 output inactive DMA request, for Slave_TIMER
1815 \arg SHRTIMER_ST_DMA_CH1OA: channel 1 output active DMA request, for Slave_TIMER
1816 \arg SHRTIMER_ST_DMA_CH1ONA: channel 1 output inactive DMA request, for Slave_TIMER
1817 \arg SHRTIMER_ST_DMA_CNTRST: counter reset DMA request, for Slave_TIMER
1818 \arg SHRTIMER_ST_DMA_DLYIDLE: delay IDLE DMA request, for Slave_TIMER
1819 \param[out] none
1820 \retval none
1821 */
shrtimer_timers_dma_enable(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t dmareq)1822 void shrtimer_timers_dma_enable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t dmareq)
1823 {
1824 switch(timer_id)
1825 {
1826 /* enable the Master_TIMER request */
1827 case SHRTIMER_MASTER_TIMER:
1828 SHRTIMER_MTDMAINTEN(shrtimer_periph) |= dmareq;
1829 break;
1830 /* enable the Slave_TIMER DMA request */
1831 case SHRTIMER_SLAVE_TIMER0:
1832 case SHRTIMER_SLAVE_TIMER1:
1833 case SHRTIMER_SLAVE_TIMER2:
1834 case SHRTIMER_SLAVE_TIMER3:
1835 case SHRTIMER_SLAVE_TIMER4:
1836 SHRTIMER_STXDMAINTEN(shrtimer_periph, timer_id) |= dmareq;
1837 break;
1838
1839 default:
1840 break;
1841 }
1842 }
1843
1844 /*!
1845 \brief disable the Master_TIMER and Slave_TIMER DMA request
1846 \param[in] shrtimer_periph: SHRTIMER0
1847 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1848 \param[in] dmareq: DMA request source
1849 only one parameter can be selected which is shown as below:
1850 \arg SHRTIMER_MT_ST_DMA_CMP0: compare 0 DMA request, for Master_TIMER and Slave_TIMER
1851 \arg SHRTIMER_MT_ST_DMA_CMP1: compare 1 DMA request, for Master_TIMER and Slave_TIMER
1852 \arg SHRTIMER_MT_ST_DMA_CMP2: compare 2 DMA request, for Master_TIMER and Slave_TIMER
1853 \arg SHRTIMER_MT_ST_DMA_CMP3: compare 3 DMA request, for Master_TIMER and Slave_TIMER
1854 \arg SHRTIMER_MT_ST_DMA_REP: repetition DMA request, for Master_TIMER and Slave_TIMER
1855 \arg SHRTIMER_MT_DMA_SYNID: synchronization input DMA request, for Master_TIMER
1856 \arg SHRTIMER_MT_ST_DMA_UPD: update DMA request, for Master_TIMER and Slave_TIMER
1857 \arg SHRTIMER_ST_DMA_CAP0: capture 0 DMA request, for Slave_TIMER
1858 \arg SHRTIMER_ST_DMA_CAP0: capture 1 DMA request, for Slave_TIMER
1859 \arg SHRTIMER_ST_DMA_CH0OA: channel 0 output active DMA request, for Slave_TIMER
1860 \arg SHRTIMER_ST_DMA_CH0ONA: channel 0 output inactive DMA request, for Slave_TIMER
1861 \arg SHRTIMER_ST_DMA_CH1OA: channel 1 output active DMA request, for Slave_TIMER
1862 \arg SHRTIMER_ST_DMA_CH1ONA: channel 1 output inactive DMA request, for Slave_TIMER
1863 \arg SHRTIMER_ST_DMA_CNTRST: counter reset DMA request, for Slave_TIMER
1864 \arg SHRTIMER_ST_DMA_DLYIDLE: delay IDLE DMA request, for Slave_TIMER
1865 \param[out] none
1866 \retval none
1867 */
shrtimer_timers_dma_disable(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t dmareq)1868 void shrtimer_timers_dma_disable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t dmareq)
1869 {
1870 switch(timer_id)
1871 {
1872 /* disable the Master_TIMER request */
1873 case SHRTIMER_MASTER_TIMER:
1874 SHRTIMER_MTDMAINTEN(shrtimer_periph) &= ~dmareq;
1875 break;
1876 /* disable the Slave_TIMER request */
1877 case SHRTIMER_SLAVE_TIMER0:
1878 case SHRTIMER_SLAVE_TIMER1:
1879 case SHRTIMER_SLAVE_TIMER2:
1880 case SHRTIMER_SLAVE_TIMER3:
1881 case SHRTIMER_SLAVE_TIMER4:
1882 SHRTIMER_STXDMAINTEN(shrtimer_periph, timer_id) &= ~dmareq;
1883 break;
1884
1885 default:
1886 break;
1887 }
1888 }
1889
1890 /*!
1891 \brief configure the DMA mode for Master_TIMER or Slave_TIMER
1892 \param[in] shrtimer_periph: SHRTIMER0
1893 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
1894 \param[in] regupdate: registers to be updated
1895 one or more parameters can be selected which is shown as below:
1896 \arg SHRTIMER_DMAMODE_NONE: No register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1897 \arg SHRTIMER_DMAMODE_CTL0: MTCTL0 or STxCTL0 register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1898 \arg SHRTIMER_DMAMODE_INTC: MT or STx register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1899 \arg SHRTIMER_DMAMODE_DMAINTEN: MTINTC or STxINTC register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1900 \arg SHRTIMER_DMAMODE_CNT: MTCNT or STxCNT register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1901 \arg SHRTIMER_DMAMODE_CAR: MTCAR or STxCAR register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1902 \arg SHRTIMER_DMAMODE_CREP: MTCREP or STxCREP register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1903 \arg SHRTIMER_DMAMODE_CMP0V: MTCMP0V or STxCMP0V register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1904 \arg SHRTIMER_DMAMODE_CMP1V: MTCMP1V or STxCMP1V register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1905 \arg SHRTIMER_DMAMODE_CMP2V: MTCMP2V or STxCMP2V register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1906 \arg SHRTIMER_DMAMODE_CMP3V: MTCMP3V or STxCMP3V register is updated by DMA mode, for Master_TIMER and Slave_TIMER
1907 \arg SHRTIMER_DMAMODE_DTCTL: STxDTCTL register is updated by DMA mode, only for Slave_TIMER
1908 \arg SHRTIMER_DMAMODE_CH0SET: STxCH0SET register is updated by DMA mode, only for Slave_TIMER
1909 \arg SHRTIMER_DMAMODE_CH0RST: STxCH0RST register is updated by DMA mode, only for Slave_TIMER
1910 \arg SHRTIMER_DMAMODE_CH1SET: STxCH1SET register is updated by DMA mode, only for Slave_TIMER
1911 \arg SHRTIMER_DMAMODE_CH1RST: STxCH1RST register is updated by DMA mode, only for Slave_TIMER
1912 \arg SHRTIMER_DMAMODE_EXEVFCFG0: STxEXEVFCFG0 register is updated by DMA mode, only for Slave_TIMER
1913 \arg SHRTIMER_DMAMODE_EXEVFCFG1: STxEXEVFCFG1 register is updated by DMA mode, only for Slave_TIMER
1914 \arg SHRTIMER_DMAMODE_CNTRST: STxCNTRST register is updated by DMA mode, only for Slave_TIMER
1915 \arg SHRTIMER_DMAMODE_CSCTL: STxCSCTL register is updated by DMA mode, only for Slave_TIMER
1916 \arg SHRTIMER_DMAMODE_CHOCTL: STxCHOCTL register is updated by DMA mode, only for Slave_TIMER
1917 \arg SHRTIMER_DMAMODE_FLTCTL: STxFLTCTL register is updated by DMA mode, only for Slave_TIMER
1918 \arg SHRTIMER_DMAMODE_ACTL: STxACTL register is updated by DMA mode, only for Slave_TIMER
1919 \param[out] none
1920 \retval none
1921 */
shrtimer_dmamode_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t regupdate)1922 void shrtimer_dmamode_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t regupdate)
1923 {
1924 switch (timer_id)
1925 {
1926 /* set the DMA mode update Slave_TIMER0 registers */
1927 case SHRTIMER_SLAVE_TIMER0:
1928 {
1929 SHRTIMER_DMAUPST0R(shrtimer_periph) = regupdate;
1930 }
1931 break;
1932 /* set the DMA mode update Slave_TIMER1 registers */
1933 case SHRTIMER_SLAVE_TIMER1:
1934 {
1935 SHRTIMER_DMAUPST1R(shrtimer_periph) = regupdate;
1936 }
1937 break;
1938 /* set the DMA mode update Slave_TIMER2 registers */
1939 case SHRTIMER_SLAVE_TIMER2:
1940 {
1941 SHRTIMER_DMAUPST2R(shrtimer_periph) = regupdate;
1942 }
1943 break;
1944 /* set the DMA mode update Slave_TIMER3 registers */
1945 case SHRTIMER_SLAVE_TIMER3:
1946 {
1947 SHRTIMER_DMAUPST3R(shrtimer_periph) = regupdate;
1948 }
1949 /* set the DMA mode update Slave_TIMER4 registers */
1950 break;
1951 case SHRTIMER_SLAVE_TIMER4:
1952 {
1953 SHRTIMER_DMAUPST4R(shrtimer_periph) = regupdate;
1954 }
1955 break;
1956 /* set the DMA mode update Master_TIMER registers */
1957 case SHRTIMER_MASTER_TIMER:
1958 {
1959 SHRTIMER_DMAUPMTR(shrtimer_periph) = regupdate;
1960 }
1961 break;
1962 default:
1963 break;
1964 }
1965 }
1966
1967 /*!
1968 \brief initialize bunch mode configuration struct with a default value
1969 \param[in] bmcfg: bunch mode configuration struct
1970 \param[out] none
1971 \retval none
1972 */
shrtimer_bunchmode_struct_para_init(shrtimer_bunchmode_parameter_struct * bmcfg)1973 void shrtimer_bunchmode_struct_para_init(shrtimer_bunchmode_parameter_struct* bmcfg)
1974 {
1975 bmcfg->clock_source = SHRTIMER_BUNCHMODE_CLOCKSOURCE_MASTER;
1976 bmcfg->idle_duration = 0U;
1977 bmcfg->mode = SHRTIMER_BUNCHMODE_SINGLE;
1978 bmcfg->period = 0U;
1979 bmcfg->prescaler = SHRTIMER_BUNCHMODE_PRESCALER_DIV1;
1980 bmcfg->shadow = SHRTIMER_BUNCHMODEPRELOAD_DISABLED;
1981 bmcfg->trigger = SHRTIMER_BUNCHMODE_TRIGGER_NONE;
1982 }
1983
1984 /*!
1985 \brief configure bunch mode for the SHRTIMER
1986 \param[in] shrtimer_periph: SHRTIMER0
1987 \param[in] bmcfg: bunch mode configuration struct
1988 mode: SHRTIMER_BUNCHMODE_SINGLE, SHRTIMER_BUNCHMODE_CONTINOUS
1989 clock_source: SHRTIMER_BUNCHMODE_CLOCKSOURCE_MASTER, SHRTIMER_BUNCHMODE_CLOCKSOURCE_STy(y=0..4), SHRTIMER_BUNCHMODE_CLOCKSOURCE_TIMER6_TRGO, SHRTIMER_BUNCHMODE_CLOCKSOURCE_SHRTIMERCK
1990 prescaler: SHRTIMER_BUNCHMODE_PRESCALER_DIVy(y=1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768)
1991 shadow: SHRTIMER_BUNCHMODEPRELOAD_DISABLED, SHRTIMER_BUNCHMODEPRELOAD_ENABLED
1992 trigger: SHRTIMER_BUNCHMODE_TRIGGER_NONE, SHRTIMER_BUNCHMODE_TRIGGER_MTRESET, SHRTIMER_BUNCHMODE_TRIGGER_MTREPETITION, SHRTIMER_BUNCHMODE_TRIGGER_MTCMPy(y=0..3),
1993 SHRTIMER_BUNCHMODE_TRIGGER_STxRESET(x=0..4), SHRTIMER_BUNCHMODE_TRIGGER_STxREPETITION(x=0..4), SHRTIMER_BUNCHMODE_TRIGGER_STxCMPy(x=0..4, y=0,1), SHRTIMER_BUNCHMODE_TRIGGER_ST0EVENT6,
1994 SHRTIMER_BUNCHMODE_TRIGGER_ST3EVENT7, SHRTIMER_BUNCHMODE_TRIGGER_EVENT6, SHRTIMER_BUNCHMODE_TRIGGER_EVENT7, SHRTIMER_BUNCHMODE_TRIGGER_CHIP
1995 idle_duration: 0x0000~0xFFFF
1996 period: 0x0001~0xFFFF
1997 \param[out] none
1998 \retval none
1999 */
shrtimer_bunchmode_config(uint32_t shrtimer_periph,shrtimer_bunchmode_parameter_struct * bmcfg)2000 void shrtimer_bunchmode_config(uint32_t shrtimer_periph, shrtimer_bunchmode_parameter_struct* bmcfg)
2001 {
2002 uint32_t bmctl_reg;
2003
2004 bmctl_reg = SHRTIMER_BMCTL(shrtimer_periph);
2005
2006 /* set the bunch mode operating mode */
2007 bmctl_reg &= ~(SHRTIMER_BMCTL_BMCTN);
2008 bmctl_reg |= bmcfg->mode;
2009
2010 /* set the bunch mode clock source */
2011 bmctl_reg &= ~(SHRTIMER_BMCTL_BMCLKS);
2012 bmctl_reg |= bmcfg->clock_source;
2013
2014 /* set the bunch mode prescaler */
2015 bmctl_reg &= ~(SHRTIMER_BMCTL_BMPSC);
2016 bmctl_reg |= bmcfg->prescaler;
2017
2018 /* enable/disable bunch mode shadow registers */
2019 bmctl_reg &= ~(SHRTIMER_BMCTL_BMSE);
2020 bmctl_reg |= bmcfg->shadow;
2021
2022 /* set the bunch mode trigger */
2023 SHRTIMER_BMSTRG(shrtimer_periph) = bmcfg->trigger;
2024
2025 /* set the bunch mode compare value */
2026 SHRTIMER_BMCMPV(shrtimer_periph) = bmcfg->idle_duration;
2027
2028 /* set the bunch mode period */
2029 SHRTIMER_BMCAR(shrtimer_periph) = bmcfg->period;
2030
2031 SHRTIMER_BMCTL(shrtimer_periph) = bmctl_reg;
2032 }
2033
2034 /*!
2035 \brief enable bunch mode for the SHRTIMER
2036 \param[in] shrtimer_periph: SHRTIMER0
2037 \param[out] none
2038 \retval none
2039 */
shrtimer_bunchmode_enable(uint32_t shrtimer_periph)2040 void shrtimer_bunchmode_enable(uint32_t shrtimer_periph)
2041 {
2042 SHRTIMER_BMCTL(shrtimer_periph) |= SHRTIMER_BMCTL_BMEN;
2043 }
2044
2045 /*!
2046 \brief disable bunch mode for the SHRTIMER
2047 \param[in] shrtimer_periph: SHRTIMER0
2048 \param[out] none
2049 \retval none
2050 */
shrtimer_bunchmode_disable(uint32_t shrtimer_periph)2051 void shrtimer_bunchmode_disable(uint32_t shrtimer_periph)
2052 {
2053 SHRTIMER_BMCTL(shrtimer_periph) &= ~SHRTIMER_BMCTL_BMEN;
2054 }
2055
2056 /*!
2057 \brief get bunch mode operating flag
2058 \param[in] shrtimer_periph: SHRTIMER0
2059 \param[out] none
2060 \retval bunch mode operating state
2061 */
shrtimer_bunchmode_flag_get(uint32_t shrtimer_periph)2062 uint32_t shrtimer_bunchmode_flag_get(uint32_t shrtimer_periph)
2063 {
2064 uint32_t val = SHRTIMER_BUNCHMODE_OPERATION_OFF;
2065 /* judge bunch mode operating state */
2066 if(RESET != (SHRTIMER_BMCTL(shrtimer_periph) & SHRTIMER_BMCTL_BMOPTF)){
2067 val = SHRTIMER_BUNCHMODE_OPERATION_ON;
2068 }else{
2069 val = SHRTIMER_BUNCHMODE_OPERATION_OFF;
2070 }
2071 return val;
2072 }
2073
2074 /*!
2075 \brief bunch mode started by software
2076 \param[in] shrtimer_periph: SHRTIMER0
2077 \param[out] none
2078 \retval bunch mode operating state
2079 */
shrtimer_bunchmode_software_start(uint32_t shrtimer_periph)2080 void shrtimer_bunchmode_software_start(uint32_t shrtimer_periph)
2081 {
2082 SHRTIMER_BMSTRG(shrtimer_periph) |= SHRTIMER_BMSTRG_SWTRG;
2083 }
2084
2085 /*!
2086 \brief configure the capture source in Slave_TIMER
2087 \param[in] shrtimer_periph: SHRTIMER0
2088 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
2089 \param[in] capturex: SHRTIMER_CAPTURE_y(y=0, 1)
2090 \param[in] trgsource: capture source
2091 one or more parameters can be selected which is shown as below:
2092 \arg SHRTIMER_CAPTURETRIGGER_NONE: Capture trigger is disabled
2093 \arg SHRTIMER_CAPTURETRIGGER_UPDATE: capture triggered by update event
2094 \arg SHRTIMER_CAPTURETRIGGER_EXEV_0: capture triggered by external event 0
2095 \arg SHRTIMER_CAPTURETRIGGER_EXEV_1: capture triggered by external event 1
2096 \arg SHRTIMER_CAPTURETRIGGER_EXEV_2: capture triggered by external event 2
2097 \arg SHRTIMER_CAPTURETRIGGER_EXEV_3: capture triggered by external event 3
2098 \arg SHRTIMER_CAPTURETRIGGER_EXEV_4: capture triggered by external event 4
2099 \arg SHRTIMER_CAPTURETRIGGER_EXEV_5: capture triggered by external event 5
2100 \arg SHRTIMER_CAPTURETRIGGER_EXEV_6: capture triggered by external event 6
2101 \arg SHRTIMER_CAPTURETRIGGER_EXEV_7: capture triggered by external event 7
2102 \arg SHRTIMER_CAPTURETRIGGER_EXEV_8: capture triggered by external event 8
2103 \arg SHRTIMER_CAPTURETRIGGER_EXEV_9: capture triggered by external event 9
2104 \arg SHRTIMER_CAPTURETRIGGER_ST0_ACTIVE: capture triggered by ST0CH0_O output inactive to active transition
2105 \arg SHRTIMER_CAPTURETRIGGER_ST0_INACTIVE: capture triggered by ST0CH0_O output active to inactive transition
2106 \arg SHRTIMER_CAPTURETRIGGER_ST0_CMP0: capture triggered by compare 0 event of Slave_TIMER0
2107 \arg SHRTIMER_CAPTURETRIGGER_ST0_CMP1: capture triggered by compare 1 event of Slave_TIMER0
2108 \arg SHRTIMER_CAPTURETRIGGER_ST1_ACTIVE: capture triggered by ST1CH0_O output inactive to active transition
2109 \arg SHRTIMER_CAPTURETRIGGER_ST1_INACTIVE: capture triggered by ST1CH0_O output active to inactive transition
2110 \arg SHRTIMER_CAPTURETRIGGER_ST1_CMP0: capture triggered by compare 0 event of Slave_TIMER1
2111 \arg SHRTIMER_CAPTURETRIGGER_ST1_CMP1: capture triggered by compare 1 event of Slave_TIMER1
2112 \arg SHRTIMER_CAPTURETRIGGER_ST2_ACTIVE: capture triggered by ST2CH0_O output inactive to active transition
2113 \arg SHRTIMER_CAPTURETRIGGER_ST2_INACTIVE: capture triggered by ST2CH0_O output active to inactive transition
2114 \arg SHRTIMER_CAPTURETRIGGER_ST2_CMP0: capture triggered by compare 0 event of Slave_TIMER2
2115 \arg SHRTIMER_CAPTURETRIGGER_ST2_CMP1: capture triggered by compare 1 event of Slave_TIMER2
2116 \arg SHRTIMER_CAPTURETRIGGER_ST3_ACTIVE: capture triggered by ST3CH0_O output inactive to active transition
2117 \arg SHRTIMER_CAPTURETRIGGER_ST3_INACTIVE: capture triggered by ST3CH0_O output active to inactive transition
2118 \arg SHRTIMER_CAPTURETRIGGER_ST3_CMP0: capture triggered by compare 0 event of Slave_TIMER3
2119 \arg SHRTIMER_CAPTURETRIGGER_ST3_CMP1: capture triggered by compare 1 event of Slave_TIMER3
2120 \arg SHRTIMER_CAPTURETRIGGER_ST4_ACTIVE: capture triggered by ST4CH0_O output inactive to active transition
2121 \arg SHRTIMER_CAPTURETRIGGER_ST4_INACTIVE: capture triggered by ST4CH0_O output active to inactive transition
2122 \arg SHRTIMER_CAPTURETRIGGER_ST4_CMP0: capture triggered by compare 0 event of Slave_TIMER4
2123 \arg SHRTIMER_CAPTURETRIGGER_ST4_CMP1: capture triggered by compare 1 event of Slave_TIMER4
2124 \param[out] none
2125 \retval none
2126 */
shrtimer_slavetimer_capture_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t capturex,uint32_t trgsource)2127 void shrtimer_slavetimer_capture_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t capturex, uint32_t trgsource)
2128 {
2129 switch (capturex)
2130 {
2131 /* configure the capture 0 unit */
2132 case SHRTIMER_CAPTURE_0:
2133 {
2134 SHRTIMER_STXCAP0TRG(shrtimer_periph, timer_id) = trgsource;
2135 }
2136 break;
2137 /* configure the capture 1 unit */
2138 case SHRTIMER_CAPTURE_1:
2139 {
2140 SHRTIMER_STXCAP1TRG(shrtimer_periph, timer_id) = trgsource;
2141 }
2142 break;
2143 default:
2144 break;
2145 }
2146 }
2147
2148 /*!
2149 \brief configure the capture source in Slave_TIMER
2150 \param[in] shrtimer_periph: SHRTIMER0
2151 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
2152 \param[in] capturex: SHRTIMER_CAPTURE_y(y=0, 1)
2153 \param[out] none
2154 \retval none
2155 */
shrtimer_slavetimer_capture_software(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t capturex)2156 void shrtimer_slavetimer_capture_software(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t capturex)
2157 {
2158 switch (capturex)
2159 {
2160 /* configure the capture 0 unit */
2161 case SHRTIMER_CAPTURE_0:
2162 {
2163 SHRTIMER_STXCAP0TRG(shrtimer_periph, timer_id) |= SHRTIMER_STXCAP0TRG_CP0BSW;
2164 }
2165 break;
2166 /* configure the capture 1 unit */
2167 case SHRTIMER_CAPTURE_1:
2168 {
2169 SHRTIMER_STXCAP1TRG(shrtimer_periph, timer_id) |= SHRTIMER_STXCAP1TRG_CP1BSW;
2170 }
2171 break;
2172 default:
2173 break;
2174 }
2175 }
2176
2177 /*!
2178 \brief read the capture value
2179 \param[in] shrtimer_periph: SHRTIMER0
2180 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
2181 \param[in] capturex: SHRTIMER_CAPTURE_y(y=0, 1)
2182 \param[out] none
2183 \retval capture value
2184 */
shrtimer_slavetimer_capture_value_read(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t capturex)2185 uint32_t shrtimer_slavetimer_capture_value_read(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t capturex)
2186 {
2187 uint32_t cap_val = 0;
2188
2189 switch (capturex)
2190 {
2191 /* read capture 0 value */
2192 case SHRTIMER_CAPTURE_0:
2193 {
2194 cap_val = SHRTIMER_STXCAP0V(shrtimer_periph, timer_id);
2195 }
2196 break;
2197 /* read capture 1 value */
2198 case SHRTIMER_CAPTURE_1:
2199 {
2200 cap_val = SHRTIMER_STXCAP1V(shrtimer_periph, timer_id);
2201 }
2202 break;
2203 default:
2204 break;
2205 }
2206
2207 return cap_val;
2208 }
2209
2210 /*!
2211 \brief initialize ADC trigger configuration struct with a default value
2212 \param[in] triggercfg: ADC trigger configuration struct
2213 \param[out] none
2214 \retval none
2215 */
shrtimer_adctrigcfg_struct_para_init(shrtimer_adctrigcfg_parameter_struct * triggercfg)2216 void shrtimer_adctrigcfg_struct_para_init(shrtimer_adctrigcfg_parameter_struct* triggercfg)
2217 {
2218 triggercfg->trigger = SHRTIMER_ADCTRGI02_EVENT_NONE;
2219 triggercfg->update_source = SHRTIMER_ADCTRGI_UPDATE_MT;
2220 }
2221
2222 /*!
2223 \brief configure the trigger source to ADC and the update source
2224 \param[in] shrtimer_periph: SHRTIMER0
2225 \param[in] trigger_id: SHRTIMER_ADCTRIG_y(y=0..3)
2226 \param[in] triggercfg: ADC trigger configuration struct
2227 update_source: SHRTIMER_ADCTRGI_UPDATE_MT, SHRTIMER_ADCTRGI_UPDATE_STx(x=0..4)
2228 trigger:
2229 for SHRTIMER_ADCTRIG0 and SHRTIMER_ADCTRIG2:
2230 SHRTIMER_ADCTRGI02_EVENT_NONE, SHRTIMER_ADCTRGI02_EVENT_MTCMPy(y=0..3),
2231 SHRTIMER_ADCTRGI02_EVENT_MTPER, SHRTIMER_ADCTRGI02_EVENT_EXEVy(y=0..4),
2232 SHRTIMER_ADCTRGI02_EVENT_STxCMPy(x=0..4,y=1..3),
2233 SHRTIMER_ADCTRGI02_EVENT_STxPER(x=0..4), SHRTIMER_ADCTRGI02_EVENT_ST0xRST(x=0,1)
2234 for SHRTIMER_ADCTRIG1 and SHRTIMER_ADCTRIG3:
2235 SHRTIMER_ADCTRGI13_EVENT_NONE, SHRTIMER_ADCTRGI13_EVENT_MTCMPy(y=0..3), SHRTIMER_ADCTRGI13_EVENT_MTPER,
2236 SHRTIMER_ADCTRGI13_EVENT_EXEVy(y=5..9), SHRTIMER_ADCTRGI13_EVENT_STxCMPy(x=0..4, y=1..3),
2237 SHRTIMER_ADCTRGI13_EVENT_STxPER(x=0..3), SHRTIMER_ADCTRGI13_EVENT_STxRST(x=2..4)
2238 \param[out] none
2239 \retval none
2240 */
shrtimer_adc_trigger_config(uint32_t shrtimer_periph,uint32_t trigger_id,shrtimer_adctrigcfg_parameter_struct * triggercfg)2241 void shrtimer_adc_trigger_config(uint32_t shrtimer_periph, uint32_t trigger_id, shrtimer_adctrigcfg_parameter_struct* triggercfg)
2242 {
2243 uint32_t comctl0_reg;
2244
2245 comctl0_reg = SHRTIMER_CTL0(shrtimer_periph);
2246 switch (trigger_id)
2247 {
2248 /* configure the ADC trigger 0 */
2249 case SHRTIMER_ADCTRIG_0:
2250 {
2251 /* configure update source */
2252 comctl0_reg &= ~(SHRTIMER_CTL0_ADTG0USRC);
2253 comctl0_reg |= triggercfg->update_source;
2254
2255 /* set the SHRTIMER_ADCTRIG0 source */
2256 SHRTIMER_ADCTRIGS0(shrtimer_periph) = triggercfg->trigger;
2257 }
2258 break;
2259 /* configure the ADC trigger 1 */
2260 case SHRTIMER_ADCTRIG_1:
2261 {
2262 /* configure update source */
2263 comctl0_reg &= ~(SHRTIMER_CTL0_ADTG1USRC);
2264 comctl0_reg |= ((triggercfg->update_source) << 3);
2265
2266 /* set the SHRTIMER_ADCTRIG1 source */
2267 SHRTIMER_ADCTRIGS1(shrtimer_periph) = triggercfg->trigger;
2268 }
2269 break;
2270 /* configure the ADC trigger 2 */
2271 case SHRTIMER_ADCTRIG_2:
2272 {
2273 /* configure update source */
2274 comctl0_reg &= ~(SHRTIMER_CTL0_ADTG2USRC);
2275 comctl0_reg |= ((triggercfg->update_source) << 6);
2276
2277 /* set the SHRTIMER_ADCTRIG2 source */
2278 SHRTIMER_ADCTRIGS2(shrtimer_periph) = triggercfg->trigger;
2279 }
2280 break;
2281 /* configure the ADC trigger 3 */
2282 case SHRTIMER_ADCTRIG_3:
2283 {
2284 /* configure update source */
2285 comctl0_reg &= ~(SHRTIMER_CTL0_ADTG3USRC);
2286 comctl0_reg |= ((triggercfg->update_source) << 9);
2287
2288 /* set the SHRTIMER_ADCTRIG3 source */
2289 SHRTIMER_ADCTRIGS3(shrtimer_periph) = triggercfg->trigger;
2290 }
2291 break;
2292 default:
2293 break;
2294 }
2295
2296 SHRTIMER_CTL0(shrtimer_periph) = comctl0_reg;
2297 }
2298
2299 /*!
2300 \brief get the Master_TIMER and Slave_TIMER flag
2301 \param[in] shrtimer_periph: SHRTIMER0
2302 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
2303 \param[in] flag: flag source
2304 only one parameter can be selected which is shown as below:
2305 \arg SHRTIMER_MT_ST_FLAG_CMP0: compare 0 flag, for Master_TIMER and Slave_TIMER
2306 \arg SHRTIMER_MT_ST_FLAG_CMP1: compare 1 flag, for Master_TIMER and Slave_TIMER
2307 \arg SHRTIMER_MT_ST_FLAG_CMP2: compare 2 flag, for Master_TIMER and Slave_TIMER
2308 \arg SHRTIMER_MT_ST_FLAG_CMP3: compare 3 flag, for Master_TIMER and Slave_TIMER
2309 \arg SHRTIMER_MT_ST_FLAG_REP: repetition flag, for Master_TIMER and Slave_TIMER
2310 \arg SHRTIMER_MT_FLAG_SYNI: synchronization input flag, for Master_TIMER
2311 \arg SHRTIMER_MT_ST_FLAG_UPD: update flag, for Master_TIMER and Slave_TIMER
2312 \arg SHRTIMER_ST_FLAG_CAP0: capture 0 flag, for Slave_TIMER
2313 \arg SHRTIMER_ST_FLAG_CAP1: capture 1 flag, for Slave_TIMER
2314 \arg SHRTIMER_ST_FLAG_CH0OA: channel 0 output active flag, for Slave_TIMER
2315 \arg SHRTIMER_ST_FLAG_CH0ONA: channel 0 output inactive flag, for Slave_TIMER
2316 \arg SHRTIMER_ST_FLAG_CH1OA: channel 1 output active flag, for Slave_TIMER
2317 \arg SHRTIMER_ST_FLAG_CH1ONA: channel 1 output inactive flag, for Slave_TIMER
2318 \arg SHRTIMER_ST_FLAG_CNTRST: counter reset flag, for Slave_TIMER
2319 \arg SHRTIMER_ST_FLAG_DLYIDLE: delayed IDLE mode entry flag, for Slave_TIMER
2320 \arg SHRTIMER_ST_FLAG_CBLN: current balanced flag, for Slave_TIMER
2321 \arg SHRTIMER_ST_FLAG_BLNIDLE: balanced IDLE flag, for Slave_TIMER
2322 \arg SHRTIMER_ST_FLAG_CH0OUT: channel 0 output flag, for Slave_TIMER
2323 \arg SHRTIMER_ST_FLAG_CH1OUT: channel 1 output flag, for Slave_TIMER
2324 \param[out] none
2325 \retval FlagStatus: SET or RESET
2326 */
shrtimer_timers_flag_get(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t flag)2327 FlagStatus shrtimer_timers_flag_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t flag)
2328 {
2329 FlagStatus flag_val = RESET;
2330 switch(timer_id)
2331 {
2332 /* get the Master_TIMER flag */
2333 case SHRTIMER_MASTER_TIMER:
2334 if(RESET != (SHRTIMER_MTINTF(shrtimer_periph) & flag)){
2335 flag_val = SET;
2336 }else{
2337 flag_val = RESET;
2338 }
2339 break;
2340 /* get the Slave_TIMER flag */
2341 case SHRTIMER_SLAVE_TIMER0:
2342 case SHRTIMER_SLAVE_TIMER1:
2343 case SHRTIMER_SLAVE_TIMER2:
2344 case SHRTIMER_SLAVE_TIMER3:
2345 case SHRTIMER_SLAVE_TIMER4:
2346 if(RESET != (SHRTIMER_STXINTF(shrtimer_periph, timer_id) & flag)){
2347 flag_val = SET;
2348 }else{
2349 flag_val = RESET;
2350 }
2351 break;
2352
2353 default:
2354 break;
2355 }
2356 return flag_val;
2357 }
2358
2359 /*!
2360 \brief clear the Master_TIMER and Slave_TIMER flag
2361 \param[in] shrtimer_periph: SHRTIMER0
2362 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
2363 \param[in] flag: flag source
2364 only one parameter can be selected which is shown as below:
2365 \arg SHRTIMER_MT_ST_FLAG_CMP0: compare 0 flag, for Master_TIMER and Slave_TIMER
2366 \arg SHRTIMER_MT_ST_FLAG_CMP1: compare 1 flag, for Master_TIMER and Slave_TIMER
2367 \arg SHRTIMER_MT_ST_FLAG_CMP2: compare 2 flag, for Master_TIMER and Slave_TIMER
2368 \arg SHRTIMER_MT_ST_FLAG_CMP3: compare 3 flag, for Master_TIMER and Slave_TIMER
2369 \arg SHRTIMER_MT_ST_FLAG_REP: repetition flag, for Master_TIMER and Slave_TIMER
2370 \arg SHRTIMER_MT_FLAG_SYNI: synchronization input flag, for Master_TIMER
2371 \arg SHRTIMER_MT_ST_FLAG_UPD: update flag, for Master_TIMER and Slave_TIMER
2372 \arg SHRTIMER_ST_FLAG_CAP0: capture 0 flag, for Slave_TIMER
2373 \arg SHRTIMER_ST_FLAG_CAP1: capture 1 flag, for Slave_TIMER
2374 \arg SHRTIMER_ST_FLAG_CH0OA: channel 0 output active flag, for Slave_TIMER
2375 \arg SHRTIMER_ST_FLAG_CH0ONA: channel 0 output inactive flag, for Slave_TIMER
2376 \arg SHRTIMER_ST_FLAG_CH1OA: channel 1 output active flag, for Slave_TIMER
2377 \arg SHRTIMER_ST_FLAG_CH1ONA: channel 1 output inactive flag, for Slave_TIMER
2378 \arg SHRTIMER_ST_FLAG_CNTRST: counter reset flag, for Slave_TIMER
2379 \arg SHRTIMER_ST_FLAG_DLYIDLE: delayed IDLE mode entry flag, for Slave_TIMER
2380 \arg SHRTIMER_ST_FLAG_CBLN: current balanced flag, for Slave_TIMER
2381 \arg SHRTIMER_ST_FLAG_BLNIDLE: balanced IDLE flag, for Slave_TIMER
2382 \arg SHRTIMER_ST_FLAG_CH0OUT: channel 0 output flag, for Slave_TIMER
2383 \arg SHRTIMER_ST_FLAG_CH1OUT: channel 1 output flag, for Slave_TIMER
2384 \param[out] none
2385 \retval none
2386 */
shrtimer_timers_flag_clear(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t flag)2387 void shrtimer_timers_flag_clear(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t flag)
2388 {
2389 switch(timer_id)
2390 {
2391 /* clear the Master_TIMER flag */
2392 case SHRTIMER_MASTER_TIMER:
2393 SHRTIMER_MTINTC(shrtimer_periph) |= flag;
2394 break;
2395 /* clear the Slave_TIMER flag */
2396 case SHRTIMER_SLAVE_TIMER0:
2397 case SHRTIMER_SLAVE_TIMER1:
2398 case SHRTIMER_SLAVE_TIMER2:
2399 case SHRTIMER_SLAVE_TIMER3:
2400 case SHRTIMER_SLAVE_TIMER4:
2401 SHRTIMER_STXINTC(shrtimer_periph, timer_id) |= flag;
2402 break;
2403 default:
2404 break;
2405 }
2406 }
2407
2408 /*!
2409 \brief get the common interrupt flag
2410 \param[in] shrtimer_periph: SHRTIMER0
2411 \param[in] flag: flag source
2412 only one parameter can be selected which is shown as below:
2413 \arg SHRTIMER_FLAG_FLT0: fault 0 flag
2414 \arg SHRTIMER_FLAG_FLT1: fault 1 flag
2415 \arg SHRTIMER_FLAG_FLT2: fault 2 flag
2416 \arg SHRTIMER_FLAG_FLT3: fault 3 flag
2417 \arg SHRTIMER_FLAG_FLT4: fault 4 flag
2418 \arg SHRTIMER_FLAG_SYSFLT: system fault flag
2419 \arg SHRTIMER_FLAG_DLLCAL: DLL calibration completed flag
2420 \arg SHRTIMER_FLAG_BMPER: bunch mode period flag
2421 \param[out] none
2422 \retval FlagStatus: SET or RESET
2423 */
shrtimer_common_flag_get(uint32_t shrtimer_periph,uint32_t flag)2424 FlagStatus shrtimer_common_flag_get(uint32_t shrtimer_periph, uint32_t flag)
2425 {
2426 /* judge interrupt status */
2427 if(RESET != (SHRTIMER_INTF(shrtimer_periph) & flag)){
2428 return SET;
2429 }else{
2430 return RESET;
2431 }
2432 }
2433
2434 /*!
2435 \brief clear the common interrupt flag
2436 \param[in] shrtimer_periph: SHRTIMER0
2437 \param[in] flag: flag source
2438 only one parameter can be selected which is shown as below:
2439 \arg SHRTIMER_FLAG_FLT0: fault 0 flag
2440 \arg SHRTIMER_FLAG_FLT1: fault 1 flag
2441 \arg SHRTIMER_FLAG_FLT2: fault 2 flag
2442 \arg SHRTIMER_FLAG_FLT3: fault 3 flag
2443 \arg SHRTIMER_FLAG_FLT4: fault 4 flag
2444 \arg SHRTIMER_FLAG_SYSFLT: system fault flag
2445 \arg SHRTIMER_FLAG_DLLCAL: DLL calibration completed flag
2446 \arg SHRTIMER_FLAG_BMPER: bunch mode period flag
2447 \param[out] none
2448 \retval none
2449 */
shrtimer_common_flag_clear(uint32_t shrtimer_periph,uint32_t flag)2450 void shrtimer_common_flag_clear(uint32_t shrtimer_periph, uint32_t flag)
2451 {
2452 SHRTIMER_INTC(shrtimer_periph) |= flag;
2453 }
2454
2455 /*!
2456 \brief enable the Master_TIMER and Slave_TIMER interrupt
2457 \param[in] shrtimer_periph: SHRTIMER0
2458 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
2459 \param[in] interrupt: interrupt source
2460 only one parameter can be selected which is shown as below:
2461 \arg SHRTIMER_MT_ST_INT_CMP0: compare 0 interrupt, for Master_TIMER and Slave_TIMER
2462 \arg SHRTIMER_MT_ST_INT_CMP1: compare 1 interrupt, for Master_TIMER and Slave_TIMER
2463 \arg SHRTIMER_MT_ST_INT_CMP2: compare 2 interrupt, for Master_TIMER and Slave_TIMER
2464 \arg SHRTIMER_MT_ST_INT_CMP3: compare 3 interrupt, for Master_TIMER and Slave_TIMER
2465 \arg SHRTIMER_MT_ST_INT_REP: repetition interrupt, for Master_TIMER and Slave_TIMER
2466 \arg SHRTIMER_MT_INT_SYNI: synchronization input interrupt, for Master_TIMER
2467 \arg SHRTIMER_MT_ST_INT_UPD: update interrupt, for Master_TIMER and Slave_TIMER
2468 \arg SHRTIMER_ST_INT_CAP0: capture 0 interrupt, for Slave_TIMER
2469 \arg SHRTIMER_ST_INT_CAP1: capture 1 interrupt, for Slave_TIMER
2470 \arg SHRTIMER_ST_INT_CH0OA: channel 0 output active interrupt, for Slave_TIMER
2471 \arg SHRTIMER_ST_INT_CH0ONA: channel 0 output inactive interrupt, for Slave_TIMER
2472 \arg SHRTIMER_ST_INT_CH1OA: channel 1 output active interrupt, for Slave_TIMER
2473 \arg SHRTIMER_ST_INT_CH1ONA: channel 1 output inactive interrupt, for Slave_TIMER
2474 \arg SHRTIMER_ST_INT_CNTRST: counter reset interrupt, for Slave_TIMER
2475 \arg SHRTIMER_ST_INT_DLYIDLE: delayed IDLE mode entry interrupt, for Slave_TIMER
2476 \param[out] none
2477 \retval none
2478 */
shrtimer_timers_interrupt_enable(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t interrupt)2479 void shrtimer_timers_interrupt_enable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt)
2480 {
2481 switch(timer_id)
2482 {
2483 /* enable the Master_TIMER interrupt */
2484 case SHRTIMER_MASTER_TIMER:
2485 SHRTIMER_MTDMAINTEN(shrtimer_periph) |= interrupt;
2486 break;
2487 /* enable the Slave_TIMER interrupt */
2488 case SHRTIMER_SLAVE_TIMER0:
2489 case SHRTIMER_SLAVE_TIMER1:
2490 case SHRTIMER_SLAVE_TIMER2:
2491 case SHRTIMER_SLAVE_TIMER3:
2492 case SHRTIMER_SLAVE_TIMER4:
2493 SHRTIMER_STXDMAINTEN(shrtimer_periph, timer_id) |= interrupt;
2494 break;
2495
2496 default:
2497 break;
2498 }
2499 }
2500 /*!
2501 \brief disable the Master_TIMER and Slave_TIMER interrupt
2502 \param[in] shrtimer_periph: SHRTIMER0
2503 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
2504 \param[in] interrupt: interrupt source
2505 only one parameter can be selected which is shown as below:
2506 \arg SHRTIMER_MT_ST_INT_CMP0: compare 0 interrupt, for Master_TIMER and Slave_TIMER
2507 \arg SHRTIMER_MT_ST_INT_CMP1: compare 1 interrupt, for Master_TIMER and Slave_TIMER
2508 \arg SHRTIMER_MT_ST_INT_CMP2: compare 2 interrupt, for Master_TIMER and Slave_TIMER
2509 \arg SHRTIMER_MT_ST_INT_CMP3: compare 3 interrupt, for Master_TIMER and Slave_TIMER
2510 \arg SHRTIMER_MT_ST_INT_REP: repetition interrupt, for Master_TIMER and Slave_TIMER
2511 \arg SHRTIMER_MT_INT_SYNI: synchronization input interrupt, for Master_TIMER
2512 \arg SHRTIMER_MT_ST_INT_UPD: update interrupt, for Master_TIMER and Slave_TIMER
2513 \arg SHRTIMER_ST_INT_CAP0: capture 0 interrupt, for Slave_TIMER
2514 \arg SHRTIMER_ST_INT_CAP1: capture 1 interrupt, for Slave_TIMER
2515 \arg SHRTIMER_ST_INT_CH0OA: channel 0 output active interrupt, for Slave_TIMER
2516 \arg SHRTIMER_ST_INT_CH0ONA: channel 0 output inactive interrupt, for Slave_TIMER
2517 \arg SHRTIMER_ST_INT_CH1OA: channel 1 output active interrupt, for Slave_TIMER
2518 \arg SHRTIMER_ST_INT_CH1ONA: channel 1 output inactive interrupt, for Slave_TIMER
2519 \arg SHRTIMER_ST_INT_CNTRST: counter reset interrupt, for Slave_TIMER
2520 \arg SHRTIMER_ST_INT_DLYIDLE: delayed IDLE mode entry interrupt, for Slave_TIMER
2521 \param[out] none
2522 \retval none
2523 */
shrtimer_timers_interrupt_disable(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t interrupt)2524 void shrtimer_timers_interrupt_disable(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt)
2525 {
2526 switch(timer_id)
2527 {
2528 /* disable the Master_TIMER interrupt */
2529 case SHRTIMER_MASTER_TIMER:
2530 SHRTIMER_MTDMAINTEN(shrtimer_periph) &= ~interrupt;
2531 break;
2532 /* disable the Slave_TIMER interrupt */
2533 case SHRTIMER_SLAVE_TIMER0:
2534 case SHRTIMER_SLAVE_TIMER1:
2535 case SHRTIMER_SLAVE_TIMER2:
2536 case SHRTIMER_SLAVE_TIMER3:
2537 case SHRTIMER_SLAVE_TIMER4:
2538 SHRTIMER_STXDMAINTEN(shrtimer_periph, timer_id) &= ~interrupt;
2539 break;
2540
2541 default:
2542 break;
2543 }
2544 }
2545
2546 /*!
2547 \brief get the Master_TIMER and Slave_TIMER interrupt flag
2548 \param[in] shrtimer_periph: SHRTIMER0
2549 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
2550 \param[in] interrupt: interrupt source
2551 only one parameter can be selected which is shown as below:
2552 \arg SHRTIMER_MT_ST_INT_FLAG_CMP0: compare 0 interrupt flag, for Master_TIMER and Slave_TIMER
2553 \arg SHRTIMER_MT_ST_INT_FLAG_CMP1: compare 1 interrupt flag, for Master_TIMER and Slave_TIMER
2554 \arg SHRTIMER_MT_ST_INT_FLAG_CMP2: compare 2 interrupt flag, for Master_TIMER and Slave_TIMER
2555 \arg SHRTIMER_MT_ST_INT_FLAG_CMP3: compare 3 interrupt flag, for Master_TIMER and Slave_TIMER
2556 \arg SHRTIMER_MT_ST_INT_FLAG_REP: repetition interrupt flag, for Master_TIMER and Slave_TIMER
2557 \arg SHRTIMER_MT_INT_FLAG_SYNI: synchronization input interrupt flag, for Master_TIMER
2558 \arg SHRTIMER_MT_ST_INT_FLAG_UPD: update interrupt flag, for Master_TIMER and Slave_TIMER
2559 \arg SHRTIMER_ST_INT_FLAG_CAP0: capture 0 interrupt flag, for Slave_TIMER
2560 \arg SHRTIMER_ST_INT_FLAG_CAP1: capture 1 interrupt flag, for Slave_TIMER
2561 \arg SHRTIMER_ST_INT_FLAG_CH0OA: channel 0 output active interrupt flag, for Slave_TIMER
2562 \arg SHRTIMER_ST_INT_FLAG_CH0ONA: channel 0 output inactive interrupt flag, for Slave_TIMER
2563 \arg SHRTIMER_ST_INT_FLAG_CH1OA: channel 1 output active interrupt flag, for Slave_TIMER
2564 \arg SHRTIMER_ST_INT_FLAG_CH1ONA: channel 1 output inactive interrupt flag, for Slave_TIMER
2565 \arg SHRTIMER_ST_INT_FLAG_CNTRST: counter reset interrupt flag, for Slave_TIMER
2566 \arg SHRTIMER_ST_INT_FLAG_DLYIDLE: delayed IDLE mode entry interrupt flag, for Slave_TIMER
2567 \param[out] none
2568 \retval FlagStatus: SET or RESET
2569 */
shrtimer_timers_interrupt_flag_get(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t interrupt)2570 FlagStatus shrtimer_timers_interrupt_flag_get(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt)
2571 {
2572 FlagStatus flag = RESET;
2573 uint32_t interflag = 0U;
2574 uint32_t interen = 0U;
2575
2576 switch(timer_id)
2577 {
2578 /* get the Master_TIMER interrupt flag */
2579 case SHRTIMER_MASTER_TIMER:
2580 interflag = (SHRTIMER_MTINTF(shrtimer_periph) & interrupt);
2581 interen = (SHRTIMER_MTDMAINTEN(shrtimer_periph) & interrupt);
2582 if((RESET != interflag) && (RESET != interen)){
2583 flag = SET;
2584 }else{
2585 flag = RESET;
2586 }
2587 break;
2588 /* get the Slave_TIMER interrupt flag */
2589 case SHRTIMER_SLAVE_TIMER0:
2590 case SHRTIMER_SLAVE_TIMER1:
2591 case SHRTIMER_SLAVE_TIMER2:
2592 case SHRTIMER_SLAVE_TIMER3:
2593 case SHRTIMER_SLAVE_TIMER4:
2594 interflag = (SHRTIMER_STXINTF(shrtimer_periph, timer_id) & interrupt);
2595 interen = (SHRTIMER_STXDMAINTEN(shrtimer_periph, timer_id) & interrupt);
2596 if((RESET != interflag) && (RESET != interen)){
2597 flag = SET;
2598 }else{
2599 flag = RESET;
2600 }
2601 break;
2602
2603 default:
2604 break;
2605 }
2606 return flag;
2607 }
2608
2609 /*!
2610 \brief clear the Master_TIMER and Slave_TIMER interrupt flag
2611 \param[in] shrtimer_periph: SHRTIMER0
2612 \param[in] timer_id: SHRTIMER_MASTER_TIMER, SHRTIMER_SLAVE_TIMERx(x=0..4)
2613 \param[in] interrupt: interrupt source
2614 only one parameter can be selected which is shown as below:
2615 \arg SHRTIMER_MT_ST_INT_FLAG_CMP0: compare 0 interrupt flag, for Master_TIMER and Slave_TIMER
2616 \arg SHRTIMER_MT_ST_INT_FLAG_CMP1: compare 1 interrupt flag, for Master_TIMER and Slave_TIMER
2617 \arg SHRTIMER_MT_ST_INT_FLAG_CMP2: compare 2 interrupt flag, for Master_TIMER and Slave_TIMER
2618 \arg SHRTIMER_MT_ST_INT_FLAG_CMP3: compare 3 interrupt flag, for Master_TIMER and Slave_TIMER
2619 \arg SHRTIMER_MT_ST_INT_FLAG_REP: repetition interrupt flag, for Master_TIMER and Slave_TIMER
2620 \arg SHRTIMER_MT_INT_FLAG_SYNI: synchronization input interrupt flag, for Master_TIMER
2621 \arg SHRTIMER_MT_ST_INT_FLAG_UPD: update interrupt flag, for Master_TIMER and Slave_TIMER
2622 \arg SHRTIMER_ST_INT_FLAG_CAP0: capture 0 interrupt flag, for Slave_TIMER
2623 \arg SHRTIMER_ST_INT_FLAG_CAP1: capture 1 interrupt flag, for Slave_TIMER
2624 \arg SHRTIMER_ST_INT_FLAG_CH0OA: channel 0 output active interrupt flag, for Slave_TIMER
2625 \arg SHRTIMER_ST_INT_FLAG_CH0ONA: channel 0 output inactive interrupt flag, for Slave_TIMER
2626 \arg SHRTIMER_ST_INT_FLAG_CH1OA: channel 1 output active interrupt flag, for Slave_TIMER
2627 \arg SHRTIMER_ST_INT_FLAG_CH1ONA: channel 1 output inactive interrupt flag, for Slave_TIMER
2628 \arg SHRTIMER_ST_INT_FLAG_CNTRST: counter reset interrupt flag, for Slave_TIMER
2629 \arg SHRTIMER_ST_INT_FLAG_DLYIDLE: delayed IDLE mode entry interrupt flag, for Slave_TIMER
2630 \param[out] none
2631 \retval none
2632 */
shrtimer_timers_interrupt_flag_clear(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t interrupt)2633 void shrtimer_timers_interrupt_flag_clear(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t interrupt)
2634 {
2635 switch(timer_id)
2636 {
2637 /* clear the Master_TIMER interrupt flag */
2638 case SHRTIMER_MASTER_TIMER:
2639 SHRTIMER_MTINTC(shrtimer_periph) |= interrupt;
2640 break;
2641 /* clear theSlave_TIMER interrupt flag */
2642 case SHRTIMER_SLAVE_TIMER0:
2643 case SHRTIMER_SLAVE_TIMER1:
2644 case SHRTIMER_SLAVE_TIMER2:
2645 case SHRTIMER_SLAVE_TIMER3:
2646 case SHRTIMER_SLAVE_TIMER4:
2647 SHRTIMER_STXINTC(shrtimer_periph, timer_id) |= interrupt;
2648 break;
2649
2650 default:
2651 break;
2652 }
2653 }
2654
2655 /*!
2656 \brief enable SHRTIMER common interrupt
2657 \param[in] shrtimer_periph: SHRTIMER0
2658 \param[in] interrupt: interrupt source
2659 only one parameter can be selected which is shown as below:
2660 \arg SHRTIMER_INT_SYSFLT: system fault interrupt
2661 \arg SHRTIMER_INT_DLLCAL: DLL calibration completed interrupt
2662 \arg SHRTIMER_INT_BMPER: bunch mode period interrupt
2663 \param[out] none
2664 \retval none
2665 */
shrtimer_common_interrupt_enable(uint32_t shrtimer_periph,uint32_t interrupt)2666 void shrtimer_common_interrupt_enable(uint32_t shrtimer_periph, uint32_t interrupt)
2667 {
2668 SHRTIMER_INTEN(shrtimer_periph) |= interrupt;
2669 }
2670
2671 /*!
2672 \brief disable SHRTIMER common interrupt
2673 \param[in] shrtimer_periph: SHRTIMER0
2674 \param[in] interrupt: interrupt source
2675 only one parameter can be selected which is shown as below:
2676 \arg SHRTIMER_INT_FLT0: fault 0 interrupt
2677 \arg SHRTIMER_INT_FLT1: fault 1 interrupt
2678 \arg SHRTIMER_INT_FLT2: fault 2 interrupt
2679 \arg SHRTIMER_INT_FLT3: fault 3 interrupt
2680 \arg SHRTIMER_INT_FLT4: fault 4 interrupt
2681 \arg SHRTIMER_INT_SYSFLT: system fault interrupt
2682 \arg SHRTIMER_INT_DLLCAL: DLL calibration completed interrupt
2683 \arg SHRTIMER_INT_BMPER: bunch mode period interrupt
2684 \param[out] none
2685 \retval none
2686 */
shrtimer_common_interrupt_disable(uint32_t shrtimer_periph,uint32_t interrupt)2687 void shrtimer_common_interrupt_disable(uint32_t shrtimer_periph, uint32_t interrupt)
2688 {
2689 SHRTIMER_INTEN(shrtimer_periph) &= ~interrupt;
2690 }
2691
2692 /*!
2693 \brief get the common interrupt flag
2694 \param[in] shrtimer_periph: SHRTIMER0
2695 \param[in] interrupt: interrupt source
2696 only one parameter can be selected which is shown as below:
2697 \arg SHRTIMER_INT_FLAG_FLT0: fault 0 interrupt flag
2698 \arg SHRTIMER_INT_FLAG_FLT1: fault 1 interrupt flag
2699 \arg SHRTIMER_INT_FLAG_FLT2: fault 2 interrupt flag
2700 \arg SHRTIMER_INT_FLAG_FLT3: fault 3 interrupt flag
2701 \arg SHRTIMER_INT_FLAG_FLT4: fault 4 interrupt flag
2702 \arg SHRTIMER_INT_FLAG_SYSFLT: system fault interrupt flag
2703 \arg SHRTIMER_INT_FLAG_DLLCAL: DLL calibration completed interrupt flag
2704 \arg SHRTIMER_INT_FLAG_BMPER: bunch mode period interrupt flag
2705 \param[out] none
2706 \retval FlagStatus: SET or RESET
2707 */
shrtimer_common_interrupt_flag_get(uint32_t shrtimer_periph,uint32_t interrupt)2708 FlagStatus shrtimer_common_interrupt_flag_get(uint32_t shrtimer_periph, uint32_t interrupt)
2709 {
2710 uint32_t interflag = 0U;
2711 uint32_t interen = 0U;
2712
2713 /* get the interrupt correlation bit value */
2714 interflag = (SHRTIMER_INTF(shrtimer_periph) & interrupt);
2715 interen = (SHRTIMER_INTEN(shrtimer_periph) & interrupt);
2716
2717 /* get the interrupt flag */
2718 if((RESET != interflag) && (RESET != interen)){
2719 return SET;
2720 }else{
2721 return RESET;
2722 }
2723 }
2724
2725 /*!
2726 \brief clear the common interrupt flag
2727 \param[in] shrtimer_periph: SHRTIMER0
2728 \param[in] interrupt: interrupt source
2729 only one parameter can be selected which is shown as below:
2730 \arg SHRTIMER_INT_FLAG_FLT0: fault 0 interrupt flag
2731 \arg SHRTIMER_INT_FLAG_FLT1: fault 1 interrupt flag
2732 \arg SHRTIMER_INT_FLAG_FLT2: fault 2 interrupt flag
2733 \arg SHRTIMER_INT_FLAG_FLT3: fault 3 interrupt flag
2734 \arg SHRTIMER_INT_FLAG_FLT4: fault 4 interrupt flag
2735 \arg SHRTIMER_INT_FLAG_SYSFLT: system fault interrupt flag
2736 \arg SHRTIMER_INT_FLAG_DLLCAL: DLL calibration completed interrupt flag
2737 \arg SHRTIMER_INT_FLAG_BMPER: bunch mode period interrupt flag
2738 \param[out] none
2739 \retval none
2740 */
shrtimer_common_interrupt_flag_clear(uint32_t shrtimer_periph,uint32_t interrupt)2741 void shrtimer_common_interrupt_flag_clear(uint32_t shrtimer_periph, uint32_t interrupt)
2742 {
2743 SHRTIMER_INTC(shrtimer_periph) |= interrupt;
2744 }
2745
2746 /*!
2747 \brief configure Master_TIMER timer base
2748 \param[in] shrtimer_periph: SHRTIMER0
2749 \param[in] master_baseinit: SHRTIMER time base parameters struct
2750 period: period value, min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
2751 repetitioncounter: the counter repetition value, 0x00~0xFF
2752 prescaler: SHRTIMER_PRESCALER_MULy(y=64,32,16,8,4,2),SHRTIMER_PRESCALER_DIVy(y=1,2,4)
2753 counter_mode: SHRTIMER_COUNTER_MODE_CONTINOUS, SHRTIMER_COUNTER_MODE_SINGLEPULSE, SHRTIMER_COUNTER_MODE_SINGLEPULSE_RETRIGGERABLE
2754 \param[out] none
2755 \retval none
2756 */
master_timer_base_config(uint32_t shrtimer_periph,shrtimer_baseinit_parameter_struct * master_baseinit)2757 static void master_timer_base_config(uint32_t shrtimer_periph, shrtimer_baseinit_parameter_struct* master_baseinit)
2758 {
2759 /* set counter clock division */
2760 SHRTIMER_MTCTL0(shrtimer_periph) &= (uint32_t) ~(SHRTIMER_MTCTL0_CNTCKDIV2_0);
2761 SHRTIMER_MTACTL(shrtimer_periph) &= (uint32_t) ~(SHRTIMER_MTACTL_CNTCKDIV3);
2762 SHRTIMER_MTCTL0(shrtimer_periph) |= (uint32_t)((master_baseinit->prescaler) & CNTCKDIV2_0_MASK);
2763 SHRTIMER_MTACTL(shrtimer_periph) |= (uint32_t)((master_baseinit->prescaler) & CNTCKDIV3_MASK);
2764
2765 /* set the counter operating mode */
2766 SHRTIMER_MTCTL0(shrtimer_periph) &= (uint32_t) ~(SHRTIMER_STXCTL0_CTNM | SHRTIMER_STXCTL0_CNTRSTM);
2767 SHRTIMER_MTCTL0(shrtimer_periph) |= (uint32_t)master_baseinit->counter_mode;
2768
2769 /* set the period and repetition registers */
2770 SHRTIMER_MTCAR(shrtimer_periph) = master_baseinit->period;
2771 SHRTIMER_MTCREP(shrtimer_periph) = master_baseinit->repetitioncounter;
2772 }
2773
2774 /*!
2775 \brief configure Master_TIMER in waveform mode
2776 \param[in] shrtimer_periph: SHRTIMER0
2777 \param[in] master_timerinit: waveform mode initialization parameters
2778 half_mode: SHRTIMER_HALFMODE_DISABLED, SHRTIMER_HALFMODE_ENABLED
2779 start_sync: SHRTIMER_SYNISTART_DISABLED, SHRTIMER_SYNISTART_ENABLED
2780 reset_sync: SHRTIMER_SYNCRESET_DISABLED, SHRTIMER_SYNCRESET_ENABLED
2781 dac_trigger: SHRTIMER_DAC_TRIGGER_NONE, SHRTIMER_DAC_TRIGGER_DACTRIGy(y=0..2)
2782 shadow: SHRTIMER_SHADOW_DISABLED, SHRTIMER_SHADOW_ENABLED
2783 update_selection: SHRTIMER_MT_ST_UPDATE_SELECTION_INDEPENDENT, SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE, SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE_UPDATE
2784 cnt_bunch: SHRTIMER_TIMERBUNCHNMODE_MAINTAINCLOCK, SHRTIMER_TIMERBUNCHMODE_RESETCOUNTER
2785 repetition_update: SHRTIMER_UPDATEONREPETITION_DISABLED, SHRTIMER_UPDATEONREPETITION_ENABLED
2786 \param[out] none
2787 \retval none
2788 */
master_timer_waveform_config(uint32_t shrtimer_periph,shrtimer_timerinit_parameter_struct * master_timerinit)2789 static void master_timer_waveform_config(uint32_t shrtimer_periph, shrtimer_timerinit_parameter_struct * master_timerinit)
2790 {
2791 uint32_t mtctl0_reg;
2792 uint32_t bmctl_reg;
2793
2794 mtctl0_reg = SHRTIMER_MTCTL0(shrtimer_periph);
2795 bmctl_reg = SHRTIMER_BMCTL(shrtimer_periph);
2796
2797 /* configure the half mode */
2798 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_HALFM);
2799 mtctl0_reg |= master_timerinit->half_mode;
2800
2801 /* configure synchronization input start counter */
2802 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_SYNISTRT);
2803 mtctl0_reg |= master_timerinit->start_sync;
2804
2805 /* configure synchronization input reset counter */
2806 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_SYNIRST);
2807 mtctl0_reg |= master_timerinit->reset_sync;
2808
2809 /* configure trigger source to DAC */
2810 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_DACTRGS);
2811 mtctl0_reg |= master_timerinit->dac_trigger;
2812
2813 /* enable/disable shadow registers */
2814 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_SHWEN);
2815 mtctl0_reg |= master_timerinit->shadow;
2816
2817 /* update event selection */
2818 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_UPSEL);
2819 mtctl0_reg |= (master_timerinit->update_selection << 2);
2820
2821 /* enable/disable registers update on repetition event */
2822 mtctl0_reg &= ~(uint32_t)(SHRTIMER_MTCTL0_UPREP);
2823 mtctl0_reg |= (master_timerinit->repetition_update);
2824
2825 /* set the timer bunch mode */
2826 bmctl_reg &= ~(SHRTIMER_BMCTL_BMMT);
2827 bmctl_reg |= master_timerinit->cnt_bunch;
2828
2829 SHRTIMER_MTCTL0(shrtimer_periph) = mtctl0_reg;
2830 SHRTIMER_BMCTL(shrtimer_periph) = bmctl_reg;
2831 }
2832
2833 /*!
2834 \brief configure Slave_TIMER timer base
2835 \param[in] shrtimer_periph: SHRTIMER0
2836 \param[in] slave_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
2837 \param[in] slave_baseinit: SHRTIMER time base parameters struct
2838 period: period value, min value: 3*tSHRTIMER_CK clock, max value: 0xFFFF �C (1*tSHRTIMER_CK)
2839 repetitioncounter: the counter repetition value, 0x00~0xFF
2840 prescaler: SHRTIMER_PRESCALER_MULy(y=64,32,16,8,4,2),SHRTIMER_PRESCALER_DIVy(y=1,2,4)
2841 counter_mode: SHRTIMER_COUNTER_MODE_CONTINOUS, SHRTIMER_COUNTER_MODE_SINGLEPULSE, SHRTIMER_COUNTER_MODE_SINGLEPULSE_RETRIGGERABLE
2842 \param[out] none
2843 \retval none
2844 */
slave_timer_base_config(uint32_t shrtimer_periph,uint32_t slave_id,shrtimer_baseinit_parameter_struct * slave_baseinit)2845 static void slave_timer_base_config(uint32_t shrtimer_periph, uint32_t slave_id, shrtimer_baseinit_parameter_struct* slave_baseinit)
2846 {
2847 /* set counter clock division */
2848 SHRTIMER_STXCTL0(shrtimer_periph, slave_id) &= (uint32_t) ~(SHRTIMER_MTCTL0_CNTCKDIV2_0);
2849 SHRTIMER_STXACTL(shrtimer_periph, slave_id) &= (uint32_t) ~(SHRTIMER_MTACTL_CNTCKDIV3);
2850 SHRTIMER_STXCTL0(shrtimer_periph, slave_id) |= (uint32_t)((slave_baseinit->prescaler) & CNTCKDIV2_0_MASK);
2851 SHRTIMER_STXACTL(shrtimer_periph, slave_id) |= (uint32_t)((slave_baseinit->prescaler) & CNTCKDIV3_MASK);
2852
2853 /* set the counter operating mode */
2854 SHRTIMER_STXCTL0(shrtimer_periph, slave_id) &= (uint32_t) ~(SHRTIMER_STXCTL0_CTNM | SHRTIMER_STXCTL0_CNTRSTM);
2855 SHRTIMER_STXCTL0(shrtimer_periph, slave_id) |= (uint32_t)slave_baseinit->counter_mode;
2856
2857 /* set the period and repetition registers */
2858 SHRTIMER_STXCAR(shrtimer_periph, slave_id) = slave_baseinit->period;
2859 SHRTIMER_STXCREP(shrtimer_periph, slave_id) = slave_baseinit->repetitioncounter;
2860 }
2861
2862 /*!
2863 \brief configure Slave_TIMER in waveform mode
2864 \param[in] shrtimer_periph: SHRTIMER0
2865 \param[in] slave_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
2866 \param[in] slave_timerinit: waveform mode initialization parameters
2867 half_mode: SHRTIMER_HALFMODE_DISABLED, SHRTIMER_HALFMODE_ENABLED
2868 start_sync: SHRTIMER_SYNISTART_DISABLED, SHRTIMER_SYNISTART_ENABLED
2869 reset_sync: SHRTIMER_SYNCRESET_DISABLED, SHRTIMER_SYNCRESET_ENABLED
2870 dac_trigger: SHRTIMER_DAC_TRIGGER_NONE, SHRTIMER_DAC_TRIGGER_DACTRIGy(y=0..2)
2871 shadow: SHRTIMER_SHADOW_DISABLED, SHRTIMER_SHADOW_ENABLED
2872 update_selection: SHRTIMER_MT_ST_UPDATE_SELECTION_INDEPENDENT, for Master_TIMER and Slave_TIMER
2873 SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE, for Master_TIMER and Slave_TIMER
2874 SHRTIMER_MT_ST_UPDATE_SELECTION_DMAMODE_UPDATE, for Master_TIMER and Slave_TIMER
2875 SHRTIMER_ST_UPDATE_SELECTION_STXUPINy(y=2), for Slave_TIMER
2876 SHRTIMER_ST_UPDATE_SELECTION_STXUPINy_UPDATE(y=2), for Slave_TIMER
2877 cnt_bunch: SHRTIMER_TIMERBUNCHNMODE_MAINTAINCLOCK, SHRTIMER_TIMERBUNCHMODE_RESETCOUNTER
2878 repetition_update: SHRTIMER_UPDATEONREPETITION_DISABLED, SHRTIMER_UPDATEONREPETITION_ENABLED
2879 \param[out] none
2880 \retval none
2881 */
slave_timer_waveform_config(uint32_t shrtimer_periph,uint32_t slave_id,shrtimer_timerinit_parameter_struct * slave_timerinit)2882 static void slave_timer_waveform_config(uint32_t shrtimer_periph, uint32_t slave_id, shrtimer_timerinit_parameter_struct * slave_timerinit)
2883 {
2884 uint32_t stxctl0_reg;
2885 uint32_t bmctl_reg;
2886
2887 stxctl0_reg = SHRTIMER_STXCTL0(shrtimer_periph, slave_id);
2888 bmctl_reg = SHRTIMER_BMCTL(shrtimer_periph);
2889
2890 /* configure the half mode */
2891 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_HALFM);
2892 stxctl0_reg |= slave_timerinit->half_mode;
2893
2894 /* configure synchronization input start counter */
2895 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_SYNISTRT);
2896 stxctl0_reg |= slave_timerinit->start_sync;
2897
2898 /* configure synchronization input reset counter */
2899 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_SYNIRST);
2900 stxctl0_reg |= slave_timerinit->reset_sync;
2901
2902 /* configure trigger source to DAC */
2903 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_DACTRGS);
2904 stxctl0_reg |= slave_timerinit->dac_trigger;
2905
2906 /* enable/disable shadow registers */
2907 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_SHWEN);
2908 stxctl0_reg |= slave_timerinit->shadow;
2909
2910 /* update event selection */
2911 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_UPSEL);
2912 stxctl0_reg |= (slave_timerinit->update_selection);
2913
2914 /* enable/disable registers update on repetition event */
2915 stxctl0_reg &= ~(uint32_t)(SHRTIMER_STXCTL0_UPREP);
2916 if(SHRTIMER_UPDATEONREPETITION_ENABLED == slave_timerinit->repetition_update){
2917 stxctl0_reg |= (SHRTIMER_STXCTL0_UPREP);
2918 }
2919
2920 /* Set the timer bunch mode */
2921 switch (slave_id)
2922 {
2923 case SHRTIMER_SLAVE_TIMER0:
2924 {
2925 bmctl_reg &= ~(SHRTIMER_BMCTL_BMST0);
2926 bmctl_reg |= (slave_timerinit->cnt_bunch << 1);
2927 }
2928 break;
2929 case SHRTIMER_SLAVE_TIMER1:
2930 {
2931 bmctl_reg &= ~(SHRTIMER_BMCTL_BMST1);
2932 bmctl_reg |= (slave_timerinit->cnt_bunch << 2);
2933 }
2934 break;
2935 case SHRTIMER_SLAVE_TIMER2:
2936 {
2937 bmctl_reg &= ~(SHRTIMER_BMCTL_BMST2);
2938 bmctl_reg |= (slave_timerinit->cnt_bunch << 3);
2939 }
2940 break;
2941 case SHRTIMER_SLAVE_TIMER3:
2942 {
2943 bmctl_reg &= ~(SHRTIMER_BMCTL_BMST3);
2944 bmctl_reg |= (slave_timerinit->cnt_bunch << 4);
2945 }
2946 break;
2947 case SHRTIMER_SLAVE_TIMER4:
2948 {
2949 bmctl_reg &= ~(SHRTIMER_BMCTL_BMST4);
2950 bmctl_reg |= (slave_timerinit->cnt_bunch << 5);
2951 }
2952 break;
2953 default:
2954 break;
2955 }
2956
2957 SHRTIMER_STXCTL0(shrtimer_periph, slave_id) = stxctl0_reg;
2958 SHRTIMER_BMCTL(shrtimer_periph) = bmctl_reg;
2959 }
2960
2961 /*!
2962 \brief configure the an external event channel
2963 \param[in] shrtimer_periph: SHRTIMER0
2964 \param[in] event_id: SHRTIMER_EXEVENT_NONE, SHRTIMER_EXEVENT_y(y=0..9)
2965 \param[in] eventcfg: external event configuration struct
2966 source: SHRTIMER_EXEV_SRCy(y=0..3)
2967 polarity: SHRTIMER_EXEV_POLARITY_HIGH, SHRTIMER_EXEV_POLARITY_LOW
2968 edge: SHRTIMER_EXEV_EDGE_LEVEL, SHRTIMER_EXEV_EDGE_RISING, SHRTIMER_EXEV_EDGE_FALLING, SHRTIMER_EXEV_EDGE_BOTH
2969 digital_filter: 0x0~0xF
2970 \param[out] none
2971 \retval none
2972 */
external_event_config(uint32_t shrtimer_periph,uint32_t event_id,shrtimer_exeventcfg_parameter_struct * eventcfg)2973 static void external_event_config(uint32_t shrtimer_periph, uint32_t event_id, shrtimer_exeventcfg_parameter_struct* eventcfg)
2974 {
2975 uint32_t exevcfg0_reg;
2976 uint32_t exevcfg1_reg;
2977 uint32_t exevdfctl_reg;
2978
2979 exevcfg0_reg = SHRTIMER_EXEVCFG0(shrtimer_periph);
2980 exevcfg1_reg = SHRTIMER_EXEVCFG1(shrtimer_periph);
2981 exevdfctl_reg = SHRTIMER_EXEVDFCTL(shrtimer_periph);
2982
2983 switch (event_id)
2984 {
2985 case SHRTIMER_EXEVENT_0:
2986 {
2987 /* configure external event 0 */
2988 exevcfg0_reg &= ~(SHRTIMER_EXEVCFG0_EXEV0SRC | SHRTIMER_EXEVCFG0_EXEV0P | SHRTIMER_EXEVCFG0_EXEV0EG);
2989 exevcfg0_reg |= eventcfg->source;
2990 exevcfg0_reg |= eventcfg->polarity;
2991 exevcfg0_reg |= eventcfg->edge;
2992 SHRTIMER_EXEVCFG0(shrtimer_periph) = exevcfg0_reg;
2993 }
2994 break;
2995 case SHRTIMER_EXEVENT_1:
2996 {
2997 /* configure external event 1 */
2998 exevcfg0_reg &= ~(SHRTIMER_EXEVCFG0_EXEV1SRC | SHRTIMER_EXEVCFG0_EXEV1P | SHRTIMER_EXEVCFG0_EXEV1EG);
2999 exevcfg0_reg |= ((eventcfg->source) << 6);
3000 exevcfg0_reg |= ((eventcfg->polarity) << 6);
3001 exevcfg0_reg |= ((eventcfg->edge) << 6);
3002 SHRTIMER_EXEVCFG0(shrtimer_periph) = exevcfg0_reg;
3003 }
3004 break;
3005 case SHRTIMER_EXEVENT_2:
3006 {
3007 /* configure external event 2 */
3008 exevcfg0_reg &= ~(SHRTIMER_EXEVCFG0_EXEV2SRC | SHRTIMER_EXEVCFG0_EXEV2P | SHRTIMER_EXEVCFG0_EXEV2EG);
3009 exevcfg0_reg |= ((eventcfg->source) << 12);
3010 exevcfg0_reg |= ((eventcfg->polarity) << 12);
3011 exevcfg0_reg |= ((eventcfg->edge) << 12);
3012 SHRTIMER_EXEVCFG0(shrtimer_periph) = exevcfg0_reg;
3013 }
3014 break;
3015 case SHRTIMER_EXEVENT_3:
3016 {
3017 /* configure external event 3 */
3018 exevcfg0_reg &= ~(SHRTIMER_EXEVCFG0_EXEV3SRC | SHRTIMER_EXEVCFG0_EXEV3P | SHRTIMER_EXEVCFG0_EXEV3EG);
3019 exevcfg0_reg |= ((eventcfg->source) << 18);
3020 exevcfg0_reg |= ((eventcfg->polarity) << 18);
3021 exevcfg0_reg |= ((eventcfg->edge) << 18);
3022 SHRTIMER_EXEVCFG0(shrtimer_periph) = exevcfg0_reg;
3023 }
3024 break;
3025 case SHRTIMER_EXEVENT_4:
3026 {
3027 /* configure external event 4 */
3028 exevcfg0_reg &= ~(SHRTIMER_EXEVCFG0_EXEV4SRC | SHRTIMER_EXEVCFG0_EXEV4P | SHRTIMER_EXEVCFG0_EXEV4EG);
3029 exevcfg0_reg |= ((eventcfg->source) << 24);
3030 exevcfg0_reg |= ((eventcfg->polarity) << 24);
3031 exevcfg0_reg |= ((eventcfg->edge) << 24);
3032 SHRTIMER_EXEVCFG0(shrtimer_periph) = exevcfg0_reg;
3033 }
3034 break;
3035 case SHRTIMER_EXEVENT_5:
3036 {
3037 /* configure external event 5 */
3038 exevcfg1_reg &= ~(SHRTIMER_EXEVCFG1_EXEV5SRC | SHRTIMER_EXEVCFG1_EXEV5P | SHRTIMER_EXEVCFG1_EXEV5EG);
3039 exevcfg1_reg |= (eventcfg->source);
3040 exevcfg1_reg |= (eventcfg->polarity);
3041 exevcfg1_reg |= (eventcfg->edge);
3042 exevdfctl_reg &= ~(SHRTIMER_EXEVDFCTL_EXEV5FC);
3043 exevdfctl_reg |= (eventcfg->digital_filter);
3044 SHRTIMER_EXEVCFG1(shrtimer_periph) = exevcfg1_reg;
3045 SHRTIMER_EXEVDFCTL(shrtimer_periph) = exevdfctl_reg;
3046 }
3047 break;
3048 case SHRTIMER_EXEVENT_6:
3049 {
3050 /* configure external event 6 */
3051 exevcfg1_reg &= ~(SHRTIMER_EXEVCFG1_EXEV6SRC | SHRTIMER_EXEVCFG1_EXEV6P | SHRTIMER_EXEVCFG1_EXEV6EG);
3052 exevcfg1_reg |= ((eventcfg->source) << 6);
3053 exevcfg1_reg |= ((eventcfg->polarity) << 6);
3054 exevcfg1_reg |= ((eventcfg->edge) << 6);
3055 exevdfctl_reg &= ~(SHRTIMER_EXEVDFCTL_EXEV6FC);
3056 exevdfctl_reg |= ((eventcfg->digital_filter) << 6);
3057 SHRTIMER_EXEVCFG1(shrtimer_periph) = exevcfg1_reg;
3058 SHRTIMER_EXEVDFCTL(shrtimer_periph) = exevdfctl_reg;
3059 }
3060 break;
3061 case SHRTIMER_EXEVENT_7:
3062 {
3063 /* configure external event 7 */
3064 exevcfg1_reg &= ~(SHRTIMER_EXEVCFG1_EXEV7SRC | SHRTIMER_EXEVCFG1_EXEV7P | SHRTIMER_EXEVCFG1_EXEV7EG);
3065 exevcfg1_reg |= ((eventcfg->source) << 12);
3066 exevcfg1_reg |= ((eventcfg->polarity) << 12);
3067 exevcfg1_reg |= ((eventcfg->edge) << 12);
3068 exevdfctl_reg &= ~(SHRTIMER_EXEVDFCTL_EXEV7FC);
3069 exevdfctl_reg |= ((eventcfg->digital_filter) << 12);
3070 SHRTIMER_EXEVCFG1(shrtimer_periph) = exevcfg1_reg;
3071 SHRTIMER_EXEVDFCTL(shrtimer_periph) = exevdfctl_reg;
3072 }
3073 break;
3074 case SHRTIMER_EXEVENT_8:
3075 {
3076 /* configure external event 8 */
3077 exevcfg1_reg &= ~(SHRTIMER_EXEVCFG1_EXEV8SRC | SHRTIMER_EXEVCFG1_EXEV8P | SHRTIMER_EXEVCFG1_EXEV8EG);
3078 exevcfg1_reg |= ((eventcfg->source) << 18);
3079 exevcfg1_reg |= ((eventcfg->polarity) << 18);
3080 exevcfg1_reg |= ((eventcfg->edge) << 18);
3081 exevdfctl_reg &= ~(SHRTIMER_EXEVDFCTL_EXEV8FC);
3082 exevdfctl_reg |= ((eventcfg->digital_filter) << 18);
3083 SHRTIMER_EXEVCFG1(shrtimer_periph) = exevcfg1_reg;
3084 SHRTIMER_EXEVDFCTL(shrtimer_periph) = exevdfctl_reg;
3085 }
3086 break;
3087 case SHRTIMER_EXEVENT_9:
3088 {
3089 /* configure external event 9 */
3090 exevcfg1_reg &= ~(SHRTIMER_EXEVCFG1_EXEV9SRC | SHRTIMER_EXEVCFG1_EXEV9P | SHRTIMER_EXEVCFG1_EXEV9EG);
3091 exevcfg1_reg |= ((eventcfg->source) << 24);
3092 exevcfg1_reg |= ((eventcfg->polarity) << 24);
3093 exevcfg1_reg |= ((eventcfg->edge) << 24);
3094 exevdfctl_reg &= ~(SHRTIMER_EXEVDFCTL_EXEV9FC);
3095 exevdfctl_reg |= ((eventcfg->digital_filter) << 24);
3096 SHRTIMER_EXEVCFG1(shrtimer_periph) = exevcfg1_reg;
3097 SHRTIMER_EXEVDFCTL(shrtimer_periph) = exevdfctl_reg;
3098 }
3099 break;
3100 default:
3101 break;
3102 }
3103 }
3104
3105
3106 /*!
3107 \brief configure the channel output
3108 \param[in] shrtimer_periph: SHRTIMER0
3109 \param[in] timer_id: SHRTIMER_SLAVE_TIMERx(x=0..4)
3110 \param[in] channel: SHRTIMER_STx_CHy(x=0..4,y=0,1)
3111 \param[in] outcfg: channel output configuration struct definitions
3112 polarity: SHRTIMER_CHANNEL_POLARITY_HIGH, SHRTIMER_CHANNEL_POLARITY_LOW
3113 set_request: SHRTIMER_CHANNEL_SET_NONE, SHRTIMER_CHANNEL_SET_RSTSYNI, SHRTIMER_CHANNEL_SET_PER, SHRTIMER_CHANNEL_SET_CMPy(y=0..3),
3114 SHRTIMER_CHANNEL_SET_MTPER, SHRTIMER_CHANNEL_SET_MTCMPy(y=0..3), SHRTIMER_CHANNEL_SET_STEVy(y=0..8),
3115 SHRTIMER_CHANNEL_SET_EXEVy(y=0..9), SHRTIMER_CHANNEL_SET_UPDATE
3116 reset_request: SHRTIMER_CHANNEL_RESET_NONE, SHRTIMER_CHANNEL_RESET_RSTSYNI, SHRTIMER_CHANNEL_RESET_PER, SHRTIMER_CHANNEL_RESET_CMPy(y=0..3),
3117 SHRTIMER_CHANNEL_RESET_MTPER, SHRTIMER_CHANNEL_RESET_MTCMPy(y=0..3), SHRTIMER_CHANNEL_RESET_STEVy(y=0..8),
3118 SHRTIMER_CHANNEL_RESET_EXEVy(y=0..9), SHRTIMER_CHANNEL_RESET_UPDATE
3119 idle_bunch: SHRTIMER_CHANNEL_BUNCH_IDLE_DISABLE, SHRTIMER_CHANNEL_BUNCH_IDLE_ENABLE
3120 idle_state: SHRTIMER_CHANNEL_IDLESTATE_INACTIVE, SHRTIMER_CHANNEL_IDLESTATE_ACTIVE
3121 fault_state: SHRTIMER_CHANNEL_FAULTSTATE_NONE, SHRTIMER_CHANNEL_FAULTSTATE_ACTIVE, SHRTIMER_CHANNEL_FAULTSTATE_INACTIVE, SHRTIMER_CHANNEL_FAULTSTATE_HIGHZ
3122 carrier_mode: SHRTIMER_CHANNEL_CARRIER_DISABLED, SHRTIMER_CHANNEL_CARRIER_ENABLED
3123 deadtime_bunch: SHRTIMER_CHANNEL_BUNCH_ENTRY_REGULAR, SHRTIMER_CHANNEL_BUNCH_ENTRY_DEADTIME
3124 \param[out] none
3125 \retval none
3126 */
channel_output_config(uint32_t shrtimer_periph,uint32_t timer_id,uint32_t channel,shrtimer_channel_outputcfg_parameter_struct * outcfg)3127 static void channel_output_config(uint32_t shrtimer_periph, uint32_t timer_id, uint32_t channel, shrtimer_channel_outputcfg_parameter_struct * outcfg)
3128 {
3129 uint32_t stxchoctl_reg;
3130 uint32_t shift = 0U;
3131
3132 stxchoctl_reg = SHRTIMER_STXCHOCTL(shrtimer_periph, timer_id);
3133 /* configure the output set/reset crossbar */
3134 switch (channel)
3135 {
3136 case SHRTIMER_ST0_CH0:
3137 case SHRTIMER_ST1_CH0:
3138 case SHRTIMER_ST2_CH0:
3139 case SHRTIMER_ST3_CH0:
3140 case SHRTIMER_ST4_CH0:
3141 {
3142 shift = 0U;
3143 SHRTIMER_STXCH0SET(shrtimer_periph, timer_id) = outcfg->set_request;
3144 SHRTIMER_STXCH0RST(shrtimer_periph, timer_id) = outcfg->reset_request;
3145 }
3146 break;
3147 case SHRTIMER_ST0_CH1:
3148 case SHRTIMER_ST1_CH1:
3149 case SHRTIMER_ST2_CH1:
3150 case SHRTIMER_ST3_CH1:
3151 case SHRTIMER_ST4_CH1:
3152 {
3153 shift = 16U;
3154 SHRTIMER_STXCH1SET(shrtimer_periph, timer_id) = outcfg->set_request;
3155 SHRTIMER_STXCH1RST(shrtimer_periph, timer_id) = outcfg->reset_request;
3156 }
3157 break;
3158 default:
3159 break;
3160 }
3161
3162 /* clear output config */
3163 stxchoctl_reg &= ~((SHRTIMER_STXCHOCTL_CH0P | SHRTIMER_STXCHOCTL_BMCH0IEN | SHRTIMER_STXCHOCTL_ISO0 | SHRTIMER_STXCHOCTL_CH0FLTOS|\
3164 SHRTIMER_STXCHOCTL_CH0CSEN | SHRTIMER_STXCHOCTL_BMCH0DTI) << shift);
3165
3166 /* config the polarity */
3167 stxchoctl_reg |= (outcfg->polarity << shift);
3168
3169 /* channel IDLE enable state config in bunch mode */
3170 stxchoctl_reg |= (outcfg->idle_bunch << shift);
3171
3172 /* config channel output IDLE state */
3173 stxchoctl_reg |= (outcfg->idle_state << shift);
3174
3175 /* config the FAULT output state */
3176 stxchoctl_reg |= (outcfg->fault_state << shift);
3177
3178 /* config the channel carrier-signal mode enable state */
3179 stxchoctl_reg |= (outcfg->carrier_mode << shift);
3180
3181 /* config channel dead-time insert in bunch mode */
3182 stxchoctl_reg |= (outcfg->deadtime_bunch << shift);
3183
3184 SHRTIMER_STXCHOCTL(shrtimer_periph, timer_id) = stxchoctl_reg;
3185 }
3186
3187 #endif /* GD32EPRT */
3188
