1 /*
2 * Copyright (c) 2022 STMicroelectronics
3 * Copyright (c) 2022 Georgij Cernysiov
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT st_stm32_ospi_nor
9
10 #include <errno.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/toolchain.h>
13 #include <zephyr/arch/common/ffs.h>
14 #include <zephyr/sys/util.h>
15 #include <soc.h>
16 #include <zephyr/drivers/pinctrl.h>
17 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
18 #include <zephyr/drivers/clock_control.h>
19 #include <zephyr/drivers/flash.h>
20 #include <zephyr/dt-bindings/flash_controller/ospi.h>
21 #include <zephyr/drivers/gpio.h>
22 #include <zephyr/irq.h>
23
24 #include "spi_nor.h"
25 #include "jesd216.h"
26
27 #include "flash_stm32_ospi.h"
28
29 #include <zephyr/logging/log.h>
30 LOG_MODULE_REGISTER(flash_stm32_ospi, CONFIG_FLASH_LOG_LEVEL);
31
32 #define STM32_OSPI_NODE DT_INST_PARENT(0)
33
34 #define DT_OSPI_IO_PORT_PROP_OR(prop, default_value) \
35 COND_CODE_1(DT_NODE_HAS_PROP(STM32_OSPI_NODE, prop), \
36 (_CONCAT(HAL_OSPIM_, DT_STRING_TOKEN(STM32_OSPI_NODE, prop))), \
37 ((default_value)))
38
39 #define DT_OSPI_PROP_OR(prop, default_value) \
40 DT_PROP_OR(STM32_OSPI_NODE, prop, default_value)
41
42 /* Get the base address of the flash from the DTS node */
43 #define STM32_OSPI_BASE_ADDRESS DT_INST_REG_ADDR(0)
44
45 #define STM32_OSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)
46
47 #define STM32_OSPI_DLYB_BYPASSED DT_PROP(STM32_OSPI_NODE, dlyb_bypass)
48
49 #define STM32_OSPI_USE_DMA DT_NODE_HAS_PROP(STM32_OSPI_NODE, dmas)
50
51 #if STM32_OSPI_USE_DMA
52 #include <zephyr/drivers/dma/dma_stm32.h>
53 #include <zephyr/drivers/dma.h>
54 #include <stm32_ll_dma.h>
55 #endif /* STM32_OSPI_USE_DMA */
56
57 #define STM32_OSPI_FIFO_THRESHOLD 4
58
59 #if defined(CONFIG_SOC_SERIES_STM32H5X)
60 /* Valid range is [0, 255] */
61 #define STM32_OSPI_CLOCK_PRESCALER_MIN 0U
62 #define STM32_OSPI_CLOCK_PRESCALER_MAX 255U
63 #define STM32_OSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U))
64 #else
65 /* Valid range is [1, 256] */
66 #define STM32_OSPI_CLOCK_PRESCALER_MIN 1U
67 #define STM32_OSPI_CLOCK_PRESCALER_MAX 256U
68 #define STM32_OSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / (prescaler))
69 #endif
70
71 /* Max Time value during reset or erase operation */
72 #define STM32_OSPI_RESET_MAX_TIME 100U
73 #define STM32_OSPI_BULK_ERASE_MAX_TIME 460000U
74 #define STM32_OSPI_SECTOR_ERASE_MAX_TIME 1000U
75 #define STM32_OSPI_SUBSECTOR_4K_ERASE_MAX_TIME 400U
76 #define STM32_OSPI_WRITE_REG_MAX_TIME 40U
77
78 /* used as default value for DTS writeoc */
79 #define SPI_NOR_WRITEOC_NONE 0xFF
80
81 #if STM32_OSPI_USE_DMA
82 #if CONFIG_DMA_STM32U5
83 static const uint32_t table_src_size[] = {
84 LL_DMA_SRC_DATAWIDTH_BYTE,
85 LL_DMA_SRC_DATAWIDTH_HALFWORD,
86 LL_DMA_SRC_DATAWIDTH_WORD,
87 };
88
89 static const uint32_t table_dest_size[] = {
90 LL_DMA_DEST_DATAWIDTH_BYTE,
91 LL_DMA_DEST_DATAWIDTH_HALFWORD,
92 LL_DMA_DEST_DATAWIDTH_WORD,
93 };
94
95 /* Lookup table to set dma priority from the DTS */
96 static const uint32_t table_priority[] = {
97 LL_DMA_LOW_PRIORITY_LOW_WEIGHT,
98 LL_DMA_LOW_PRIORITY_MID_WEIGHT,
99 LL_DMA_LOW_PRIORITY_HIGH_WEIGHT,
100 LL_DMA_HIGH_PRIORITY,
101 };
102 #else
103 static const uint32_t table_m_size[] = {
104 LL_DMA_MDATAALIGN_BYTE,
105 LL_DMA_MDATAALIGN_HALFWORD,
106 LL_DMA_MDATAALIGN_WORD,
107 };
108
109 static const uint32_t table_p_size[] = {
110 LL_DMA_PDATAALIGN_BYTE,
111 LL_DMA_PDATAALIGN_HALFWORD,
112 LL_DMA_PDATAALIGN_WORD,
113 };
114
115 /* Lookup table to set dma priority from the DTS */
116 static const uint32_t table_priority[] = {
117 DMA_PRIORITY_LOW,
118 DMA_PRIORITY_MEDIUM,
119 DMA_PRIORITY_HIGH,
120 DMA_PRIORITY_VERY_HIGH,
121 };
122 #endif /* CONFIG_DMA_STM32U5 */
123
124 struct stream {
125 DMA_TypeDef *reg;
126 const struct device *dev;
127 uint32_t channel;
128 struct dma_config cfg;
129 };
130 #endif /* STM32_OSPI_USE_DMA */
131
132 typedef void (*irq_config_func_t)(const struct device *dev);
133
134 struct flash_stm32_ospi_config {
135 OCTOSPI_TypeDef *regs;
136 const struct stm32_pclken pclken; /* clock subsystem */
137 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_ker)
138 const struct stm32_pclken pclken_ker; /* clock subsystem */
139 #endif
140 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
141 const struct stm32_pclken pclken_mgr; /* clock subsystem */
142 #endif
143 irq_config_func_t irq_config;
144 size_t flash_size;
145 uint32_t max_frequency;
146 int data_mode; /* SPI or QSPI or OSPI */
147 int data_rate; /* DTR or STR */
148 const struct pinctrl_dev_config *pcfg;
149 #if STM32_OSPI_RESET_GPIO
150 const struct gpio_dt_spec reset;
151 #endif /* STM32_OSPI_RESET_GPIO */
152 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
153 uint8_t sfdp_bfp[DT_INST_PROP_LEN(0, sfdp_bfp)];
154 #endif /* sfdp_bfp */
155 };
156
157 struct flash_stm32_ospi_data {
158 OSPI_HandleTypeDef hospi;
159 struct k_sem sem;
160 struct k_sem sync;
161 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
162 struct flash_pages_layout layout;
163 #endif
164 struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES];
165 /* Number of bytes per page */
166 uint16_t page_size;
167 /* Address width in bytes */
168 uint8_t address_width;
169 /* Read operation dummy cycles */
170 uint8_t read_dummy;
171 uint32_t read_opcode;
172 uint32_t write_opcode;
173 enum jesd216_mode_type read_mode;
174 enum jesd216_dw15_qer_type qer_type;
175 #if defined(CONFIG_FLASH_JESD216_API)
176 /* Table to hold the jedec Read ID given by the octoFlash or the DTS */
177 uint8_t jedec_id[JESD216_READ_ID_LEN];
178 #endif /* CONFIG_FLASH_JESD216_API */
179 int cmd_status;
180 #if STM32_OSPI_USE_DMA
181 struct stream dma;
182 #endif /* STM32_OSPI_USE_DMA */
183 };
184
ospi_lock_thread(const struct device * dev)185 static inline void ospi_lock_thread(const struct device *dev)
186 {
187 struct flash_stm32_ospi_data *dev_data = dev->data;
188
189 k_sem_take(&dev_data->sem, K_FOREVER);
190 }
191
ospi_unlock_thread(const struct device * dev)192 static inline void ospi_unlock_thread(const struct device *dev)
193 {
194 struct flash_stm32_ospi_data *dev_data = dev->data;
195
196 k_sem_give(&dev_data->sem);
197 }
198
ospi_send_cmd(const struct device * dev,OSPI_RegularCmdTypeDef * cmd)199 static int ospi_send_cmd(const struct device *dev, OSPI_RegularCmdTypeDef *cmd)
200 {
201 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
202 struct flash_stm32_ospi_data *dev_data = dev->data;
203 HAL_StatusTypeDef hal_ret;
204
205 LOG_DBG("Instruction 0x%x", cmd->Instruction);
206
207 dev_data->cmd_status = 0;
208
209 hal_ret = HAL_OSPI_Command(&dev_data->hospi, cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
210 if (hal_ret != HAL_OK) {
211 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
212 return -EIO;
213 }
214 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR);
215
216 return dev_data->cmd_status;
217 }
218
ospi_read_access(const struct device * dev,OSPI_RegularCmdTypeDef * cmd,uint8_t * data,size_t size)219 static int ospi_read_access(const struct device *dev, OSPI_RegularCmdTypeDef *cmd,
220 uint8_t *data, size_t size)
221 {
222 struct flash_stm32_ospi_data *dev_data = dev->data;
223 HAL_StatusTypeDef hal_ret;
224
225 LOG_DBG("Instruction 0x%x", cmd->Instruction);
226
227 cmd->NbData = size;
228
229 dev_data->cmd_status = 0;
230
231 hal_ret = HAL_OSPI_Command(&dev_data->hospi, cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
232 if (hal_ret != HAL_OK) {
233 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
234 return -EIO;
235 }
236
237 #if STM32_OSPI_USE_DMA
238 hal_ret = HAL_OSPI_Receive_DMA(&dev_data->hospi, data);
239 #else
240 hal_ret = HAL_OSPI_Receive_IT(&dev_data->hospi, data);
241 #endif
242 if (hal_ret != HAL_OK) {
243 LOG_ERR("%d: Failed to read data", hal_ret);
244 return -EIO;
245 }
246
247 k_sem_take(&dev_data->sync, K_FOREVER);
248
249 return dev_data->cmd_status;
250 }
251
ospi_write_access(const struct device * dev,OSPI_RegularCmdTypeDef * cmd,const uint8_t * data,size_t size)252 static int ospi_write_access(const struct device *dev, OSPI_RegularCmdTypeDef *cmd,
253 const uint8_t *data, size_t size)
254 {
255 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
256 struct flash_stm32_ospi_data *dev_data = dev->data;
257 HAL_StatusTypeDef hal_ret;
258
259 LOG_DBG("Instruction 0x%x", cmd->Instruction);
260
261 cmd->NbData = size;
262
263 dev_data->cmd_status = 0;
264
265 /* in OPI/STR the 3-byte AddressSize is not supported by the NOR flash */
266 if ((dev_cfg->data_mode == OSPI_OPI_MODE) &&
267 (cmd->AddressSize != HAL_OSPI_ADDRESS_32_BITS)) {
268 LOG_ERR("OSPI wr in OPI/STR mode is for 32bit address only");
269 return -EIO;
270 }
271
272 hal_ret = HAL_OSPI_Command(&dev_data->hospi, cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
273 if (hal_ret != HAL_OK) {
274 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
275 return -EIO;
276 }
277
278 #if STM32_OSPI_USE_DMA
279 hal_ret = HAL_OSPI_Transmit_DMA(&dev_data->hospi, (uint8_t *)data);
280 #else
281 hal_ret = HAL_OSPI_Transmit_IT(&dev_data->hospi, (uint8_t *)data);
282 #endif
283
284 if (hal_ret != HAL_OK) {
285 LOG_ERR("%d: Failed to write data", hal_ret);
286 return -EIO;
287 }
288
289 k_sem_take(&dev_data->sync, K_FOREVER);
290
291 return dev_data->cmd_status;
292 }
293
294 /*
295 * Gives a OSPI_RegularCmdTypeDef with all parameters set
296 * except Instruction, Address, DummyCycles, NbData
297 */
ospi_prepare_cmd(uint8_t transfer_mode,uint8_t transfer_rate)298 static OSPI_RegularCmdTypeDef ospi_prepare_cmd(uint8_t transfer_mode, uint8_t transfer_rate)
299 {
300 OSPI_RegularCmdTypeDef cmd_tmp = {
301 .OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
302 .FlashId = HAL_OSPI_FLASH_ID_1,
303 .InstructionSize = ((transfer_mode == OSPI_OPI_MODE)
304 ? HAL_OSPI_INSTRUCTION_16_BITS
305 : HAL_OSPI_INSTRUCTION_8_BITS),
306 .InstructionDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
307 ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
308 : HAL_OSPI_INSTRUCTION_DTR_DISABLE),
309 .AddressDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
310 ? HAL_OSPI_ADDRESS_DTR_ENABLE
311 : HAL_OSPI_ADDRESS_DTR_DISABLE),
312 /* AddressSize must be set to 32bits for init and mem config phase */
313 .AddressSize = HAL_OSPI_ADDRESS_32_BITS,
314 .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
315 .DataDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
316 ? HAL_OSPI_DATA_DTR_ENABLE
317 : HAL_OSPI_DATA_DTR_DISABLE),
318 .DQSMode = (transfer_rate == OSPI_DTR_TRANSFER)
319 ? HAL_OSPI_DQS_ENABLE
320 : HAL_OSPI_DQS_DISABLE,
321 .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
322 };
323
324 switch (transfer_mode) {
325 case OSPI_OPI_MODE: {
326 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
327 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
328 cmd_tmp.DataMode = HAL_OSPI_DATA_8_LINES;
329 break;
330 }
331 case OSPI_QUAD_MODE: {
332 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
333 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
334 cmd_tmp.DataMode = HAL_OSPI_DATA_4_LINES;
335 break;
336 }
337 case OSPI_DUAL_MODE: {
338 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES;
339 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
340 cmd_tmp.DataMode = HAL_OSPI_DATA_2_LINES;
341 break;
342 }
343 default: {
344 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
345 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
346 cmd_tmp.DataMode = HAL_OSPI_DATA_1_LINE;
347 break;
348 }
349 }
350
351 return cmd_tmp;
352 }
353
stm32_ospi_hal_address_size(const struct device * dev)354 static uint32_t stm32_ospi_hal_address_size(const struct device *dev)
355 {
356 struct flash_stm32_ospi_data *dev_data = dev->data;
357
358 if (dev_data->address_width == 4U) {
359 return HAL_OSPI_ADDRESS_32_BITS;
360 }
361
362 return HAL_OSPI_ADDRESS_24_BITS;
363 }
364
365 #if defined(CONFIG_FLASH_JESD216_API)
366 /*
367 * Read the JEDEC ID data from the octoFlash at init or DTS
368 * and store in the jedec_id Table of the flash_stm32_ospi_data
369 */
stm32_ospi_read_jedec_id(const struct device * dev)370 static int stm32_ospi_read_jedec_id(const struct device *dev)
371 {
372 struct flash_stm32_ospi_data *dev_data = dev->data;
373
374 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), jedec_id)
375 /* If DTS has the jedec_id property, check its length */
376 if (DT_INST_PROP_LEN(0, jedec_id) != JESD216_READ_ID_LEN) {
377 LOG_ERR("Read ID length is wrong (%d)", DT_INST_PROP_LEN(0, jedec_id));
378 return -EIO;
379 }
380
381 /* The dev_data->jedec_id if filled from the DTS property */
382 #else
383 /* This is a SPI/STR command to issue to the octoFlash device */
384 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(OSPI_SPI_MODE, OSPI_STR_TRANSFER);
385
386 cmd.Instruction = JESD216_CMD_READ_ID;
387 cmd.AddressSize = stm32_ospi_hal_address_size(dev);
388 cmd.AddressMode = HAL_OSPI_ADDRESS_NONE;
389 cmd.NbData = JESD216_READ_ID_LEN; /* 3 bytes in the READ ID */
390
391 HAL_StatusTypeDef hal_ret;
392
393 hal_ret = HAL_OSPI_Command(&dev_data->hospi, &cmd,
394 HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
395
396 if (hal_ret != HAL_OK) {
397 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
398 return -EIO;
399 }
400
401 /* Place the received data directly into the jedec Table */
402 hal_ret = HAL_OSPI_Receive(&dev_data->hospi, dev_data->jedec_id,
403 HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
404 if (hal_ret != HAL_OK) {
405 LOG_ERR("%d: Failed to read data", hal_ret);
406 return -EIO;
407 }
408 #endif /* jedec_id */
409 LOG_DBG("Jedec ID = [%02x %02x %02x]",
410 dev_data->jedec_id[0], dev_data->jedec_id[1], dev_data->jedec_id[2]);
411
412 dev_data->cmd_status = 0;
413
414 return 0;
415 }
416
417 /*
418 * Read Serial Flash ID :
419 * just gives the values received by the octoFlash or from the DTS
420 */
ospi_read_jedec_id(const struct device * dev,uint8_t * id)421 static int ospi_read_jedec_id(const struct device *dev, uint8_t *id)
422 {
423 struct flash_stm32_ospi_data *dev_data = dev->data;
424
425 /* Take jedec Id values from the table (issued from the octoFlash) */
426 memcpy(id, dev_data->jedec_id, JESD216_READ_ID_LEN);
427
428 LOG_INF("Manuf ID = %02x Memory Type = %02x Memory Density = %02x",
429 id[0], id[1], id[2]);
430
431 return 0;
432 }
433 #endif /* CONFIG_FLASH_JESD216_API */
434
435 #if !DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
436 /*
437 * Read Serial Flash Discovery Parameter from the octoFlash at init :
438 * perform a read access over SPI bus for SDFP (DataMode is already set)
439 */
stm32_ospi_read_sfdp(const struct device * dev,off_t addr,void * data,size_t size)440 static int stm32_ospi_read_sfdp(const struct device *dev, off_t addr,
441 void *data,
442 size_t size)
443 {
444 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
445 struct flash_stm32_ospi_data *dev_data = dev->data;
446
447 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode,
448 dev_cfg->data_rate);
449 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
450 cmd.Instruction = JESD216_OCMD_READ_SFDP;
451 cmd.DummyCycles = 20U;
452 cmd.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
453 } else {
454 cmd.Instruction = JESD216_CMD_READ_SFDP;
455 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
456 cmd.DataMode = HAL_OSPI_DATA_1_LINE;
457 cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
458 cmd.DummyCycles = 8U;
459 cmd.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
460 }
461 cmd.Address = addr;
462 cmd.NbData = size;
463
464 HAL_StatusTypeDef hal_ret;
465
466 hal_ret = HAL_OSPI_Command(&dev_data->hospi, &cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
467 if (hal_ret != HAL_OK) {
468 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
469 return -EIO;
470 }
471
472 hal_ret = HAL_OSPI_Receive(&dev_data->hospi, (uint8_t *)data,
473 HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
474 if (hal_ret != HAL_OK) {
475 LOG_ERR("%d: Failed to read data", hal_ret);
476 return -EIO;
477 }
478
479 dev_data->cmd_status = 0;
480
481 return 0;
482 }
483 #endif /* ! sfdp_bfp */
484
485 /*
486 * Read Serial Flash Discovery Parameter :
487 * perform a read access over SPI bus for SDFP (DataMode is already set)
488 * or get it from the sdfp table (in the DTS)
489 */
ospi_read_sfdp(const struct device * dev,off_t addr,void * data,size_t size)490 static int ospi_read_sfdp(const struct device *dev, off_t addr, void *data,
491 size_t size)
492 {
493 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
494 /* There is a sfdp-bfp property in the deviceTree : do not read the flash */
495 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
496
497 LOG_INF("Read SFDP from DTS property");
498 /* If DTS has the sdfp table property, check its length */
499 if (size > DT_INST_PROP_LEN(0, sfdp_bfp)) {
500 LOG_ERR("SDFP bdfp length is wrong (%d)", DT_INST_PROP_LEN(0, sfdp_bfp));
501 return -EIO;
502 }
503 /* The dev_cfg->sfdp_bfp if filled from the DTS property */
504 memcpy(data, dev_cfg->sfdp_bfp + addr, size);
505
506 return 0;
507 #else
508 LOG_INF("Read SFDP from octoFlash");
509 /* Get the SFDP from the octoFlash (no sfdp-bfp table in the DeviceTree) */
510 if (stm32_ospi_read_sfdp(dev, addr, data, size) == 0) {
511 /* If valid, then ignore any table from the DTS */
512 return 0;
513 }
514 LOG_INF("Error reading SFDP from octoFlash and none in the DTS");
515 return -EINVAL;
516 #endif /* sfdp_bfp */
517 }
518
ospi_address_is_valid(const struct device * dev,off_t addr,size_t size)519 static bool ospi_address_is_valid(const struct device *dev, off_t addr,
520 size_t size)
521 {
522 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
523 size_t flash_size = dev_cfg->flash_size;
524
525 return (addr >= 0) && ((uint64_t)addr + (uint64_t)size <= flash_size);
526 }
527
stm32_ospi_wait_auto_polling(struct flash_stm32_ospi_data * dev_data,OSPI_AutoPollingTypeDef * s_config,uint32_t timeout_ms)528 static int stm32_ospi_wait_auto_polling(struct flash_stm32_ospi_data *dev_data,
529 OSPI_AutoPollingTypeDef *s_config, uint32_t timeout_ms)
530 {
531 dev_data->cmd_status = 0;
532 if (HAL_OSPI_AutoPolling_IT(&dev_data->hospi, s_config) != HAL_OK) {
533 LOG_ERR("OSPI AutoPoll failed");
534 return -EIO;
535 }
536
537 if (k_sem_take(&dev_data->sync, K_MSEC(timeout_ms)) != 0) {
538 LOG_ERR("OSPI AutoPoll wait failed");
539 HAL_OSPI_Abort(&dev_data->hospi);
540 k_sem_reset(&dev_data->sync);
541 return -EIO;
542 }
543
544 /* HAL_OSPI_AutoPolling_IT enables transfer error interrupt which sets
545 * cmd_status.
546 */
547 return dev_data->cmd_status;
548 }
549
550 /*
551 * This function Polls the WEL (write enable latch) bit to become to 0
552 * When the Chip Erase Cycle is completed, the Write Enable Latch (WEL) bit is cleared.
553 * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE
554 * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER
555 */
stm32_ospi_mem_erased(const struct device * dev)556 static int stm32_ospi_mem_erased(const struct device *dev)
557 {
558 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
559 struct flash_stm32_ospi_data *dev_data = dev->data;
560 uint8_t nor_mode = dev_cfg->data_mode;
561 uint8_t nor_rate = dev_cfg->data_rate;
562 OSPI_HandleTypeDef *hospi = &dev_data->hospi;
563 OSPI_AutoPollingTypeDef s_config = {0};
564 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
565
566 /* Configure automatic polling mode command to wait for memory ready */
567 if (nor_mode == OSPI_OPI_MODE) {
568 s_command.Instruction = SPI_NOR_OCMD_RDSR;
569 s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
570 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
571 : SPI_NOR_DUMMY_REG_OCTAL;
572 } else {
573 s_command.Instruction = SPI_NOR_CMD_RDSR;
574 /* force 1-line InstructionMode for any non-OSPI transfer */
575 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
576 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
577 /* force 1-line DataMode for any non-OSPI transfer */
578 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
579 s_command.DummyCycles = 0;
580 }
581 s_command.NbData = ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
582 s_command.Address = 0U;
583
584 /* Set the mask to 0x02 to mask all Status REG bits except WEL */
585 /* Set the match to 0x00 to check if the WEL bit is Reset */
586 s_config.Match = SPI_NOR_WEL_MATCH;
587 s_config.Mask = SPI_NOR_WEL_MASK; /* Write Enable Latch */
588
589 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
590 s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL;
591 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
592
593 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
594 LOG_ERR("OSPI AutoPoll command (WEL) failed");
595 return -EIO;
596 }
597
598 /* Start Automatic-Polling mode to wait until the memory is totally erased */
599 return stm32_ospi_wait_auto_polling(dev_data,
600 &s_config, STM32_OSPI_BULK_ERASE_MAX_TIME);
601 }
602
603 /*
604 * This function Polls the WIP(Write In Progress) bit to become to 0
605 * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE
606 * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER
607 */
stm32_ospi_mem_ready(struct flash_stm32_ospi_data * dev_data,uint8_t nor_mode,uint8_t nor_rate)608 static int stm32_ospi_mem_ready(struct flash_stm32_ospi_data *dev_data, uint8_t nor_mode,
609 uint8_t nor_rate)
610 {
611 OSPI_HandleTypeDef *hospi = &dev_data->hospi;
612 OSPI_AutoPollingTypeDef s_config = {0};
613 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
614
615 /* Configure automatic polling mode command to wait for memory ready */
616 if (nor_mode == OSPI_OPI_MODE) {
617 s_command.Instruction = SPI_NOR_OCMD_RDSR;
618 s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
619 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
620 : SPI_NOR_DUMMY_REG_OCTAL;
621 } else {
622 s_command.Instruction = SPI_NOR_CMD_RDSR;
623 /* force 1-line InstructionMode for any non-OSPI transfer */
624 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
625 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
626 /* force 1-line DataMode for any non-OSPI transfer */
627 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
628 s_command.DummyCycles = 0;
629 }
630 s_command.NbData = ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
631 s_command.Address = 0U;
632
633 /* Set the mask to 0x01 to mask all Status REG bits except WIP */
634 /* Set the match to 0x00 to check if the WIP bit is Reset */
635 s_config.Match = SPI_NOR_MEM_RDY_MATCH;
636 s_config.Mask = SPI_NOR_MEM_RDY_MASK; /* Write in progress */
637 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
638 s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL;
639 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
640
641 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
642 LOG_ERR("OSPI AutoPoll command failed");
643 return -EIO;
644 }
645
646 /* Start Automatic-Polling mode to wait until the memory is ready WIP=0 */
647 return stm32_ospi_wait_auto_polling(dev_data, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
648 }
649
650 /* Enables writing to the memory sending a Write Enable and wait it is effective */
stm32_ospi_write_enable(struct flash_stm32_ospi_data * dev_data,uint8_t nor_mode,uint8_t nor_rate)651 static int stm32_ospi_write_enable(struct flash_stm32_ospi_data *dev_data,
652 uint8_t nor_mode, uint8_t nor_rate)
653 {
654 OSPI_HandleTypeDef *hospi = &dev_data->hospi;
655 OSPI_AutoPollingTypeDef s_config = {0};
656 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
657
658 /* Initialize the write enable command */
659 if (nor_mode == OSPI_OPI_MODE) {
660 s_command.Instruction = SPI_NOR_OCMD_WREN;
661 } else {
662 s_command.Instruction = SPI_NOR_CMD_WREN;
663 /* force 1-line InstructionMode for any non-OSPI transfer */
664 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
665 }
666 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
667 s_command.DataMode = HAL_OSPI_DATA_NONE;
668 s_command.DummyCycles = 0U;
669
670 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
671 LOG_ERR("OSPI flash write enable cmd failed");
672 return -EIO;
673 }
674
675 /* New command to Configure automatic polling mode to wait for write enabling */
676 if (nor_mode == OSPI_OPI_MODE) {
677 s_command.Instruction = SPI_NOR_OCMD_RDSR;
678 s_command.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
679 s_command.DataMode = HAL_OSPI_DATA_8_LINES;
680 s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
681 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
682 : SPI_NOR_DUMMY_REG_OCTAL;
683 } else {
684 s_command.Instruction = SPI_NOR_CMD_RDSR;
685 /* force 1-line DataMode for any non-OSPI transfer */
686 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
687 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
688 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
689 s_command.DummyCycles = 0;
690
691 /* DummyCycles remains 0 */
692 }
693 s_command.NbData = (nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U;
694 s_command.Address = 0U;
695
696 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
697 LOG_ERR("OSPI config auto polling cmd failed");
698 return -EIO;
699 }
700
701 s_config.Match = SPI_NOR_WREN_MATCH;
702 s_config.Mask = SPI_NOR_WREN_MASK;
703 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
704 s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL;
705 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
706
707 return stm32_ospi_wait_auto_polling(dev_data, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
708 }
709
710 /* Write Flash configuration register 2 with new dummy cycles */
stm32_ospi_write_cfg2reg_dummy(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate)711 static int stm32_ospi_write_cfg2reg_dummy(OSPI_HandleTypeDef *hospi,
712 uint8_t nor_mode, uint8_t nor_rate)
713 {
714 uint8_t transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ;
715 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
716
717 /* Initialize the writing of configuration register 2 */
718 s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
719 ? SPI_NOR_CMD_WR_CFGREG2
720 : SPI_NOR_OCMD_WR_CFGREG2;
721 s_command.Address = SPI_NOR_REG2_ADDR3;
722 s_command.DummyCycles = 0U;
723 s_command.NbData = (nor_mode == OSPI_SPI_MODE) ? 1U
724 : ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
725
726 if (HAL_OSPI_Command(hospi, &s_command,
727 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
728 LOG_ERR("OSPI transmit ");
729 return -EIO;
730 }
731
732 if (HAL_OSPI_Transmit(hospi, &transmit_data,
733 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
734 LOG_ERR("OSPI transmit ");
735 return -EIO;
736 }
737
738 return 0;
739 }
740
741 /* Write Flash configuration register 2 with new single or octal SPI protocol */
stm32_ospi_write_cfg2reg_io(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate,uint8_t op_enable)742 static int stm32_ospi_write_cfg2reg_io(OSPI_HandleTypeDef *hospi,
743 uint8_t nor_mode, uint8_t nor_rate, uint8_t op_enable)
744 {
745 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
746
747 /* Initialize the writing of configuration register 2 */
748 s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
749 ? SPI_NOR_CMD_WR_CFGREG2
750 : SPI_NOR_OCMD_WR_CFGREG2;
751 s_command.Address = SPI_NOR_REG2_ADDR1;
752 s_command.DummyCycles = 0U;
753 s_command.NbData = (nor_mode == OSPI_SPI_MODE) ? 1U
754 : ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
755
756 if (HAL_OSPI_Command(hospi, &s_command,
757 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
758 LOG_ERR("Write Flash configuration reg2 failed");
759 return -EIO;
760 }
761
762 if (HAL_OSPI_Transmit(hospi, &op_enable,
763 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
764 LOG_ERR("Write Flash configuration reg2 failed");
765 return -EIO;
766 }
767
768 return 0;
769 }
770
771 /* Read Flash configuration register 2 with new single or octal SPI protocol */
stm32_ospi_read_cfg2reg(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate,uint8_t * value)772 static int stm32_ospi_read_cfg2reg(OSPI_HandleTypeDef *hospi,
773 uint8_t nor_mode, uint8_t nor_rate, uint8_t *value)
774 {
775 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
776
777 /* Initialize the writing of configuration register 2 */
778 s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
779 ? SPI_NOR_CMD_RD_CFGREG2
780 : SPI_NOR_OCMD_RD_CFGREG2;
781 s_command.Address = SPI_NOR_REG2_ADDR1;
782 s_command.DummyCycles = (nor_mode == OSPI_SPI_MODE)
783 ? 0U
784 : ((nor_rate == OSPI_DTR_TRANSFER)
785 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
786 : SPI_NOR_DUMMY_REG_OCTAL);
787 s_command.NbData = (nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U;
788
789 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
790 LOG_ERR("Write Flash configuration reg2 failed");
791 return -EIO;
792 }
793
794 if (HAL_OSPI_Receive(hospi, value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
795 LOG_ERR("Write Flash configuration reg2 failed");
796 return -EIO;
797 }
798
799 return 0;
800 }
801
802 /* Set the NOR Flash to desired Interface mode : SPI/OSPI and STR/DTR according to the DTS */
stm32_ospi_config_mem(const struct device * dev)803 static int stm32_ospi_config_mem(const struct device *dev)
804 {
805 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
806 struct flash_stm32_ospi_data *dev_data = dev->data;
807 uint8_t reg[2];
808
809 /* Going to set the SPI mode and STR transfer rate : done */
810 if ((dev_cfg->data_mode != OSPI_OPI_MODE)
811 && (dev_cfg->data_rate == OSPI_STR_TRANSFER)) {
812 LOG_INF("OSPI flash config is SPI|DUAL|QUAD / STR");
813 return 0;
814 }
815
816 /* Going to set the OPI mode (STR or DTR transfer rate) */
817 LOG_DBG("OSPI configuring OctoSPI mode");
818
819 if (stm32_ospi_write_enable(dev_data,
820 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
821 LOG_ERR("OSPI write Enable failed");
822 return -EIO;
823 }
824
825 /* Write Configuration register 2 (with new dummy cycles) */
826 if (stm32_ospi_write_cfg2reg_dummy(&dev_data->hospi,
827 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
828 LOG_ERR("OSPI write CFGR2 failed");
829 return -EIO;
830 }
831 if (stm32_ospi_mem_ready(dev_data,
832 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
833 LOG_ERR("OSPI autopolling failed");
834 return -EIO;
835 }
836 if (stm32_ospi_write_enable(dev_data,
837 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
838 LOG_ERR("OSPI write Enable 2 failed");
839 return -EIO;
840 }
841
842 /* Write Configuration register 2 (with Octal I/O SPI protocol : choose STR or DTR) */
843 uint8_t mode_enable = ((dev_cfg->data_rate == OSPI_DTR_TRANSFER)
844 ? SPI_NOR_CR2_DTR_OPI_EN
845 : SPI_NOR_CR2_STR_OPI_EN);
846 if (stm32_ospi_write_cfg2reg_io(&dev_data->hospi,
847 OSPI_SPI_MODE, OSPI_STR_TRANSFER, mode_enable) != 0) {
848 LOG_ERR("OSPI write CFGR2 failed");
849 return -EIO;
850 }
851
852 /* Wait that the configuration is effective and check that memory is ready */
853 k_busy_wait(STM32_OSPI_WRITE_REG_MAX_TIME * USEC_PER_MSEC);
854
855 /* Reconfigure the memory type of the peripheral */
856 dev_data->hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX;
857 dev_data->hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;
858 if (HAL_OSPI_Init(&dev_data->hospi) != HAL_OK) {
859 LOG_ERR("OSPI mem type MACRONIX failed");
860 return -EIO;
861 }
862
863 if (dev_cfg->data_rate == OSPI_STR_TRANSFER) {
864 if (stm32_ospi_mem_ready(dev_data,
865 OSPI_OPI_MODE, OSPI_STR_TRANSFER) != 0) {
866 /* Check Flash busy ? */
867 LOG_ERR("OSPI flash busy failed");
868 return -EIO;
869 }
870
871 if (stm32_ospi_read_cfg2reg(&dev_data->hospi,
872 OSPI_OPI_MODE, OSPI_STR_TRANSFER, reg) != 0) {
873 /* Check the configuration has been correctly done on SPI_NOR_REG2_ADDR1 */
874 LOG_ERR("OSPI flash config read failed");
875 return -EIO;
876 }
877
878 LOG_INF("OSPI flash config is OPI / STR");
879 }
880
881 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
882 if (stm32_ospi_mem_ready(dev_data,
883 OSPI_OPI_MODE, OSPI_DTR_TRANSFER) != 0) {
884 /* Check Flash busy ? */
885 LOG_ERR("OSPI flash busy failed");
886 return -EIO;
887 }
888
889 LOG_INF("OSPI flash config is OPI / DTR");
890 }
891
892 return 0;
893 }
894
895 /* gpio or send the different reset command to the NOR flash in SPI/OSPI and STR/DTR */
stm32_ospi_mem_reset(const struct device * dev)896 static int stm32_ospi_mem_reset(const struct device *dev)
897 {
898 struct flash_stm32_ospi_data *dev_data = dev->data;
899
900 #if STM32_OSPI_RESET_GPIO
901 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
902
903 /* Generate RESETn pulse for the flash memory */
904 gpio_pin_configure_dt(&dev_cfg->reset, GPIO_OUTPUT_ACTIVE);
905 k_msleep(DT_INST_PROP(0, reset_gpios_duration));
906 gpio_pin_set_dt(&dev_cfg->reset, 0);
907 #else
908
909 /* Reset command sent sucessively for each mode SPI/OPS & STR/DTR */
910 OSPI_RegularCmdTypeDef s_command = {
911 .OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
912 .FlashId = HAL_OSPI_FLASH_ID_1,
913 .AddressMode = HAL_OSPI_ADDRESS_NONE,
914 .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
915 .InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE,
916 .Instruction = SPI_NOR_CMD_RESET_EN,
917 .InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS,
918 .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
919 .DataMode = HAL_OSPI_DATA_NONE,
920 .DummyCycles = 0U,
921 .DQSMode = HAL_OSPI_DQS_DISABLE,
922 .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
923 };
924
925 /* Reset enable in SPI mode and STR transfer mode */
926 if (HAL_OSPI_Command(&dev_data->hospi,
927 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
928 LOG_ERR("OSPI reset enable (SPI/STR) failed");
929 return -EIO;
930 }
931
932 /* Reset memory in SPI mode and STR transfer mode */
933 s_command.Instruction = SPI_NOR_CMD_RESET_MEM;
934 if (HAL_OSPI_Command(&dev_data->hospi,
935 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
936 LOG_ERR("OSPI reset memory (SPI/STR) failed");
937 return -EIO;
938 }
939
940 /* Reset enable in OPI mode and STR transfer mode */
941 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
942 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
943 s_command.Instruction = SPI_NOR_OCMD_RESET_EN;
944 s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
945 if (HAL_OSPI_Command(&dev_data->hospi,
946 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
947 LOG_ERR("OSPI reset enable (OPI/STR) failed");
948 return -EIO;
949 }
950
951 /* Reset memory in OPI mode and STR transfer mode */
952 s_command.Instruction = SPI_NOR_OCMD_RESET_MEM;
953 if (HAL_OSPI_Command(&dev_data->hospi,
954 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
955 LOG_ERR("OSPI reset memory (OPI/STR) failed");
956 return -EIO;
957 }
958
959 /* Reset enable in OPI mode and DTR transfer mode */
960 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
961 s_command.Instruction = SPI_NOR_OCMD_RESET_EN;
962 if (HAL_OSPI_Command(&dev_data->hospi,
963 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
964 LOG_ERR("OSPI reset enable (OPI/DTR) failed");
965 return -EIO;
966 }
967
968 /* Reset memory in OPI mode and DTR transfer mode */
969 s_command.Instruction = SPI_NOR_OCMD_RESET_MEM;
970 if (HAL_OSPI_Command(&dev_data->hospi,
971 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
972 LOG_ERR("OSPI reset memory (OPI/DTR) failed");
973 return -EIO;
974 }
975
976 #endif
977 /* Wait after SWreset CMD, in case SWReset occurred during erase operation */
978 k_busy_wait(STM32_OSPI_RESET_MAX_TIME * USEC_PER_MSEC);
979
980 return 0;
981 }
982
983 #ifdef CONFIG_STM32_MEMMAP
984 /* Function to configure the octoflash in MemoryMapped mode */
stm32_ospi_set_memorymap(const struct device * dev)985 static int stm32_ospi_set_memorymap(const struct device *dev)
986 {
987 HAL_StatusTypeDef ret;
988 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
989 struct flash_stm32_ospi_data *dev_data = dev->data;
990 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
991 OSPI_MemoryMappedTypeDef s_MemMappedCfg;
992
993 /* Configure octoflash in MemoryMapped mode */
994 if ((dev_cfg->data_mode == OSPI_SPI_MODE) &&
995 (stm32_ospi_hal_address_size(dev) == HAL_OSPI_ADDRESS_24_BITS)) {
996 /* OPI mode and 3-bytes address size not supported by memory */
997 LOG_ERR("OSPI_SPI_MODE in 3Bytes addressing is not supported");
998 return -ENOTSUP;
999 }
1000
1001 /* Initialize the read command */
1002 s_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
1003 s_command.AddressSize = (dev_cfg->data_rate == OSPI_STR_TRANSFER)
1004 ? stm32_ospi_hal_address_size(dev)
1005 : HAL_OSPI_ADDRESS_32_BITS;
1006 /* Adapt lines based on read_mode */
1007 if (dev_cfg->data_mode != OSPI_OPI_MODE) {
1008 switch (dev_data->read_mode) {
1009 case JESD216_MODE_112:
1010 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1011 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1012 s_command.DataMode = HAL_OSPI_DATA_2_LINES;
1013 break;
1014 case JESD216_MODE_122:
1015 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1016 s_command.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
1017 s_command.DataMode = HAL_OSPI_DATA_2_LINES;
1018 break;
1019 case JESD216_MODE_114:
1020 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1021 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1022 s_command.DataMode = HAL_OSPI_DATA_4_LINES;
1023 break;
1024 case JESD216_MODE_144:
1025 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1026 s_command.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
1027 s_command.DataMode = HAL_OSPI_DATA_4_LINES;
1028 break;
1029 default:
1030 /* Use lines based on data_mode set in ospi_prepare_cmd */
1031 break;
1032 }
1033 }
1034 /* Set instruction and dummy cycles parameters */
1035 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
1036 /* DTR transfer rate (==> Octal mode) */
1037 s_command.Instruction = SPI_NOR_OCMD_DTR_RD;
1038 s_command.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
1039 } else {
1040 /* STR transfer rate */
1041 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
1042 /* OPI and STR */
1043 s_command.Instruction = SPI_NOR_OCMD_RD;
1044 s_command.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
1045 } else {
1046 /* use SFDP:BFP read instruction */
1047 s_command.Instruction = dev_data->read_opcode;
1048 s_command.DummyCycles = dev_data->read_dummy;
1049 }
1050 }
1051
1052 ret = HAL_OSPI_Command(&dev_data->hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
1053 if (ret != HAL_OK) {
1054 LOG_ERR("%d: Failed to set memory map read cmd", ret);
1055 return -EIO;
1056 }
1057
1058 /* Initialize the program command */
1059 s_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
1060 s_command.DQSMode = HAL_OSPI_DQS_DISABLE;
1061
1062 s_command.Instruction = dev_data->write_opcode;
1063 s_command.DummyCycles = 0U;
1064 /* Adapt lines based on write opcode */
1065 switch (s_command.Instruction) {
1066 case SPI_NOR_CMD_PP_4B:
1067 __fallthrough;
1068 case SPI_NOR_CMD_PP:
1069 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1070 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1071 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
1072 break;
1073 case SPI_NOR_CMD_PP_1_1_2:
1074 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1075 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1076 s_command.DataMode = HAL_OSPI_DATA_2_LINES;
1077 break;
1078 case SPI_NOR_CMD_PP_1_1_4_4B:
1079 __fallthrough;
1080 case SPI_NOR_CMD_PP_1_1_4:
1081 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1082 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1083 s_command.DataMode = HAL_OSPI_DATA_4_LINES;
1084 break;
1085 case SPI_NOR_CMD_PP_1_4_4_4B:
1086 __fallthrough;
1087 case SPI_NOR_CMD_PP_1_4_4:
1088 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1089 s_command.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
1090 s_command.DataMode = HAL_OSPI_DATA_4_LINES;
1091 break;
1092 default:
1093 /* Use lines based on data_mode set in ospi_prepare_cmd */
1094 break;
1095 }
1096
1097 ret = HAL_OSPI_Command(&dev_data->hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
1098 if (ret != HAL_OK) {
1099 LOG_ERR("%d: Failed to set memory map write cmd", ret);
1100 return -EIO;
1101 }
1102
1103 /* Enable the memory-mapping */
1104 s_MemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
1105
1106 ret = HAL_OSPI_MemoryMapped(&dev_data->hospi, &s_MemMappedCfg);
1107 if (ret != HAL_OK) {
1108 LOG_ERR("%d: Failed to enable memory map", ret);
1109 return -EIO;
1110 }
1111
1112 LOG_DBG("MemoryMap mode enabled");
1113 return 0;
1114 }
1115
1116 /* Function to return true if the octoflash is in MemoryMapped else false */
stm32_ospi_is_memorymap(const struct device * dev)1117 static bool stm32_ospi_is_memorymap(const struct device *dev)
1118 {
1119 struct flash_stm32_ospi_data *dev_data = dev->data;
1120
1121 return ((READ_BIT(dev_data->hospi.Instance->CR,
1122 OCTOSPI_CR_FMODE) == OCTOSPI_CR_FMODE) ?
1123 true : false);
1124 }
1125
stm32_ospi_abort(const struct device * dev)1126 static int stm32_ospi_abort(const struct device *dev)
1127 {
1128 struct flash_stm32_ospi_data *dev_data = dev->data;
1129 HAL_StatusTypeDef hal_ret;
1130
1131 hal_ret = HAL_OSPI_Abort(&dev_data->hospi);
1132 if (hal_ret != HAL_OK) {
1133 LOG_ERR("%d: OSPI abort failed", hal_ret);
1134 return -EIO;
1135 }
1136
1137 return 0;
1138 }
1139 #endif /* CONFIG_STM32_MEMMAP */
1140
1141 /*
1142 * Function to erase the flash : chip or sector with possible OSPI/SPI and STR/DTR
1143 * to erase the complete chip (using dedicated command) :
1144 * set size >= flash size
1145 * set addr = 0
1146 * NOTE: cannot erase in MemoryMapped mode
1147 */
flash_stm32_ospi_erase(const struct device * dev,off_t addr,size_t size)1148 static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
1149 size_t size)
1150 {
1151 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1152 struct flash_stm32_ospi_data *dev_data = dev->data;
1153 int ret = 0;
1154
1155 /* Ignore zero size erase */
1156 if (size == 0) {
1157 return 0;
1158 }
1159
1160 /* Maximise erase size : means the complete chip */
1161 if (size > dev_cfg->flash_size) {
1162 size = dev_cfg->flash_size;
1163 }
1164
1165 if (!ospi_address_is_valid(dev, addr, size)) {
1166 LOG_ERR("Error: address or size exceeds expected values: "
1167 "addr 0x%lx, size %zu", (long)addr, size);
1168 return -EINVAL;
1169 }
1170
1171 if (((size % SPI_NOR_SECTOR_SIZE) != 0) && (size < dev_cfg->flash_size)) {
1172 LOG_ERR("Error: wrong sector size 0x%x", size);
1173 return -ENOTSUP;
1174 }
1175
1176 ospi_lock_thread(dev);
1177
1178 #ifdef CONFIG_STM32_MEMMAP
1179 if (stm32_ospi_is_memorymap(dev)) {
1180 /* Abort ongoing transfer to force CS high/BUSY deasserted */
1181 ret = stm32_ospi_abort(dev);
1182 if (ret != 0) {
1183 LOG_ERR("Failed to abort memory-mapped access before erase");
1184 goto end_erase;
1185 }
1186 }
1187 /* Continue with Indirect Mode */
1188 #endif /* CONFIG_STM32_MEMMAP */
1189
1190 OSPI_RegularCmdTypeDef cmd_erase = {
1191 .OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
1192 .FlashId = HAL_OSPI_FLASH_ID_1,
1193 .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
1194 .DataMode = HAL_OSPI_DATA_NONE,
1195 .DummyCycles = 0U,
1196 .DQSMode = HAL_OSPI_DQS_DISABLE,
1197 .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
1198 };
1199
1200 if (stm32_ospi_mem_ready(dev_data,
1201 dev_cfg->data_mode, dev_cfg->data_rate) != 0) {
1202 LOG_ERR("Erase failed : flash busy");
1203 ret = -EBUSY;
1204 goto end_erase;
1205 }
1206
1207 cmd_erase.InstructionMode = (dev_cfg->data_mode == OSPI_OPI_MODE)
1208 ? HAL_OSPI_INSTRUCTION_8_LINES
1209 : HAL_OSPI_INSTRUCTION_1_LINE;
1210 cmd_erase.InstructionDtrMode = (dev_cfg->data_rate == OSPI_DTR_TRANSFER)
1211 ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
1212 : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1213 cmd_erase.InstructionSize = (dev_cfg->data_mode == OSPI_OPI_MODE)
1214 ? HAL_OSPI_INSTRUCTION_16_BITS
1215 : HAL_OSPI_INSTRUCTION_8_BITS;
1216
1217 while ((size > 0) && (ret == 0)) {
1218
1219 ret = stm32_ospi_write_enable(dev_data,
1220 dev_cfg->data_mode, dev_cfg->data_rate);
1221 if (ret != 0) {
1222 LOG_ERR("Erase failed : write enable");
1223 break;
1224 }
1225
1226 if (size == dev_cfg->flash_size) {
1227 /* Chip erase */
1228 LOG_DBG("Chip Erase");
1229
1230 cmd_erase.Address = 0;
1231 cmd_erase.Instruction = (dev_cfg->data_mode == OSPI_OPI_MODE)
1232 ? SPI_NOR_OCMD_BULKE
1233 : SPI_NOR_CMD_BULKE;
1234 cmd_erase.AddressMode = HAL_OSPI_ADDRESS_NONE;
1235 /* Full chip erase (Bulk) command */
1236 ospi_send_cmd(dev, &cmd_erase);
1237
1238 size -= dev_cfg->flash_size;
1239 /* Chip (Bulk) erase started, wait until WEL becomes 0 */
1240 ret = stm32_ospi_mem_erased(dev);
1241 if (ret != 0) {
1242 LOG_ERR("Chip Erase failed");
1243 break;
1244 }
1245 } else {
1246 /* Sector or Block erase depending on the size */
1247 LOG_DBG("Sector/Block Erase");
1248
1249 cmd_erase.AddressMode =
1250 (dev_cfg->data_mode == OSPI_OPI_MODE)
1251 ? HAL_OSPI_ADDRESS_8_LINES
1252 : HAL_OSPI_ADDRESS_1_LINE;
1253 cmd_erase.AddressDtrMode =
1254 (dev_cfg->data_rate == OSPI_DTR_TRANSFER)
1255 ? HAL_OSPI_ADDRESS_DTR_ENABLE
1256 : HAL_OSPI_ADDRESS_DTR_DISABLE;
1257 cmd_erase.AddressSize = stm32_ospi_hal_address_size(dev);
1258 cmd_erase.Address = addr;
1259
1260 const struct jesd216_erase_type *erase_types =
1261 dev_data->erase_types;
1262 const struct jesd216_erase_type *bet = NULL;
1263
1264 for (uint8_t ei = 0;
1265 ei < JESD216_NUM_ERASE_TYPES; ++ei) {
1266 const struct jesd216_erase_type *etp =
1267 &erase_types[ei];
1268
1269 if ((etp->exp != 0)
1270 && SPI_NOR_IS_ALIGNED(addr, etp->exp)
1271 && (size >= BIT(etp->exp))
1272 && ((bet == NULL)
1273 || (etp->exp > bet->exp))) {
1274 bet = etp;
1275 cmd_erase.Instruction = bet->cmd;
1276 } else if (bet == NULL) {
1277 /* Use the default sector erase cmd */
1278 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
1279 cmd_erase.Instruction = SPI_NOR_OCMD_SE;
1280 } else {
1281 cmd_erase.Instruction =
1282 (stm32_ospi_hal_address_size(dev) ==
1283 HAL_OSPI_ADDRESS_32_BITS)
1284 ? SPI_NOR_CMD_SE_4B
1285 : SPI_NOR_CMD_SE;
1286 }
1287 }
1288 /* Avoid using wrong erase type,
1289 * if zero entries are found in erase_types
1290 */
1291 bet = NULL;
1292 }
1293 LOG_DBG("Sector/Block Erase addr 0x%x, asize 0x%x amode 0x%x instr 0x%x",
1294 cmd_erase.Address, cmd_erase.AddressSize,
1295 cmd_erase.AddressMode, cmd_erase.Instruction);
1296
1297 ospi_send_cmd(dev, &cmd_erase);
1298
1299 if (bet != NULL) {
1300 addr += BIT(bet->exp);
1301 size -= BIT(bet->exp);
1302 } else {
1303 addr += SPI_NOR_SECTOR_SIZE;
1304 size -= SPI_NOR_SECTOR_SIZE;
1305 }
1306
1307 ret = stm32_ospi_mem_ready(dev_data, dev_cfg->data_mode,
1308 dev_cfg->data_rate);
1309 }
1310 }
1311 goto end_erase;
1312
1313 end_erase:
1314 ospi_unlock_thread(dev);
1315
1316 return ret;
1317 }
1318
1319 /* Function to read the flash with possible OSPI/SPI and STR/DTR */
flash_stm32_ospi_read(const struct device * dev,off_t addr,void * data,size_t size)1320 static int flash_stm32_ospi_read(const struct device *dev, off_t addr,
1321 void *data, size_t size)
1322 {
1323 int ret = 0;
1324
1325 if (!ospi_address_is_valid(dev, addr, size)) {
1326 LOG_ERR("Error: address or size exceeds expected values: "
1327 "addr 0x%lx, size %zu", (long)addr, size);
1328 return -EINVAL;
1329 }
1330
1331 /* Ignore zero size read */
1332 if (size == 0) {
1333 return 0;
1334 }
1335
1336 #ifdef CONFIG_STM32_MEMMAP
1337 /* If not MemMapped then configure it */
1338 if (!stm32_ospi_is_memorymap(dev)) {
1339 if (stm32_ospi_set_memorymap(dev) != 0) {
1340 LOG_ERR("READ failed: cannot enable MemoryMap");
1341 return -EIO;
1342 }
1343 }
1344 /* Now in MemMapped mode : read with memcopy */
1345 LOG_DBG("MemoryMapped Read offset: 0x%lx, len: %zu",
1346 (long)(STM32_OSPI_BASE_ADDRESS + addr),
1347 size);
1348 memcpy(data, (uint8_t *)STM32_OSPI_BASE_ADDRESS + addr, size);
1349
1350 #else /* CONFIG_STM32_MEMMAP */
1351 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1352 struct flash_stm32_ospi_data *dev_data = dev->data;
1353
1354
1355 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
1356
1357 if (dev_cfg->data_mode != OSPI_OPI_MODE) {
1358 switch (dev_data->read_mode) {
1359 case JESD216_MODE_112: {
1360 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1361 cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1362 cmd.DataMode = HAL_OSPI_DATA_2_LINES;
1363 break;
1364 }
1365 case JESD216_MODE_122: {
1366 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1367 cmd.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
1368 cmd.DataMode = HAL_OSPI_DATA_2_LINES;
1369 break;
1370 }
1371 case JESD216_MODE_114: {
1372 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1373 cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1374 cmd.DataMode = HAL_OSPI_DATA_4_LINES;
1375 break;
1376 }
1377 case JESD216_MODE_144: {
1378 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1379 cmd.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
1380 cmd.DataMode = HAL_OSPI_DATA_4_LINES;
1381 break;
1382 }
1383 default:
1384 /* use the mode from ospi_prepare_cmd */
1385 break;
1386 }
1387 }
1388
1389 /* Instruction and DummyCycles are set below */
1390 cmd.Address = addr; /* AddressSize is 32bits in OPSI mode */
1391 cmd.AddressSize = stm32_ospi_hal_address_size(dev);
1392 /* DataSize is set by the read cmd */
1393
1394 /* Configure other parameters */
1395 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
1396 /* DTR transfer rate (==> Octal mode) */
1397 cmd.Instruction = SPI_NOR_OCMD_DTR_RD;
1398 cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
1399 } else {
1400 /* STR transfer rate */
1401 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
1402 /* OPI and STR */
1403 cmd.Instruction = SPI_NOR_OCMD_RD;
1404 cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
1405 } else {
1406 /* use SFDP:BFP read instruction */
1407 cmd.Instruction = dev_data->read_opcode;
1408 cmd.DummyCycles = dev_data->read_dummy;
1409 /* in SPI and STR : expecting SPI_NOR_CMD_READ_FAST_4B */
1410 }
1411 }
1412
1413 LOG_DBG("OSPI: read %zu data", size);
1414 ospi_lock_thread(dev);
1415
1416 ret = ospi_read_access(dev, &cmd, data, size);
1417
1418 ospi_unlock_thread(dev);
1419
1420 #endif /* CONFIG_STM32_MEMMAP */
1421 return ret;
1422 }
1423
1424 /*
1425 * Function to write the flash (page program) : with possible OSPI/SPI and STR/DTR
1426 * NOTE: writing in MemoryMapped mode is not guaranted
1427 */
flash_stm32_ospi_write(const struct device * dev,off_t addr,const void * data,size_t size)1428 static int flash_stm32_ospi_write(const struct device *dev, off_t addr,
1429 const void *data, size_t size)
1430 {
1431 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1432 struct flash_stm32_ospi_data *dev_data = dev->data;
1433 size_t to_write;
1434 int ret = 0;
1435
1436 if (!ospi_address_is_valid(dev, addr, size)) {
1437 LOG_ERR("Error: address or size exceeds expected values: "
1438 "addr 0x%lx, size %zu", (long)addr, size);
1439 return -EINVAL;
1440 }
1441
1442 /* Ignore zero size write */
1443 if (size == 0) {
1444 return 0;
1445 }
1446
1447 ospi_lock_thread(dev);
1448
1449 #ifdef CONFIG_STM32_MEMMAP
1450 if (stm32_ospi_is_memorymap(dev)) {
1451 /* Abort ongoing transfer to force CS high/BUSY deasserted */
1452 ret = stm32_ospi_abort(dev);
1453 if (ret != 0) {
1454 LOG_ERR("Failed to abort memory-mapped access before write");
1455 goto end_write;
1456 }
1457 }
1458 /* Continue with Indirect Mode */
1459 #endif /* CONFIG_STM32_MEMMAP */
1460 /* page program for STR or DTR mode */
1461 OSPI_RegularCmdTypeDef cmd_pp = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
1462
1463 /* using 32bits address also in SPI/STR mode */
1464 cmd_pp.Instruction = dev_data->write_opcode;
1465
1466 /* Adapt lines based on write_opcode */
1467 switch (cmd_pp.Instruction) {
1468 case SPI_NOR_CMD_PP_4B:
1469 __fallthrough;
1470 case SPI_NOR_CMD_PP:
1471 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1472 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1473 cmd_pp.DataMode = HAL_OSPI_DATA_1_LINE;
1474 break;
1475 case SPI_NOR_CMD_PP_1_1_2:
1476 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1477 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1478 cmd_pp.DataMode = HAL_OSPI_DATA_2_LINES;
1479 break;
1480 case SPI_NOR_CMD_PP_1_1_4_4B:
1481 __fallthrough;
1482 case SPI_NOR_CMD_PP_1_1_4:
1483 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1484 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1485 cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES;
1486 break;
1487 case SPI_NOR_CMD_PP_1_4_4_4B:
1488 __fallthrough;
1489 case SPI_NOR_CMD_PP_1_4_4:
1490 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1491 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
1492 cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES;
1493 break;
1494 default:
1495 /* Use lines based on data mode set in ospi_prepare_cmd */
1496 break;
1497 }
1498
1499 cmd_pp.Address = addr;
1500 cmd_pp.AddressSize = stm32_ospi_hal_address_size(dev);
1501 cmd_pp.DummyCycles = 0U;
1502
1503 LOG_DBG("OSPI: write %zu data", size);
1504
1505 ret = stm32_ospi_mem_ready(dev_data,
1506 dev_cfg->data_mode, dev_cfg->data_rate);
1507 if (ret != 0) {
1508 ospi_unlock_thread(dev);
1509 LOG_ERR("OSPI: write not ready");
1510 return -EIO;
1511 }
1512
1513 while ((size > 0) && (ret == 0)) {
1514 to_write = size;
1515 ret = stm32_ospi_write_enable(dev_data,
1516 dev_cfg->data_mode, dev_cfg->data_rate);
1517 if (ret != 0) {
1518 LOG_ERR("OSPI: write not enabled");
1519 break;
1520 }
1521 /* Don't write more than a page. */
1522 if (to_write >= SPI_NOR_PAGE_SIZE) {
1523 to_write = SPI_NOR_PAGE_SIZE;
1524 }
1525
1526 /* Don't write across a page boundary */
1527 if (((addr + to_write - 1U) / SPI_NOR_PAGE_SIZE)
1528 != (addr / SPI_NOR_PAGE_SIZE)) {
1529 to_write = SPI_NOR_PAGE_SIZE -
1530 (addr % SPI_NOR_PAGE_SIZE);
1531 }
1532 cmd_pp.Address = addr;
1533
1534 ret = ospi_write_access(dev, &cmd_pp, data, to_write);
1535 if (ret != 0) {
1536 LOG_ERR("OSPI: write not access");
1537 break;
1538 }
1539
1540 size -= to_write;
1541 data = (const uint8_t *)data + to_write;
1542 addr += to_write;
1543
1544 /* Configure automatic polling mode to wait for end of program */
1545 ret = stm32_ospi_mem_ready(dev_data,
1546 dev_cfg->data_mode, dev_cfg->data_rate);
1547 if (ret != 0) {
1548 LOG_ERR("OSPI: write PP not ready");
1549 break;
1550 }
1551 }
1552 goto end_write;
1553
1554 end_write:
1555 ospi_unlock_thread(dev);
1556
1557 return ret;
1558 }
1559
1560 static const struct flash_parameters flash_stm32_ospi_parameters = {
1561 .write_block_size = 1,
1562 .erase_value = 0xff
1563 };
1564
1565 static const struct flash_parameters *
flash_stm32_ospi_get_parameters(const struct device * dev)1566 flash_stm32_ospi_get_parameters(const struct device *dev)
1567 {
1568 ARG_UNUSED(dev);
1569
1570 return &flash_stm32_ospi_parameters;
1571 }
1572
flash_stm32_ospi_isr(const struct device * dev)1573 static void flash_stm32_ospi_isr(const struct device *dev)
1574 {
1575 struct flash_stm32_ospi_data *dev_data = dev->data;
1576
1577 HAL_OSPI_IRQHandler(&dev_data->hospi);
1578 }
1579
1580 #if !defined(CONFIG_SOC_SERIES_STM32H7X)
1581 /* weak function required for HAL compilation */
HAL_DMA_Abort_IT(DMA_HandleTypeDef * hdma)1582 __weak HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
1583 {
1584 return HAL_OK;
1585 }
1586
1587 /* weak function required for HAL compilation */
HAL_DMA_Abort(DMA_HandleTypeDef * hdma)1588 __weak HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
1589 {
1590 return HAL_OK;
1591 }
1592 #endif /* !CONFIG_SOC_SERIES_STM32H7X */
1593
1594 /* This function is executed in the interrupt context */
1595 #if STM32_OSPI_USE_DMA
ospi_dma_callback(const struct device * dev,void * arg,uint32_t channel,int status)1596 static void ospi_dma_callback(const struct device *dev, void *arg,
1597 uint32_t channel, int status)
1598 {
1599 DMA_HandleTypeDef *hdma = arg;
1600
1601 ARG_UNUSED(dev);
1602
1603 if (status < 0) {
1604 LOG_ERR("DMA callback error with channel %d.", channel);
1605 }
1606
1607 HAL_DMA_IRQHandler(hdma);
1608 }
1609 #endif
1610
1611 /*
1612 * Transfer Error callback.
1613 */
HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef * hospi)1614 void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi)
1615 {
1616 struct flash_stm32_ospi_data *dev_data =
1617 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1618
1619 LOG_DBG("Error cb");
1620
1621 dev_data->cmd_status = -EIO;
1622
1623 k_sem_give(&dev_data->sync);
1624 }
1625
1626 /*
1627 * Command completed callback.
1628 */
HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef * hospi)1629 void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
1630 {
1631 struct flash_stm32_ospi_data *dev_data =
1632 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1633
1634 LOG_DBG("Cmd Cplt cb");
1635
1636 k_sem_give(&dev_data->sync);
1637 }
1638
1639 /*
1640 * Rx Transfer completed callback.
1641 */
HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef * hospi)1642 void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
1643 {
1644 struct flash_stm32_ospi_data *dev_data =
1645 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1646
1647 LOG_DBG("Rx Cplt cb");
1648
1649 k_sem_give(&dev_data->sync);
1650 }
1651
1652 /*
1653 * Tx Transfer completed callback.
1654 */
HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef * hospi)1655 void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
1656 {
1657 struct flash_stm32_ospi_data *dev_data =
1658 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1659
1660 LOG_DBG("Tx Cplt cb");
1661
1662 k_sem_give(&dev_data->sync);
1663 }
1664
1665 /*
1666 * Status Match callback.
1667 */
HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef * hospi)1668 void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi)
1669 {
1670 struct flash_stm32_ospi_data *dev_data =
1671 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1672
1673 LOG_DBG("Status Match cb");
1674
1675 k_sem_give(&dev_data->sync);
1676 }
1677
1678 /*
1679 * Timeout callback.
1680 */
HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef * hospi)1681 void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
1682 {
1683 struct flash_stm32_ospi_data *dev_data =
1684 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1685
1686 LOG_DBG("Timeout cb");
1687
1688 dev_data->cmd_status = -EIO;
1689
1690 k_sem_give(&dev_data->sync);
1691 }
1692
1693 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_stm32_ospi_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)1694 static void flash_stm32_ospi_pages_layout(const struct device *dev,
1695 const struct flash_pages_layout **layout,
1696 size_t *layout_size)
1697 {
1698 struct flash_stm32_ospi_data *dev_data = dev->data;
1699
1700 *layout = &dev_data->layout;
1701 *layout_size = 1;
1702 }
1703 #endif
1704
1705 static DEVICE_API(flash, flash_stm32_ospi_driver_api) = {
1706 .read = flash_stm32_ospi_read,
1707 .write = flash_stm32_ospi_write,
1708 .erase = flash_stm32_ospi_erase,
1709 .get_parameters = flash_stm32_ospi_get_parameters,
1710 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1711 .page_layout = flash_stm32_ospi_pages_layout,
1712 #endif
1713 #if defined(CONFIG_FLASH_JESD216_API)
1714 .sfdp_read = ospi_read_sfdp,
1715 .read_jedec_id = ospi_read_jedec_id,
1716 #endif /* CONFIG_FLASH_JESD216_API */
1717 };
1718
1719 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
setup_pages_layout(const struct device * dev)1720 static int setup_pages_layout(const struct device *dev)
1721 {
1722 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1723 struct flash_stm32_ospi_data *data = dev->data;
1724 const size_t flash_size = dev_cfg->flash_size;
1725 uint32_t layout_page_size = data->page_size;
1726 uint8_t value = 0;
1727 int rv = 0;
1728
1729 /* Find the smallest erase size. */
1730 for (size_t i = 0; i < ARRAY_SIZE(data->erase_types); ++i) {
1731 const struct jesd216_erase_type *etp = &data->erase_types[i];
1732
1733 if ((etp->cmd != 0)
1734 && ((value == 0) || (etp->exp < value))) {
1735 value = etp->exp;
1736 }
1737 }
1738
1739 uint32_t erase_size = BIT(value);
1740
1741 if (erase_size == 0) {
1742 erase_size = SPI_NOR_SECTOR_SIZE;
1743 }
1744
1745 /* We need layout page size to be compatible with erase size */
1746 if ((layout_page_size % erase_size) != 0) {
1747 LOG_DBG("layout page %u not compatible with erase size %u",
1748 layout_page_size, erase_size);
1749 LOG_DBG("erase size will be used as layout page size");
1750 layout_page_size = erase_size;
1751 }
1752
1753 /* Warn but accept layout page sizes that leave inaccessible
1754 * space.
1755 */
1756 if ((flash_size % layout_page_size) != 0) {
1757 LOG_DBG("layout page %u wastes space with device size %zu",
1758 layout_page_size, flash_size);
1759 }
1760
1761 data->layout.pages_size = layout_page_size;
1762 data->layout.pages_count = flash_size / layout_page_size;
1763 LOG_DBG("layout %u x %u By pages", data->layout.pages_count,
1764 data->layout.pages_size);
1765
1766 return rv;
1767 }
1768 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
1769
stm32_ospi_read_status_register(const struct device * dev,uint8_t reg_num,uint8_t * reg)1770 static int stm32_ospi_read_status_register(const struct device *dev, uint8_t reg_num, uint8_t *reg)
1771 {
1772 OSPI_RegularCmdTypeDef s_command = {
1773 .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
1774 .DataMode = HAL_OSPI_DATA_1_LINE,
1775 };
1776
1777 switch (reg_num) {
1778 case 1U:
1779 s_command.Instruction = SPI_NOR_CMD_RDSR;
1780 break;
1781 case 2U:
1782 s_command.Instruction = SPI_NOR_CMD_RDSR2;
1783 break;
1784 case 3U:
1785 s_command.Instruction = SPI_NOR_CMD_RDSR3;
1786 break;
1787 default:
1788 return -EINVAL;
1789 }
1790
1791 return ospi_read_access(dev, &s_command, reg, sizeof(*reg));
1792 }
1793
stm32_ospi_write_status_register(const struct device * dev,uint8_t reg_num,uint8_t reg)1794 static int stm32_ospi_write_status_register(const struct device *dev, uint8_t reg_num, uint8_t reg)
1795 {
1796 struct flash_stm32_ospi_data *data = dev->data;
1797 OSPI_RegularCmdTypeDef s_command = {
1798 .Instruction = SPI_NOR_CMD_WRSR,
1799 .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
1800 .DataMode = HAL_OSPI_DATA_1_LINE
1801 };
1802 size_t size;
1803 uint8_t regs[4] = { 0 };
1804 uint8_t *regs_p;
1805 int ret;
1806
1807 if (reg_num == 1U) {
1808 size = 1U;
1809 regs[0] = reg;
1810 regs_p = ®s[0];
1811 /* 1 byte write clears SR2, write SR2 as well */
1812 if (data->qer_type == JESD216_DW15_QER_S2B1v1) {
1813 ret = stm32_ospi_read_status_register(dev, 2, ®s[1]);
1814 if (ret < 0) {
1815 return ret;
1816 }
1817 size = 2U;
1818 }
1819 } else if (reg_num == 2U) {
1820 s_command.Instruction = SPI_NOR_CMD_WRSR2;
1821 size = 1U;
1822 regs[1] = reg;
1823 regs_p = ®s[1];
1824 /* if SR2 write needs SR1 */
1825 if ((data->qer_type == JESD216_DW15_QER_VAL_S2B1v1) ||
1826 (data->qer_type == JESD216_DW15_QER_VAL_S2B1v4) ||
1827 (data->qer_type == JESD216_DW15_QER_VAL_S2B1v5)) {
1828 ret = stm32_ospi_read_status_register(dev, 1, ®s[0]);
1829 if (ret < 0) {
1830 return ret;
1831 }
1832 s_command.Instruction = SPI_NOR_CMD_WRSR;
1833 size = 2U;
1834 regs_p = ®s[0];
1835 }
1836 } else if (reg_num == 3U) {
1837 s_command.Instruction = SPI_NOR_CMD_WRSR3;
1838 size = 1U;
1839 regs[2] = reg;
1840 regs_p = ®s[2];
1841 } else {
1842 return -EINVAL;
1843 }
1844
1845 return ospi_write_access(dev, &s_command, regs_p, size);
1846 }
1847
stm32_ospi_enable_qe(const struct device * dev)1848 static int stm32_ospi_enable_qe(const struct device *dev)
1849 {
1850 struct flash_stm32_ospi_data *data = dev->data;
1851 uint8_t qe_reg_num;
1852 uint8_t qe_bit;
1853 uint8_t reg;
1854 int ret;
1855
1856 switch (data->qer_type) {
1857 case JESD216_DW15_QER_NONE:
1858 /* no QE bit, device detects reads based on opcode */
1859 return 0;
1860 case JESD216_DW15_QER_S1B6:
1861 qe_reg_num = 1U;
1862 qe_bit = BIT(6U);
1863 break;
1864 case JESD216_DW15_QER_S2B7:
1865 qe_reg_num = 2U;
1866 qe_bit = BIT(7U);
1867 break;
1868 case JESD216_DW15_QER_S2B1v1:
1869 __fallthrough;
1870 case JESD216_DW15_QER_S2B1v4:
1871 __fallthrough;
1872 case JESD216_DW15_QER_S2B1v5:
1873 __fallthrough;
1874 case JESD216_DW15_QER_S2B1v6:
1875 qe_reg_num = 2U;
1876 qe_bit = BIT(1U);
1877 break;
1878 default:
1879 return -ENOTSUP;
1880 }
1881
1882 ret = stm32_ospi_read_status_register(dev, qe_reg_num, ®);
1883 if (ret < 0) {
1884 return ret;
1885 }
1886
1887 /* exit early if QE bit is already set */
1888 if ((reg & qe_bit) != 0U) {
1889 return 0;
1890 }
1891
1892 ret = stm32_ospi_write_enable(data, OSPI_SPI_MODE, OSPI_STR_TRANSFER);
1893 if (ret < 0) {
1894 return ret;
1895 }
1896
1897 reg |= qe_bit;
1898
1899 ret = stm32_ospi_write_status_register(dev, qe_reg_num, reg);
1900 if (ret < 0) {
1901 return ret;
1902 }
1903
1904 ret = stm32_ospi_mem_ready(data, OSPI_SPI_MODE, OSPI_STR_TRANSFER);
1905 if (ret < 0) {
1906 return ret;
1907 }
1908
1909 /* validate that QE bit is set */
1910 ret = stm32_ospi_read_status_register(dev, qe_reg_num, ®);
1911 if (ret < 0) {
1912 return ret;
1913 }
1914
1915 if ((reg & qe_bit) == 0U) {
1916 LOG_ERR("Status Register %u [0x%02x] not set", qe_reg_num, reg);
1917 ret = -EIO;
1918 }
1919
1920 return ret;
1921 }
1922
spi_nor_process_bfp_addrbytes(const struct device * dev,const uint8_t jesd216_bfp_addrbytes)1923 static void spi_nor_process_bfp_addrbytes(const struct device *dev,
1924 const uint8_t jesd216_bfp_addrbytes)
1925 {
1926 struct flash_stm32_ospi_data *data = dev->data;
1927
1928 if ((jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B) ||
1929 (jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B4B)) {
1930 data->address_width = 4U;
1931 } else {
1932 data->address_width = 3U;
1933 }
1934 }
1935
spi_nor_convert_read_to_4b(const uint8_t opcode)1936 static inline uint8_t spi_nor_convert_read_to_4b(const uint8_t opcode)
1937 {
1938 switch (opcode) {
1939 case SPI_NOR_CMD_READ:
1940 return SPI_NOR_CMD_READ_4B;
1941 case SPI_NOR_CMD_DREAD:
1942 return SPI_NOR_CMD_DREAD_4B;
1943 case SPI_NOR_CMD_2READ:
1944 return SPI_NOR_CMD_2READ_4B;
1945 case SPI_NOR_CMD_QREAD:
1946 return SPI_NOR_CMD_QREAD_4B;
1947 case SPI_NOR_CMD_4READ:
1948 return SPI_NOR_CMD_4READ_4B;
1949 default:
1950 /* use provided */
1951 return opcode;
1952 }
1953 }
1954
spi_nor_convert_write_to_4b(const uint8_t opcode)1955 static inline uint8_t spi_nor_convert_write_to_4b(const uint8_t opcode)
1956 {
1957 switch (opcode) {
1958 case SPI_NOR_CMD_PP:
1959 return SPI_NOR_CMD_PP_4B;
1960 case SPI_NOR_CMD_PP_1_1_4:
1961 return SPI_NOR_CMD_PP_1_1_4_4B;
1962 case SPI_NOR_CMD_PP_1_4_4:
1963 return SPI_NOR_CMD_PP_1_4_4_4B;
1964 default:
1965 /* use provided */
1966 return opcode;
1967 }
1968 }
1969
spi_nor_process_bfp(const struct device * dev,const struct jesd216_param_header * php,const struct jesd216_bfp * bfp)1970 static int spi_nor_process_bfp(const struct device *dev,
1971 const struct jesd216_param_header *php,
1972 const struct jesd216_bfp *bfp)
1973 {
1974 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1975 struct flash_stm32_ospi_data *data = dev->data;
1976 /* must be kept in data mode order, ignore 1-1-1 (always supported) */
1977 const enum jesd216_mode_type supported_read_modes[] = { JESD216_MODE_112, JESD216_MODE_122,
1978 JESD216_MODE_114,
1979 JESD216_MODE_144 };
1980 size_t supported_read_modes_max_idx;
1981 struct jesd216_erase_type *etp = data->erase_types;
1982 size_t idx;
1983 const size_t flash_size = jesd216_bfp_density(bfp) / 8U;
1984 struct jesd216_instr read_instr = { 0 };
1985 struct jesd216_bfp_dw15 dw15;
1986
1987 if (flash_size != dev_cfg->flash_size) {
1988 LOG_DBG("Unexpected flash size: %u", flash_size);
1989 }
1990
1991 LOG_DBG("%s: %u MiBy flash", dev->name, (uint32_t)(flash_size >> 20));
1992
1993 /* Copy over the erase types, preserving their order. (The
1994 * Sector Map Parameter table references them by index.)
1995 */
1996 memset(data->erase_types, 0, sizeof(data->erase_types));
1997 for (idx = 1U; idx <= ARRAY_SIZE(data->erase_types); ++idx) {
1998 if (jesd216_bfp_erase(bfp, idx, etp) == 0) {
1999 LOG_DBG("Erase %u with %02x",
2000 (uint32_t)BIT(etp->exp), etp->cmd);
2001 }
2002 ++etp;
2003 }
2004
2005 spi_nor_process_bfp_addrbytes(dev, jesd216_bfp_addrbytes(bfp));
2006 LOG_DBG("Address width: %u Bytes", data->address_width);
2007
2008 /* use PP opcode based on configured data mode if nothing is set in DTS */
2009 if (data->write_opcode == SPI_NOR_WRITEOC_NONE) {
2010 switch (dev_cfg->data_mode) {
2011 case OSPI_OPI_MODE:
2012 data->write_opcode = SPI_NOR_OCMD_PAGE_PRG;
2013 break;
2014 case OSPI_QUAD_MODE:
2015 data->write_opcode = SPI_NOR_CMD_PP_1_4_4;
2016 break;
2017 case OSPI_DUAL_MODE:
2018 data->write_opcode = SPI_NOR_CMD_PP_1_1_2;
2019 break;
2020 default:
2021 data->write_opcode = SPI_NOR_CMD_PP;
2022 break;
2023 }
2024 }
2025
2026 if (dev_cfg->data_mode != OSPI_OPI_MODE) {
2027 /* determine supported read modes, begin from the slowest */
2028 data->read_mode = JESD216_MODE_111;
2029 data->read_opcode = SPI_NOR_CMD_READ;
2030 data->read_dummy = 0U;
2031
2032 if (dev_cfg->data_mode != OSPI_SPI_MODE) {
2033 if (dev_cfg->data_mode == OSPI_DUAL_MODE) {
2034 /* the index of JESD216_MODE_114 in supported_read_modes */
2035 supported_read_modes_max_idx = 2U;
2036 } else {
2037 supported_read_modes_max_idx = ARRAY_SIZE(supported_read_modes);
2038 }
2039
2040 for (idx = 0U; idx < supported_read_modes_max_idx; ++idx) {
2041 if (jesd216_bfp_read_support(php, bfp, supported_read_modes[idx],
2042 &read_instr) < 0) {
2043 /* not supported */
2044 continue;
2045 }
2046
2047 LOG_DBG("Supports read mode: %d, instr: 0x%X",
2048 supported_read_modes[idx], read_instr.instr);
2049 data->read_mode = supported_read_modes[idx];
2050 data->read_opcode = read_instr.instr;
2051 data->read_dummy =
2052 (read_instr.wait_states + read_instr.mode_clocks);
2053 }
2054 }
2055
2056 /* convert 3-Byte opcodes to 4-Byte (if required) */
2057 if (IS_ENABLED(DT_INST_PROP(0, four_byte_opcodes))) {
2058 if (data->address_width != 4U) {
2059 LOG_DBG("4-Byte opcodes require 4-Byte address width");
2060 return -ENOTSUP;
2061 }
2062 data->read_opcode = spi_nor_convert_read_to_4b(data->read_opcode);
2063 data->write_opcode = spi_nor_convert_write_to_4b(data->write_opcode);
2064 }
2065
2066 /* enable quad mode (if required) */
2067 if (dev_cfg->data_mode == OSPI_QUAD_MODE) {
2068 if (jesd216_bfp_decode_dw15(php, bfp, &dw15) < 0) {
2069 /* will use QER from DTS or default (refer to device data) */
2070 LOG_WRN("Unable to decode QE requirement [DW15]");
2071 } else {
2072 /* bypass DTS QER value */
2073 data->qer_type = dw15.qer;
2074 }
2075
2076 LOG_DBG("QE requirement mode: %x", data->qer_type);
2077
2078 if (stm32_ospi_enable_qe(dev) < 0) {
2079 LOG_ERR("Failed to enable QUAD mode");
2080 return -EIO;
2081 }
2082
2083 LOG_DBG("QUAD mode enabled");
2084 }
2085 }
2086
2087 data->page_size = jesd216_bfp_page_size(php, bfp);
2088
2089 LOG_DBG("Page size %u bytes", data->page_size);
2090 LOG_DBG("Flash size %zu bytes", flash_size);
2091 LOG_DBG("Using read mode: %d, instr: 0x%X, dummy cycles: %u",
2092 data->read_mode, data->read_opcode, data->read_dummy);
2093 LOG_DBG("Using write instr: 0x%X", data->write_opcode);
2094
2095 return 0;
2096 }
2097
flash_stm32_ospi_init(const struct device * dev)2098 static int flash_stm32_ospi_init(const struct device *dev)
2099 {
2100 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
2101 struct flash_stm32_ospi_data *dev_data = dev->data;
2102 uint32_t ahb_clock_freq;
2103 uint32_t prescaler = STM32_OSPI_CLOCK_PRESCALER_MIN;
2104 int ret;
2105
2106 /* The SPI/DTR is not a valid config of data_mode/data_rate according to the DTS */
2107 if ((dev_cfg->data_mode != OSPI_OPI_MODE)
2108 && (dev_cfg->data_rate == OSPI_DTR_TRANSFER)) {
2109 /* already the right config, continue */
2110 LOG_ERR("OSPI mode SPI|DUAL|QUAD/DTR is not valid");
2111 return -ENOTSUP;
2112 }
2113
2114 /* Signals configuration */
2115 ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
2116 if (ret < 0) {
2117 LOG_ERR("OSPI pinctrl setup failed (%d)", ret);
2118 return ret;
2119 }
2120
2121 if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
2122 LOG_ERR("clock control device not ready");
2123 return -ENODEV;
2124 }
2125
2126 #ifdef CONFIG_STM32_MEMMAP
2127 /* If MemoryMapped then configure skip init */
2128 if (stm32_ospi_is_memorymap(dev)) {
2129 LOG_DBG("NOR init'd in MemMapped mode\n");
2130 /* Force HAL instance in correct state */
2131 dev_data->hospi.State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
2132 return 0;
2133 }
2134 #endif /* CONFIG_STM32_MEMMAP */
2135
2136 #if STM32_OSPI_USE_DMA
2137 /*
2138 * DMA configuration
2139 * Due to use of OSPI HAL API in current driver,
2140 * both HAL and Zephyr DMA drivers should be configured.
2141 * The required configuration for Zephyr DMA driver should only provide
2142 * the minimum information to inform the DMA slot will be in used and
2143 * how to route callbacks.
2144 */
2145 struct dma_config dma_cfg = dev_data->dma.cfg;
2146 static DMA_HandleTypeDef hdma;
2147
2148 if (!device_is_ready(dev_data->dma.dev)) {
2149 LOG_ERR("%s device not ready", dev_data->dma.dev->name);
2150 return -ENODEV;
2151 }
2152
2153 /* Proceed to the minimum Zephyr DMA driver init */
2154 dma_cfg.user_data = &hdma;
2155 /* HACK: This field is used to inform driver that it is overridden */
2156 dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
2157 /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
2158 ret = dma_config(dev_data->dma.dev,
2159 (dev_data->dma.channel + STM32_DMA_STREAM_OFFSET), &dma_cfg);
2160 if (ret != 0) {
2161 LOG_ERR("Failed to configure DMA channel %d",
2162 dev_data->dma.channel + STM32_DMA_STREAM_OFFSET);
2163 return ret;
2164 }
2165
2166 /* Proceed to the HAL DMA driver init */
2167 if (dma_cfg.source_data_size != dma_cfg.dest_data_size) {
2168 LOG_ERR("Source and destination data sizes not aligned");
2169 return -EINVAL;
2170 }
2171
2172 int index = find_lsb_set(dma_cfg.source_data_size) - 1;
2173
2174 #if CONFIG_DMA_STM32U5
2175 /* Fill the structure for dma init */
2176 hdma.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
2177 hdma.Init.SrcInc = DMA_SINC_FIXED;
2178 hdma.Init.DestInc = DMA_DINC_INCREMENTED;
2179 hdma.Init.SrcDataWidth = table_src_size[index];
2180 hdma.Init.DestDataWidth = table_dest_size[index];
2181 hdma.Init.SrcBurstLength = 4;
2182 hdma.Init.DestBurstLength = 4;
2183 hdma.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT1;
2184 hdma.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
2185 #else
2186 hdma.Init.PeriphDataAlignment = table_p_size[index];
2187 hdma.Init.MemDataAlignment = table_m_size[index];
2188 hdma.Init.PeriphInc = DMA_PINC_DISABLE;
2189 hdma.Init.MemInc = DMA_MINC_ENABLE;
2190 #endif /* CONFIG_DMA_STM32U5 */
2191 hdma.Init.Mode = DMA_NORMAL;
2192 hdma.Init.Priority = table_priority[dma_cfg.channel_priority];
2193 hdma.Init.Direction = DMA_PERIPH_TO_MEMORY;
2194 #ifdef CONFIG_DMA_STM32_V1
2195 /* TODO: Not tested in this configuration */
2196 hdma.Init.Channel = dma_cfg.dma_slot;
2197 hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg,
2198 dev_data->dma.channel);
2199 #else
2200 hdma.Init.Request = dma_cfg.dma_slot;
2201 #if CONFIG_DMA_STM32U5
2202 hdma.Instance = LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
2203 dev_data->dma.channel);
2204 #elif defined(CONFIG_DMAMUX_STM32)
2205 /*
2206 * HAL expects a valid DMA channel (not DMAMUX).
2207 * The channel is from 0 to 7 because of the STM32_DMA_STREAM_OFFSET in the dma_stm32 driver
2208 */
2209 hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
2210 dev_data->dma.channel);
2211 #else
2212 hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
2213 dev_data->dma.channel-1);
2214 #endif /* CONFIG_DMA_STM32U5 */
2215 #endif /* CONFIG_DMA_STM32_V1 */
2216
2217 /* Initialize DMA HAL */
2218 __HAL_LINKDMA(&dev_data->hospi, hdma, hdma);
2219 if (HAL_DMA_Init(&hdma) != HAL_OK) {
2220 LOG_ERR("OSPI DMA Init failed");
2221 return -EIO;
2222 }
2223 LOG_INF("OSPI with DMA transfer");
2224
2225 #endif /* STM32_OSPI_USE_DMA */
2226
2227 /* Clock configuration */
2228 if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2229 (clock_control_subsys_t) &dev_cfg->pclken) != 0) {
2230 LOG_ERR("Could not enable OSPI clock");
2231 return -EIO;
2232 }
2233 /* Alternate clock config for peripheral if any */
2234 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_ker)
2235 if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2236 (clock_control_subsys_t) &dev_cfg->pclken_ker,
2237 NULL) != 0) {
2238 LOG_ERR("Could not select OSPI domain clock");
2239 return -EIO;
2240 }
2241 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2242 (clock_control_subsys_t) &dev_cfg->pclken_ker,
2243 &ahb_clock_freq) < 0) {
2244 LOG_ERR("Failed call clock_control_get_rate(pclken_ker)");
2245 return -EIO;
2246 }
2247 #else
2248 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2249 (clock_control_subsys_t) &dev_cfg->pclken,
2250 &ahb_clock_freq) < 0) {
2251 LOG_ERR("Failed call clock_control_get_rate(pclken)");
2252 return -EIO;
2253 }
2254 #endif
2255 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
2256 if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2257 (clock_control_subsys_t) &dev_cfg->pclken_mgr) != 0) {
2258 LOG_ERR("Could not enable OSPI Manager clock");
2259 return -EIO;
2260 }
2261 #endif
2262
2263 for (; prescaler <= STM32_OSPI_CLOCK_PRESCALER_MAX; prescaler++) {
2264 uint32_t clk = STM32_OSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler);
2265
2266 if (clk <= dev_cfg->max_frequency) {
2267 break;
2268 }
2269 }
2270 __ASSERT_NO_MSG(prescaler >= STM32_OSPI_CLOCK_PRESCALER_MIN &&
2271 prescaler <= STM32_OSPI_CLOCK_PRESCALER_MAX);
2272
2273 /* Initialize OSPI HAL structure completely */
2274 dev_data->hospi.Init.FifoThreshold = 4;
2275 dev_data->hospi.Init.ClockPrescaler = prescaler;
2276 #if defined(CONFIG_SOC_SERIES_STM32H5X)
2277 /* The stm32h5xx_hal_xspi does not reduce DEVSIZE before writing the DCR1 */
2278 dev_data->hospi.Init.DeviceSize = find_lsb_set(dev_cfg->flash_size) - 2;
2279 #else
2280 /* Give a bit position from 0 to 31 to the HAL init for the DCR1 reg */
2281 dev_data->hospi.Init.DeviceSize = find_lsb_set(dev_cfg->flash_size) - 1;
2282 #endif /* CONFIG_SOC_SERIES_STM32U5X */
2283 dev_data->hospi.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
2284 dev_data->hospi.Init.ChipSelectHighTime = 2;
2285 dev_data->hospi.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
2286 dev_data->hospi.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;
2287 #if defined(OCTOSPI_DCR2_WRAPSIZE)
2288 dev_data->hospi.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
2289 #endif /* OCTOSPI_DCR2_WRAPSIZE */
2290 /* STR mode else Macronix for DTR mode */
2291 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
2292 dev_data->hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX;
2293 dev_data->hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;
2294 } else {
2295 dev_data->hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;
2296 dev_data->hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE;
2297 }
2298 dev_data->hospi.Init.ChipSelectBoundary = 0;
2299 #if STM32_OSPI_DLYB_BYPASSED
2300 dev_data->hospi.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED;
2301 #else
2302 dev_data->hospi.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED;
2303 #endif /* STM32_OSPI_DLYB_BYPASSED */
2304 #if defined(OCTOSPI_DCR4_REFRESH)
2305 dev_data->hospi.Init.Refresh = 0;
2306 #endif /* OCTOSPI_DCR4_REFRESH */
2307
2308 if (HAL_OSPI_Init(&dev_data->hospi) != HAL_OK) {
2309 LOG_ERR("OSPI Init failed");
2310 return -EIO;
2311 }
2312
2313 LOG_DBG("OSPI Init'd");
2314
2315 #if defined(OCTOSPIM)
2316 /* OCTOSPI I/O manager init Function */
2317 OSPIM_CfgTypeDef ospi_mgr_cfg = {0};
2318
2319 if (dev_data->hospi.Instance == OCTOSPI1) {
2320 ospi_mgr_cfg.ClkPort = DT_OSPI_PROP_OR(clk_port, 1);
2321 ospi_mgr_cfg.DQSPort = DT_OSPI_PROP_OR(dqs_port, 1);
2322 ospi_mgr_cfg.NCSPort = DT_OSPI_PROP_OR(ncs_port, 1);
2323 ospi_mgr_cfg.IOLowPort = DT_OSPI_IO_PORT_PROP_OR(io_low_port,
2324 HAL_OSPIM_IOPORT_1_LOW);
2325 ospi_mgr_cfg.IOHighPort = DT_OSPI_IO_PORT_PROP_OR(io_high_port,
2326 HAL_OSPIM_IOPORT_1_HIGH);
2327 } else if (dev_data->hospi.Instance == OCTOSPI2) {
2328 ospi_mgr_cfg.ClkPort = DT_OSPI_PROP_OR(clk_port, 2);
2329 ospi_mgr_cfg.DQSPort = DT_OSPI_PROP_OR(dqs_port, 2);
2330 ospi_mgr_cfg.NCSPort = DT_OSPI_PROP_OR(ncs_port, 2);
2331 ospi_mgr_cfg.IOLowPort = DT_OSPI_IO_PORT_PROP_OR(io_low_port,
2332 HAL_OSPIM_IOPORT_2_LOW);
2333 ospi_mgr_cfg.IOHighPort = DT_OSPI_IO_PORT_PROP_OR(io_high_port,
2334 HAL_OSPIM_IOPORT_2_HIGH);
2335 }
2336 #if defined(OCTOSPIM_CR_MUXEN)
2337 ospi_mgr_cfg.Req2AckTime = 1;
2338 #endif /* OCTOSPIM_CR_MUXEN */
2339 if (HAL_OSPIM_Config(&dev_data->hospi, &ospi_mgr_cfg,
2340 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
2341 LOG_ERR("OSPI M config failed");
2342 return -EIO;
2343 }
2344 #if defined(CONFIG_SOC_SERIES_STM32U5X)
2345 /* OCTOSPI2 delay block init Function */
2346 HAL_OSPI_DLYB_CfgTypeDef ospi_delay_block_cfg = {0};
2347
2348 ospi_delay_block_cfg.Units = 56;
2349 ospi_delay_block_cfg.PhaseSel = 2;
2350 if (HAL_OSPI_DLYB_SetConfig(&dev_data->hospi, &ospi_delay_block_cfg) != HAL_OK) {
2351 LOG_ERR("OSPI DelayBlock failed");
2352 return -EIO;
2353 }
2354 #endif /* CONFIG_SOC_SERIES_STM32U5X */
2355
2356 #endif /* OCTOSPIM */
2357
2358 #if defined(CONFIG_SOC_SERIES_STM32H5X)
2359 /* OCTOSPI1 delay block init Function */
2360 HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0};
2361
2362 (void)HAL_XSPI_DLYB_GetClockPeriod(&dev_data->hospi, &xspi_delay_block_cfg);
2363 /* with DTR, set the PhaseSel/4 (empiric value from stm32Cube) */
2364 xspi_delay_block_cfg.PhaseSel /= 4;
2365
2366 if (HAL_XSPI_DLYB_SetConfig(&dev_data->hospi, &xspi_delay_block_cfg) != HAL_OK) {
2367 LOG_ERR("XSPI DelayBlock failed");
2368 return -EIO;
2369 }
2370
2371 LOG_DBG("Delay Block Init");
2372
2373 #endif /* CONFIG_SOC_SERIES_STM32H5X */
2374
2375 /* Initialize semaphores */
2376 k_sem_init(&dev_data->sem, 1, 1);
2377 k_sem_init(&dev_data->sync, 0, 1);
2378
2379 /* Run IRQ init */
2380 dev_cfg->irq_config(dev);
2381
2382 /* Reset NOR flash memory : still with the SPI/STR config for the NOR */
2383 if (stm32_ospi_mem_reset(dev) != 0) {
2384 LOG_ERR("OSPI reset failed");
2385 return -EIO;
2386 }
2387
2388 LOG_DBG("Reset Mem (SPI/STR)");
2389
2390 /* Check if memory is ready in the SPI/STR mode */
2391 if (stm32_ospi_mem_ready(dev_data,
2392 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
2393 LOG_ERR("OSPI memory not ready");
2394 return -EIO;
2395 }
2396
2397 LOG_DBG("Mem Ready (SPI/STR)");
2398
2399 #if defined(CONFIG_FLASH_JESD216_API)
2400 /* Process with the RDID (jedec read ID) instruction at init and fill jedec_id Table */
2401 ret = stm32_ospi_read_jedec_id(dev);
2402 if (ret != 0) {
2403 LOG_ERR("Read ID failed: %d", ret);
2404 return ret;
2405 }
2406 #endif /* CONFIG_FLASH_JESD216_API */
2407
2408 if (stm32_ospi_config_mem(dev) != 0) {
2409 LOG_ERR("OSPI mode not config'd (%u rate %u)",
2410 dev_cfg->data_mode, dev_cfg->data_rate);
2411 return -EIO;
2412 }
2413
2414
2415
2416 /* Send the instruction to read the SFDP */
2417 const uint8_t decl_nph = 2;
2418 union {
2419 /* We only process BFP so use one parameter block */
2420 uint8_t raw[JESD216_SFDP_SIZE(decl_nph)];
2421 struct jesd216_sfdp_header sfdp;
2422 } u;
2423 const struct jesd216_sfdp_header *hp = &u.sfdp;
2424
2425 ret = ospi_read_sfdp(dev, 0, u.raw, sizeof(u.raw));
2426 if (ret != 0) {
2427 LOG_ERR("SFDP read failed: %d", ret);
2428 return ret;
2429 }
2430
2431 uint32_t magic = jesd216_sfdp_magic(hp);
2432
2433 if (magic != JESD216_SFDP_MAGIC) {
2434 LOG_ERR("SFDP magic %08x invalid", magic);
2435 return -EINVAL;
2436 }
2437
2438 LOG_DBG("%s: SFDP v %u.%u AP %x with %u PH", dev->name,
2439 hp->rev_major, hp->rev_minor, hp->access, 1 + hp->nph);
2440
2441 const struct jesd216_param_header *php = hp->phdr;
2442 const struct jesd216_param_header *phpe = php +
2443 MIN(decl_nph, 1 + hp->nph);
2444
2445 while (php != phpe) {
2446 uint16_t id = jesd216_param_id(php);
2447
2448 LOG_DBG("PH%u: %04x rev %u.%u: %u DW @ %x",
2449 (php - hp->phdr), id, php->rev_major, php->rev_minor,
2450 php->len_dw, jesd216_param_addr(php));
2451
2452 if (id == JESD216_SFDP_PARAM_ID_BFP) {
2453 union {
2454 uint32_t dw[20];
2455 struct jesd216_bfp bfp;
2456 } u2;
2457 const struct jesd216_bfp *bfp = &u2.bfp;
2458
2459 ret = ospi_read_sfdp(dev, jesd216_param_addr(php),
2460 (uint8_t *)u2.dw,
2461 MIN(sizeof(uint32_t) * php->len_dw, sizeof(u2.dw)));
2462 if (ret == 0) {
2463 ret = spi_nor_process_bfp(dev, php, bfp);
2464 }
2465
2466 if (ret != 0) {
2467 LOG_ERR("SFDP BFP failed: %d", ret);
2468 break;
2469 }
2470 }
2471 if (id == JESD216_SFDP_PARAM_ID_4B_ADDR_INSTR) {
2472
2473 if (dev_data->address_width == 4U) {
2474 /*
2475 * Check table 4 byte address instruction table to get supported
2476 * erase opcodes when running in 4 byte address mode
2477 */
2478 union {
2479 uint32_t dw[2];
2480 struct {
2481 uint32_t dummy;
2482 uint8_t type[4];
2483 } types;
2484 } u2;
2485 ret = ospi_read_sfdp(dev, jesd216_param_addr(php),
2486 (uint8_t *)u2.dw,
2487 MIN(sizeof(uint32_t) * php->len_dw, sizeof(u2.dw)));
2488 if (ret != 0) {
2489 break;
2490 }
2491 for (uint8_t ei = 0; ei < JESD216_NUM_ERASE_TYPES; ++ei) {
2492 struct jesd216_erase_type *etp = &dev_data->erase_types[ei];
2493 const uint8_t cmd = u2.types.type[ei];
2494 /* 0xff means not supported */
2495 if (cmd == 0xff) {
2496 etp->exp = 0;
2497 etp->cmd = 0;
2498 } else {
2499 etp->cmd = cmd;
2500 };
2501 }
2502 }
2503 }
2504 ++php;
2505 }
2506
2507 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
2508 ret = setup_pages_layout(dev);
2509 if (ret != 0) {
2510 LOG_ERR("layout setup failed: %d", ret);
2511 return -ENODEV;
2512 }
2513 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
2514
2515 #ifdef CONFIG_STM32_MEMMAP
2516 /* Now configure the octo Flash in MemoryMapped (access by address) */
2517 ret = stm32_ospi_set_memorymap(dev);
2518 if (ret != 0) {
2519 LOG_ERR("Error (%d): setting NOR in MemoryMapped mode", ret);
2520 return -EINVAL;
2521 }
2522 LOG_DBG("NOR octo-flash in MemoryMapped mode at 0x%lx (0x%x bytes)",
2523 (long)(STM32_OSPI_BASE_ADDRESS),
2524 dev_cfg->flash_size);
2525 #else
2526 LOG_DBG("NOR octo-flash at 0x%lx (0x%x bytes)",
2527 (long)(STM32_OSPI_BASE_ADDRESS),
2528 dev_cfg->flash_size);
2529 #endif /* CONFIG_STM32_MEMMAP */
2530
2531 return 0;
2532 }
2533
2534 #if STM32_OSPI_USE_DMA
2535 #define DMA_CHANNEL_CONFIG(node, dir) \
2536 DT_DMAS_CELL_BY_NAME(node, dir, channel_config)
2537
2538 #define OSPI_DMA_CHANNEL_INIT(node, dir) \
2539 .dev = DEVICE_DT_GET(DT_DMAS_CTLR(node)), \
2540 .channel = DT_DMAS_CELL_BY_NAME(node, dir, channel), \
2541 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
2542 DT_PHANDLE_BY_NAME(node, dmas, dir)),\
2543 .cfg = { \
2544 .dma_slot = DT_DMAS_CELL_BY_NAME(node, dir, slot), \
2545 .source_data_size = STM32_DMA_CONFIG_PERIPHERAL_DATA_SIZE( \
2546 DMA_CHANNEL_CONFIG(node, dir)), \
2547 .dest_data_size = STM32_DMA_CONFIG_MEMORY_DATA_SIZE( \
2548 DMA_CHANNEL_CONFIG(node, dir)), \
2549 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
2550 DMA_CHANNEL_CONFIG(node, dir)), \
2551 .dma_callback = ospi_dma_callback, \
2552 }, \
2553
2554 #define OSPI_DMA_CHANNEL(node, dir) \
2555 .dma = { \
2556 COND_CODE_1(DT_DMAS_HAS_NAME(node, dir), \
2557 (OSPI_DMA_CHANNEL_INIT(node, dir)), \
2558 (NULL)) \
2559 },
2560
2561 #else
2562 #define OSPI_DMA_CHANNEL(node, dir)
2563 #endif /* CONFIG_USE_STM32_HAL_DMA */
2564
2565 #define OSPI_FLASH_MODULE(drv_id, flash_id) \
2566 (DT_DRV_INST(drv_id), ospi_nor_flash_##flash_id)
2567
2568 #define DT_WRITEOC_PROP_OR(inst, default_value) \
2569 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, writeoc), \
2570 (_CONCAT(SPI_NOR_CMD_, DT_STRING_TOKEN(DT_DRV_INST(inst), writeoc))), \
2571 ((default_value)))
2572
2573 #define DT_QER_PROP_OR(inst, default_value) \
2574 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, quad_enable_requirements), \
2575 (_CONCAT(JESD216_DW15_QER_VAL_, \
2576 DT_STRING_TOKEN(DT_DRV_INST(inst), quad_enable_requirements))), \
2577 ((default_value)))
2578
2579 static void flash_stm32_ospi_irq_config_func(const struct device *dev);
2580
2581 PINCTRL_DT_DEFINE(STM32_OSPI_NODE);
2582
2583 static const struct flash_stm32_ospi_config flash_stm32_ospi_cfg = {
2584 .regs = (OCTOSPI_TypeDef *)DT_REG_ADDR(STM32_OSPI_NODE),
2585 .pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospix, bus),
2586 .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospix, bits)},
2587 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_ker)
2588 .pclken_ker = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_ker, bus),
2589 .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_ker, bits)},
2590 #endif
2591 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
2592 .pclken_mgr = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_mgr, bus),
2593 .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_mgr, bits)},
2594 #endif
2595 .irq_config = flash_stm32_ospi_irq_config_func,
2596 .flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
2597 .max_frequency = DT_INST_PROP(0, ospi_max_frequency),
2598 .data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */
2599 .data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */
2600 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_OSPI_NODE),
2601 #if STM32_OSPI_RESET_GPIO
2602 .reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
2603 #endif /* STM32_OSPI_RESET_GPIO */
2604 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
2605 .sfdp_bfp = DT_INST_PROP(0, sfdp_bfp),
2606 #endif /* sfdp_bfp */
2607 };
2608
2609 static struct flash_stm32_ospi_data flash_stm32_ospi_dev_data = {
2610 .hospi = {
2611 .Instance = (OCTOSPI_TypeDef *)DT_REG_ADDR(STM32_OSPI_NODE),
2612 .Init = {
2613 .FifoThreshold = STM32_OSPI_FIFO_THRESHOLD,
2614 .SampleShifting = (DT_PROP(STM32_OSPI_NODE, ssht_enable)
2615 ? HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE
2616 : HAL_OSPI_SAMPLE_SHIFTING_NONE),
2617 .ChipSelectHighTime = 1,
2618 .ClockMode = HAL_OSPI_CLOCK_MODE_0,
2619 },
2620 },
2621 .qer_type = DT_QER_PROP_OR(0, JESD216_DW15_QER_VAL_S1B6),
2622 .write_opcode = DT_WRITEOC_PROP_OR(0, SPI_NOR_WRITEOC_NONE),
2623 .page_size = SPI_NOR_PAGE_SIZE, /* by default, to be updated by sfdp */
2624 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), jedec_id)
2625 .jedec_id = DT_INST_PROP(0, jedec_id),
2626 #endif /* jedec_id */
2627 OSPI_DMA_CHANNEL(STM32_OSPI_NODE, tx_rx)
2628 };
2629
2630 DEVICE_DT_INST_DEFINE(0, &flash_stm32_ospi_init, NULL,
2631 &flash_stm32_ospi_dev_data, &flash_stm32_ospi_cfg,
2632 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
2633 &flash_stm32_ospi_driver_api);
2634
flash_stm32_ospi_irq_config_func(const struct device * dev)2635 static void flash_stm32_ospi_irq_config_func(const struct device *dev)
2636 {
2637 IRQ_CONNECT(DT_IRQN(STM32_OSPI_NODE), DT_IRQ(STM32_OSPI_NODE, priority),
2638 flash_stm32_ospi_isr, DEVICE_DT_INST_GET(0), 0);
2639 irq_enable(DT_IRQN(STM32_OSPI_NODE));
2640 }
2641
