1 /*
2 * Copyright (c) 2022 Andriy Gelman, andriy.gelman@gmail.com
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT infineon_xmc4xxx_adc
8
9 #include <errno.h>
10 #include <soc.h>
11 #include <stdint.h>
12 #include <xmc_scu.h>
13 #include <xmc_vadc.h>
14 #include <zephyr/drivers/adc.h>
15 #include <zephyr/device.h>
16 #include <zephyr/irq.h>
17
18 #define ADC_CONTEXT_USES_KERNEL_TIMER
19 #include "adc_context.h"
20
21 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(adc_xmc4xxx);
24
25 #define XMC4XXX_CHANNEL_COUNT 8
26
27 struct adc_xmc4xxx_data {
28 struct adc_context ctx;
29 const struct device *dev;
30 uint16_t *buffer;
31 uint16_t *repeat_buffer;
32 uint8_t channel_mask;
33 };
34
35 struct adc_xmc4xxx_cfg {
36 XMC_VADC_GROUP_t *base;
37 void (*irq_cfg_func)(void);
38 uint8_t irq_num;
39 };
40
41 static bool adc_global_init;
42 static XMC_VADC_GLOBAL_t *const adc_global_ptr = (XMC_VADC_GLOBAL_t *)0x40004000;
43
adc_context_start_sampling(struct adc_context * ctx)44 static void adc_context_start_sampling(struct adc_context *ctx)
45 {
46 struct adc_xmc4xxx_data *data = CONTAINER_OF(ctx, struct adc_xmc4xxx_data, ctx);
47 const struct device *dev = data->dev;
48 const struct adc_xmc4xxx_cfg *config = dev->config;
49 VADC_G_TypeDef *adc_group = config->base;
50
51 data->repeat_buffer = data->buffer;
52
53 XMC_VADC_GROUP_ScanTriggerConversion(adc_group);
54
55 XMC_VADC_GROUP_ScanEnableArbitrationSlot(adc_group);
56 }
57
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)58 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
59 bool repeat_sampling)
60 {
61 struct adc_xmc4xxx_data *data = CONTAINER_OF(ctx, struct adc_xmc4xxx_data, ctx);
62
63 if (repeat_sampling) {
64 data->buffer = data->repeat_buffer;
65 }
66 }
67
adc_xmc4xxx_isr(const struct device * dev)68 static void adc_xmc4xxx_isr(const struct device *dev)
69 {
70 struct adc_xmc4xxx_data *data = dev->data;
71 const struct adc_xmc4xxx_cfg *config = dev->config;
72 XMC_VADC_GROUP_t *adc_group = config->base;
73 uint32_t channel_mask = data->channel_mask;
74 uint32_t ch;
75
76 /* Conversion has completed. */
77 while (channel_mask > 0) {
78 ch = find_lsb_set(channel_mask) - 1;
79 *data->buffer++ = XMC_VADC_GROUP_GetResult(adc_group, ch);
80 channel_mask &= ~BIT(ch);
81 }
82
83 adc_context_on_sampling_done(&data->ctx, dev);
84 LOG_DBG("%s ISR triggered.", dev->name);
85 }
86
adc_xmc4xxx_validate_buffer_size(const struct adc_sequence * sequence)87 static int adc_xmc4xxx_validate_buffer_size(const struct adc_sequence *sequence)
88 {
89 int active_channels = 0;
90 int total_buffer_size;
91
92 for (int i = 0; i < XMC4XXX_CHANNEL_COUNT; i++) {
93 if (sequence->channels & BIT(i)) {
94 active_channels++;
95 }
96 }
97
98 total_buffer_size = active_channels * sizeof(uint16_t);
99
100 if (sequence->options) {
101 total_buffer_size *= (1 + sequence->options->extra_samplings);
102 }
103
104 if (sequence->buffer_size < total_buffer_size) {
105 return -ENOMEM;
106 }
107
108 return 0;
109 }
110
start_read(const struct device * dev,const struct adc_sequence * sequence)111 static int start_read(const struct device *dev,
112 const struct adc_sequence *sequence)
113 {
114 int ret;
115 struct adc_xmc4xxx_data *data = dev->data;
116 const struct adc_xmc4xxx_cfg *config = dev->config;
117 XMC_VADC_GROUP_t *adc_group = config->base;
118 uint32_t requested_channels = sequence->channels;
119 uint8_t resolution = sequence->resolution;
120 uint32_t configured_channels = adc_group->ASSEL & requested_channels;
121 XMC_VADC_GROUP_CLASS_t group_class = {0};
122
123 if (requested_channels == 0) {
124 LOG_ERR("No channels requested");
125 return -EINVAL;
126 }
127
128 if (requested_channels != configured_channels) {
129 LOG_ERR("Selected channels not configured");
130 return -EINVAL;
131 }
132
133 if (sequence->oversampling) {
134 LOG_ERR("Oversampling not supported");
135 return -ENOTSUP;
136 }
137
138 ret = adc_xmc4xxx_validate_buffer_size(sequence);
139 if (ret < 0) {
140 LOG_ERR("Invalid sequence buffer size");
141 return ret;
142 }
143
144 if (resolution == 8) {
145 group_class.conversion_mode_standard = XMC_VADC_CONVMODE_8BIT;
146 } else if (resolution == 10) {
147 group_class.conversion_mode_standard = XMC_VADC_CONVMODE_10BIT;
148 } else if (resolution == 12) {
149 group_class.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT;
150 } else {
151 LOG_ERR("Invalid resolution");
152 return -EINVAL;
153 }
154 XMC_VADC_GROUP_InputClassInit(adc_group, group_class, XMC_VADC_GROUP_CONV_STD, 0);
155
156 data->channel_mask = requested_channels;
157 data->buffer = sequence->buffer;
158 adc_context_start_read(&data->ctx, sequence);
159
160 return adc_context_wait_for_completion(&data->ctx);
161 }
162
adc_xmc4xxx_read(const struct device * dev,const struct adc_sequence * sequence)163 static int adc_xmc4xxx_read(const struct device *dev,
164 const struct adc_sequence *sequence)
165 {
166 int ret;
167 struct adc_xmc4xxx_data *data = dev->data;
168
169 adc_context_lock(&data->ctx, false, NULL);
170 ret = start_read(dev, sequence);
171 adc_context_release(&data->ctx, ret);
172 return ret;
173 }
174
175 #ifdef CONFIG_ADC_ASYNC
adc_xmc4xxx_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)176 static int adc_xmc4xxx_read_async(const struct device *dev,
177 const struct adc_sequence *sequence,
178 struct k_poll_signal *async)
179 {
180 int ret;
181 struct adc_xmc4xxx_data *data = dev->data;
182
183 adc_context_lock(&data->ctx, true, async);
184 ret = start_read(dev, sequence);
185 adc_context_release(&data->ctx, ret);
186
187 return ret;
188 }
189 #endif
190
adc_xmc4xxx_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)191 static int adc_xmc4xxx_channel_setup(const struct device *dev,
192 const struct adc_channel_cfg *channel_cfg)
193 {
194 const struct adc_xmc4xxx_cfg *config = dev->config;
195 VADC_G_TypeDef *adc_group = config->base;
196 uint32_t ch_num = channel_cfg->channel_id;
197 XMC_VADC_CHANNEL_CONFIG_t channel_config = {0};
198
199 if (ch_num >= XMC4XXX_CHANNEL_COUNT) {
200 LOG_ERR("Channel %d is not valid", ch_num);
201 return -EINVAL;
202 }
203
204 if (channel_cfg->differential) {
205 LOG_ERR("Differential channels are not supported");
206 return -EINVAL;
207 }
208
209 if (channel_cfg->gain != ADC_GAIN_1) {
210 LOG_ERR("Invalid channel gain");
211 return -EINVAL;
212 }
213
214 if (channel_cfg->reference != ADC_REF_INTERNAL) {
215 LOG_ERR("Invalid channel reference");
216 return -EINVAL;
217 }
218
219 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
220 LOG_ERR("Invalid acquisition time");
221 return -EINVAL;
222 }
223
224 /* check that the group global calibration has successfully finished */
225 if (adc_group->ARBCFG & VADC_G_ARBCFG_CAL_Msk) {
226 LOG_WRN("Group calibration hasn't completed yet");
227 return -EBUSY;
228 }
229
230 channel_config.channel_priority = true;
231 channel_config.result_reg_number = ch_num;
232 channel_config.result_alignment = XMC_VADC_RESULT_ALIGN_RIGHT;
233 channel_config.alias_channel = -1; /* do not alias channel */
234 XMC_VADC_GROUP_ChannelInit(adc_group, ch_num, &channel_config);
235
236 adc_group->RCR[ch_num] = 0;
237
238 XMC_VADC_GROUP_ScanAddChannelToSequence(adc_group, ch_num);
239
240 return 0;
241 }
242
243 #define VADC_IRQ_MIN 18
244 #define IRQS_PER_VADC_GROUP 4
245
adc_xmc4xxx_init(const struct device * dev)246 static int adc_xmc4xxx_init(const struct device *dev)
247 {
248 struct adc_xmc4xxx_data *data = dev->data;
249 const struct adc_xmc4xxx_cfg *config = dev->config;
250 VADC_G_TypeDef *adc_group = config->base;
251 uint8_t service_request;
252
253 data->dev = dev;
254 config->irq_cfg_func();
255
256 if (adc_global_init == 0) {
257
258 /* defined using xmc_device.h */
259 #ifdef CLOCK_GATING_SUPPORTED
260 XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_VADC);
261 #endif
262 /* Reset the Hardware */
263 XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_VADC);
264
265 /* enable the module clock */
266 adc_global_ptr->CLC = 0;
267
268 /* global configuration register - defines clock divider to adc clock */
269 /* automatic post calibration after each conversion is enabled */
270 adc_global_ptr->GLOBCFG = 0;
271
272 /* global result control register is unused */
273 adc_global_ptr->GLOBRCR = 0;
274 /* global bound register is unused */
275 adc_global_ptr->GLOBBOUND = 0;
276
277 adc_global_init = 1;
278 }
279
280 adc_group->ARBCFG = 0;
281 adc_group->BOUND = 0;
282
283 XMC_VADC_GROUP_SetPowerMode(adc_group, XMC_VADC_GROUP_POWERMODE_NORMAL);
284
285 /* Initiate calibration. It is initialized for all groups. Check that the */
286 /* calibration completed in the channel setup. */
287 adc_global_ptr->GLOBCFG |= VADC_GLOBCFG_SUCAL_Msk;
288
289 XMC_VADC_GROUP_BackgroundDisableArbitrationSlot(adc_group);
290 XMC_VADC_GROUP_ScanDisableArbitrationSlot(adc_group);
291
292 service_request = (config->irq_num - VADC_IRQ_MIN) % IRQS_PER_VADC_GROUP;
293
294 XMC_VADC_GROUP_ScanSetGatingMode(adc_group, XMC_VADC_GATEMODE_IGNORE);
295 XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode(adc_group, service_request);
296 XMC_VADC_GROUP_ScanEnableEvent(adc_group);
297
298 adc_context_unlock_unconditionally(&data->ctx);
299
300 return 0;
301 }
302
303 static const struct adc_driver_api api_xmc4xxx_driver_api = {
304 .channel_setup = adc_xmc4xxx_channel_setup,
305 .read = adc_xmc4xxx_read,
306 #ifdef CONFIG_ADC_ASYNC
307 .read_async = adc_xmc4xxx_read_async,
308 #endif
309 .ref_internal = DT_INST_PROP(0, vref_internal_mv),
310 };
311
312 #define ADC_XMC4XXX_CONFIG(index) \
313 static void adc_xmc4xxx_cfg_func_##index(void) \
314 { \
315 IRQ_CONNECT(DT_INST_IRQN(index), \
316 DT_INST_IRQ(index, priority), \
317 adc_xmc4xxx_isr, DEVICE_DT_INST_GET(index), 0); \
318 irq_enable(DT_INST_IRQN(index)); \
319 } \
320 \
321 static const struct adc_xmc4xxx_cfg adc_xmc4xxx_cfg_##index = { \
322 .base = (VADC_G_TypeDef *)DT_INST_REG_ADDR(index), \
323 .irq_cfg_func = adc_xmc4xxx_cfg_func_##index, \
324 .irq_num = DT_INST_IRQN(index), \
325 };
326
327 #define ADC_XMC4XXX_INIT(index) \
328 ADC_XMC4XXX_CONFIG(index) \
329 \
330 static struct adc_xmc4xxx_data adc_xmc4xxx_data_##index = { \
331 ADC_CONTEXT_INIT_TIMER(adc_xmc4xxx_data_##index, ctx), \
332 ADC_CONTEXT_INIT_LOCK(adc_xmc4xxx_data_##index, ctx), \
333 ADC_CONTEXT_INIT_SYNC(adc_xmc4xxx_data_##index, ctx), \
334 }; \
335 \
336 DEVICE_DT_INST_DEFINE(index, \
337 &adc_xmc4xxx_init, NULL, \
338 &adc_xmc4xxx_data_##index, &adc_xmc4xxx_cfg_##index, \
339 POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
340 &api_xmc4xxx_driver_api);
341
342 DT_INST_FOREACH_STATUS_OKAY(ADC_XMC4XXX_INIT)
343
