1 /*
2 * Copyright 2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_SDADC_H_
9 #define FSL_SDADC_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup sdadc
15 * @{
16 */
17
18 /******************************************************************************
19 * Definitions
20 ******************************************************************************/
21 /*! @name Driver version */
22 /*!
23 * @{
24 */
25 /*! @brief SDADC driver version 2.0.0. */
26 #define FSL_SDADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
27 /*!
28 * @}
29 */
30
31 /*! @brief Macros are used to configure decimator volume. */
32 #define SDADC_DECIMATOR_VOL_CTRL_P_MASK(offset) (SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0_MASK << offset)
33 #define SDADC_DECIMATOR_VOL_CTRL_P_SHIFT(offset) (SDADC_DECIMATOR_CTL_2_VOL_CTRL_P_0_SHIFT + offset)
34 #define SDADC_DECIMATOR_VOL_CTRL_P(volume, offset) \
35 (((uint32_t)(((uint32_t)(volume)) << SDADC_DECIMATOR_VOL_CTRL_P_SHIFT(offset))) & \
36 SDADC_DECIMATOR_VOL_CTRL_P_MASK(offset))
37 #define SDADC_DECIMATOR_VOL_CTRL_N_MASK(offset) (SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0_MASK << offset)
38 #define SDADC_DECIMATOR_VOL_CTRL_N_SHIFT(offset) (SDADC_DECIMATOR_CTL_2_VOL_CTRL_N_0_SHIFT + offset)
39 #define SDADC_DECIMATOR_VOL_CTRL_N(volume, offset) \
40 (((uint32_t)(((uint32_t)(volume)) << SDADC_DECIMATOR_VOL_CTRL_N_SHIFT(offset))) & \
41 SDADC_DECIMATOR_VOL_CTRL_N_MASK(offset))
42
43 /*! @brief Macros are used to configure decimator sample rate. */
44 #define SDADC_DECIMATOR_SET_SPEED_P_MASK(offset) (SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0_MASK << (offset * 4U))
45 #define SDADC_DECIMATOR_SET_SPEED_P_SHIFT(offset) (SDADC_DECIMATOR_CTL_4_SET_SPEED_P_0_SHIFT + (offset * 4U))
46 #define SDADC_DECIMATOR_SET_SPEED_P(rate, offset) \
47 (((uint32_t)(((uint32_t)(rate)) << SDADC_DECIMATOR_SET_SPEED_P_SHIFT(offset))) & \
48 SDADC_DECIMATOR_SET_SPEED_P_MASK(offset))
49 #define SDADC_DECIMATOR_SET_SPEED_N_MASK(offset) (SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0_MASK << (offset * 4U))
50 #define SDADC_DECIMATOR_SET_SPEED_N_SHIFT(offset) (SDADC_DECIMATOR_CTL_4_SET_SPEED_N_0_SHIFT + (offset * 4U))
51 #define SDADC_DECIMATOR_SET_SPEED_N(rate, offset) \
52 (((uint32_t)(((uint32_t)(rate)) << SDADC_DECIMATOR_SET_SPEED_N_SHIFT(offset))) & \
53 SDADC_DECIMATOR_SET_SPEED_N_MASK(offset))
54
55 /*! @brief Macros are used to configure the dither amplitude. */
56 #define SDADC_ADC_CTL_2_SET_DITHER_MASK(offset) (SDADC_ADC_CTL_2_SET_DITHER3_MASK << ((3U - offset) * 4U))
57 #define SDADC_ADC_CTL_2_SET_DITHER_SHIFT(offset) (SDADC_ADC_CTL_2_SET_DITHER3_SHIFT + ((3U - offset) * 4U))
58 #define SDADC_ADC_CTL_2_SET_DITHER(val, offset) \
59 (((uint32_t)(((uint32_t)(val)) << SDADC_ADC_CTL_2_SET_DITHER_SHIFT(offset))) & \
60 SDADC_ADC_CTL_2_SET_DITHER_MASK(offset))
61
62 /*! @brief Macros are used to configure FIFO watermark. */
63 #define SDADC_FIFO_WATERMARK_CTL_P_MASK(offset) (SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P_MASK << (offset * 8U))
64 #define SDADC_FIFO_WATERMARK_CTL_P_SHIFT(offset) (SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_P_SHIFT + (offset * 8U))
65 #define SDADC_FIFO_WATERMARK_CTL_P(watermark, offset) \
66 (((uint32_t)(((uint32_t)(watermark)) << SDADC_FIFO_WATERMARK_CTL_P_SHIFT(offset))) & \
67 SDADC_FIFO_WATERMARK_CTL_P_MASK(offset))
68 #define SDADC_FIFO_WATERMARK_CTL_N_MASK(offset) (SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N_MASK << (offset * 8U))
69 #define SDADC_FIFO_WATERMARK_CTL_N_SHIFT(offset) (SDADC_FIFO_WATERMARK_CTL_WATERMARK_0_N_SHIFT + (offset * 8U))
70 #define SDADC_FIFO_WATERMARK_CTL_N(watermark, offset) \
71 (((uint32_t)(((uint32_t)(watermark)) << SDADC_FIFO_WATERMARK_CTL_N_SHIFT(offset))) & \
72 SDADC_FIFO_WATERMARK_CTL_N_MASK(offset))
73
74 /*! @brief Macros are used for FIFO operations. */
75 #define SDADC_FIFO_WATERMARK_STATUS_MASK 0xFFU
76 #define SDADC_FIFO_WATERMARK_STATUS_SHIFT SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST_SHIFT
77 #define SDADC_FIFO_FULL_INT_STATUS_MASK 0xFF00U
78 #define SDADC_FIFO_FULL_INT_STATUS_SHIFT SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P_SHIFT
79 #define SDADC_FIFO_MASK SDADC_FIFO_0_P_FIFO_0_P_MASK
80 #define SDADC_FIFO_SHIFT SDADC_FIFO_0_P_FIFO_0_P_SHIFT
81 #define SDADC_FIFO_ENTRIES_AVAIL_MASK SDADC_FIFO_ENTRIES_AVAIL_0_FIFO_0_P_AVAIL_MASK
82 #define SDADC_FIFO_DEPTH (16U)
83 #define SDADC_FIFO_WIDTH (4U)
84
85 /*!
86 * @brief This enumeration provides the mask for the SDADC channel P-Side and N-Side FIFO full interrupt enable/disable.
87 */
88 enum _sdadc_fifo_int_enable
89 {
90 kSDADC_Channel0_PSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_P_EN_MASK,
91 kSDADC_Channel0_NSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_0_N_EN_MASK,
92 kSDADC_Channel1_PSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_P_EN_MASK,
93 kSDADC_Channel1_NSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_1_N_EN_MASK,
94 kSDADC_Channel2_PSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_P_EN_MASK,
95 kSDADC_Channel2_NSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_2_N_EN_MASK,
96 kSDADC_Channel3_PSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_P_EN_MASK,
97 kSDADC_Channel3_NSide_FifoFullIntEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_ERR_3_N_EN_MASK,
98 };
99
100 /*!
101 * @brief This enumeration provides the mask for the SDADC channel P-Side and N-Side FIFO watermark enable/disable.
102 */
103 enum _sdadc_fifo_watermark_enable
104 {
105 kSDADC_Channel0_PSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_P_EN_MASK,
106 kSDADC_Channel0_NSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_0_N_EN_MASK,
107 kSDADC_Channel1_PSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_P_EN_MASK,
108 kSDADC_Channel1_NSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_1_N_EN_MASK,
109 kSDADC_Channel2_PSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_P_EN_MASK,
110 kSDADC_Channel2_NSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_2_N_EN_MASK,
111 kSDADC_Channel3_PSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_P_EN_MASK,
112 kSDADC_Channel3_NSide_FifoWatermarkEnable = SDADC_FIFO_WATERMARK_ERROR_CTL_WM_3_N_EN_MASK,
113 };
114
115 /*!
116 * @brief This enumeration provides the mask for the SDADC channel P-Side and N-Side FIFO full interrupt status flag.
117 */
118 enum _sdadc_fifo_int_status_flag
119 {
120 kSDADC_Channel0_PSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_P_MASK,
121 kSDADC_Channel0_NSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_0_N_MASK,
122 kSDADC_Channel1_PSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_P_MASK,
123 kSDADC_Channel1_NSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_1_N_MASK,
124 kSDADC_Channel2_PSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_P_MASK,
125 kSDADC_Channel2_NSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_2_N_MASK,
126 kSDADC_Channel3_PSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_P_MASK,
127 kSDADC_Channel3_NSide_FifoFullIntStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_ERR_3_N_MASK,
128 };
129
130 /*!
131 * @brief This enumeration provides the mask for the SDADC channel P-Side and N-Side FIFO watermark status flag.
132 */
133 enum _sdadc_fifo_watermark_status_flag
134 {
135 kSDADC_Channel0_PSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_P_ST_MASK,
136 kSDADC_Channel0_NSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_0_N_ST_MASK,
137 kSDADC_Channel1_PSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_P_ST_MASK,
138 kSDADC_Channel1_NSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_1_N_ST_MASK,
139 kSDADC_Channel2_PSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_P_ST_MASK,
140 kSDADC_Channel2_NSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_2_N_ST_MASK,
141 kSDADC_Channel3_PSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_P_ST_MASK,
142 kSDADC_Channel3_NSide_FifoWatermarkStatusFlag = SDADC_FIFO_WATERMARK_ERROR_ST_WM_3_N_ST_MASK,
143 };
144
145 /*!
146 * @brief This enumeration provides the selection of the SDADC channel mode.
147 */
148 typedef enum _sdadc_channel_mode
149 {
150 kSDADC_SingleEnd_Mode = 0U, /*!< Single-end mode. */
151 kSDADC_Differential_Mode = 1U, /*!< Differential mode. */
152 } sdadc_channel_mode_t;
153
154 /*!
155 * @brief This enumeration provides the selection of the SDADC channel number.
156 */
157 typedef enum _sdadc_channel_number
158 {
159 kSDADC_Channel0 = 0U, /*!< SDADC channel 0. */
160 kSDADC_Channel1 = 1U, /*!< SDADC channel 1. */
161 kSDADC_Channel2 = 2U, /*!< SDADC channel 2. */
162 kSDADC_Channel3 = 3U, /*!< SDADC channel 3. */
163 } sdadc_channel_number_t;
164
165 /*!
166 * @brief This enumeration provides the selection of the SDADC channel type.
167 */
168 typedef enum _sdadc_channel_type
169 {
170 kSDADC_Channel_NSide_Type = 0x01U, /*!< N-side selected. */
171 kSDADC_Channel_PSide_Type = 0x10U, /*!< P-side selected. */
172 kSDADC_Channel_NandPSide_Type = 0x11U, /*!< N- and P-side selected. */
173 } sdadc_channel_type_t;
174
175 /*!
176 * @brief This enumeration provides the selection of the SDADC decimator sample rate.
177 */
178 typedef enum _sdadc_decimator_sample_rate
179 {
180 kSDADC_DecimatorSampleRate48kHz = 0x0U, /*!< 48kHz decimator sample rate. */
181 kSDADC_DecimatorSampleRate32kHz = 0x1U, /*!< 32kHz decimator sample rate. */
182 kSDADC_DecimatorSampleRate16kHz = 0x2U, /*!< 16kHz decimator sample rate. */
183 } sdadc_decimator_sample_rate_t;
184
185 /*!
186 * @brief This enumeration provides the selection of the SDADC LDO drive capability.
187 */
188 typedef enum _sdadc_ldo_drive_capability
189 {
190 kSDADC_LdoLowPower = 0x0U, /*!< To drive 1 single-end mode or 1 differential mode SDADC. */
191 kSDADC_LdoHighPower = 0x1U, /*!< To drive more than 1 SDADC */
192 } sdadc_ldo_drive_capability_t;
193
194 /*!
195 * @brief This enumeration provides the selection of the SDADC reference mode.
196 *
197 * @details The SDADC reference module has four modes, these modes are controlled via REF_CTL register
198 * 'fast_ref_enable' and 'pwr_fast_ref_enable' bitfields.
199 * 1.Retain mode: pwr_fast_ref_enable = 0b, fast_ref_enable = 0b.
200 * 2.Low noise mode: pwr_fast_ref_enable = 0b, fast_ref_enable = 1b.
201 * 3.Low power mode: pwr_fast_ref_enable = 1b, fast_ref_enable = 0b.
202 * 4.Fast charge mode: pwr_fast_ref_enable = 1b, fast_ref_enable = 1b.
203 */
204 typedef enum _sdadc_ref_mode
205 {
206 kSDADC_RefRetainMode = 0x0U, /*!< Reference in retain mode. */
207 kSDADC_RefLowNoiseMode = 0x1U, /*!< Reference in low noise mode. */
208 kSDADC_RefLowPowerMode = 0x2U, /*!< Reference in low power mode. */
209 kSDADC_RefFastChargeMode = 0x3U, /*!< Reference in fast charge mode. */
210 } sdadc_ref_mode_t;
211
212 /*!
213 * @brief This enumeration provides the selection of the SDADC FIFO write or/and read operation.
214 */
215 typedef enum _sdadc_fifo_reset_operation
216 {
217 kSDADC_FifoWriteReset = 0x1U, /*!< FIFO write reset. */
218 kSDADC_FifoReadReset = 0x2U, /*!< FIFO read reset. */
219 kSDADC_FifoWriteAndReadReset = 0x3U, /*!< FIFO write and read reset. */
220 } sdadc_fifo_reset_operation_t;
221
222 /*!
223 * @brief This structure is used to configure the decimator volume (gain).
224 *
225 * @note The gain setting is not applicable for the channel N-Side when executing the differential mode. For the
226 * specific gain setting value please refer to the reference manual.
227 */
228 typedef struct _sdadc_volume
229 {
230 uint8_t pSideVolume; /*!< Sets the gain for the P-Side decimator. */
231 uint8_t nSideVolume; /*!< Sets the gain for the N-Side decimator. */
232 } sdadc_volume_control_t;
233
234 /*!
235 * @brief This structure is used to configure the decimator sample rate.
236 */
237 typedef struct _sdadc_sample_rate
238 {
239 sdadc_decimator_sample_rate_t pSideSampleRate; /*!< Sets the P-Side decimator sample rate. */
240 sdadc_decimator_sample_rate_t nSideSampleRate; /*!< Sets the N-Side decimator sample rate. */
241 } sdadc_sample_rate_t;
242
243 /*!
244 * @brief This structure is used to configure the FIFO watermark.
245 *
246 * @note In the differential mode, the bitstream is converted to 24bit data (FIFO_x_P[23:0]) by P-Side decimator,
247 * the output of N-Side decimator (FIFO_x_N[23:0]) is not valid.
248 */
249 typedef struct _sdadc_watermark
250 {
251 uint8_t pSideWatermark; /*!< Sets the channel N-Side FIFO watermark. */
252 uint8_t nSideWatermark; /*!< Sets the channel P-Side FIFO watermark. */
253 } sdadc_watermark_t;
254
255 /*!
256 * @brief This structure is used to configure the SDADC channels.
257 */
258 typedef struct _sdadc_channel_config
259 {
260 sdadc_channel_mode_t mode; /*!< Sets channel mode. */
261 sdadc_channel_number_t number; /*!< Sets channel number. */
262 sdadc_channel_type_t type; /*!< Sets channel type. */
263
264 sdadc_volume_control_t volume; /*!< Sets N- and P-side decimator volume. */
265 sdadc_sample_rate_t samplerate; /*!< Sets N- and P-side decimator samplerate. */
266 sdadc_watermark_t watermark; /*!< Sets N- and P-side FIFO watermark. */
267
268 bool enableDacCompensation; /*!< Decides whether to enable the compensation feature for the ADCp[3:0] or/and
269 ADCn[3:0] in the single-end mode, is used to avoid large data-dependent ripple
270 on LDO output which will impact the ADC performance. */
271 bool enableDCLoop; /*!< In some cases of the single-end mode, the microphone output is connected
272 directly to ADC input without the coupling capacitor, DC Loop is activated to
273 regulate input common-mode voltage of the ADCp[3:0] or/and ADCn[3:0]. In the
274 single-end mode, there is the possibility to connect MEMS or JFET microphone
275 directly to the input (DC-coupled). In this configuration, DC Loop mode needs
276 to be activated to establish the correct common mode input voltage level at
277 the input pin. The DC Loop function should disabled in the differential mode. */
278 bool enableDcFilter; /*!< Decides whether to enable the decimator DC Filter to remove DC components.*/
279 bool enablePolarityInvert; /*!< Decides whether to enable the polarity invert function, for example: if the input to
280 ADC is a pure sinus signal, then if the polarity invert is enabled, the decimation output
281 will be a sinus signal 180 out of phase with the input. */
282 } sdadc_channel_config_t;
283
284 /*!
285 * @brief This structure is used to configure the SDADC module.
286 */
287 typedef struct _sdadc_config
288 {
289 uint8_t channelCount; /*!< Indicates how many channels to execute the conversion. */
290 sdadc_channel_config_t *channelConfig; /*!< SDADC channels configuration. */
291 } sdadc_config_t;
292
293 /*!
294 * @brief This structure is used to construct channel groups.
295 */
296 typedef struct _sdadc_channel_group
297 {
298 sdadc_channel_number_t number; /*!< Channel number. */
299 sdadc_channel_type_t type; /*!< Channel type. */
300 } sdadc_channel_group;
301
302 /******************************************************************************
303 * API
304 ******************************************************************************/
305 #if defined(__cplusplus)
306 extern "C" {
307 #endif
308
309 /*!
310 * @name SDADC initialization and de-initialization.
311 * @{
312 */
313 /*!
314 * @brief This function is used to get available predefined configurations for the SDADC initialization.
315 *
316 * @param config Pointer to the SDADC configuration structure, please refer to @ref sdadc_config_t for details.
317 */
318 void SDADC_GetDefaultConfig(sdadc_config_t *config);
319
320 /*!
321 * @brief This function is used to initialize the SDADC.
322 *
323 * @param base SDADC peripheral base address.
324 * @param config Pointer to the SDADC configuration structure, please refer to @ref sdadc_config_t for details.
325 */
326 void SDADC_Init(SDADC_Type *base, const sdadc_config_t *config);
327
328 /*!
329 * @brief This function is used to de-initialize the SDADC.
330 *
331 * @param base SDADC peripheral base address.
332 * @param config Pointer to the SDADC configuration structure, please refer to @ref sdadc_config_t for details.
333 */
334 void SDADC_Deinit(SDADC_Type *base, const sdadc_config_t *config);
335 /*!
336 * @}
337 */
338
339 /*!
340 * @name SDADC channel modulator, reference, and LDO configuration.
341 * @{
342 */
343 /*!
344 * @brief This function is used to power up the SDADC in the initialization state.
345 *
346 * @param base SDADC peripheral base address.
347 * @param config Pointer to the SDADC configuration structure, please refer to @ref sdadc_config_t for details.
348 * @param clock Core clock frequency with Hz.
349 */
350 void SDADC_DoInitPowerUp(SDADC_Type *base, sdadc_config_t *config, uint32_t clock);
351
352 /*!
353 * @brief This function is used to enable or disable SDADC specific channel's P-Side or/and N-Side sigma-delta
354 * modulator power.
355 *
356 * @param base SDADC peripheral base address.
357 * @param number channel number, refer @ref sdadc_channel_number_t for details.
358 * @param type channel type, refer @ref sdadc_channel_type_t for details.
359 * @param enable Decides whether to enable or disable.
360 * - @b true Enable
361 * - @b false Disable
362 */
SDADC_ControlModulatorPowerEnable(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool enable)363 static inline void SDADC_ControlModulatorPowerEnable(SDADC_Type *base,
364 sdadc_channel_number_t number,
365 sdadc_channel_type_t type,
366 bool enable)
367 {
368 if (enable)
369 {
370 if (type == kSDADC_Channel_PSide_Type)
371 {
372 base->ADC_CTL_0 |= (0x1U << (number + SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_SHIFT));
373 }
374 else if (type == kSDADC_Channel_NSide_Type)
375 {
376 base->ADC_CTL_0 |= (0x1U << (number + SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_SHIFT));
377 }
378 else
379 {
380 base->ADC_CTL_0 |= ((0x1U << (number + SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_SHIFT)) |
381 (0x1U << (number + SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_SHIFT)));
382 }
383 }
384 else
385 {
386 if (type == kSDADC_Channel_PSide_Type)
387 {
388 base->ADC_CTL_0 &= ~(0x1U << (number + SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_SHIFT));
389 }
390 else if (type == kSDADC_Channel_NSide_Type)
391 {
392 base->ADC_CTL_0 &= ~(0x1U << (number + SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_SHIFT));
393 }
394 else
395 {
396 base->ADC_CTL_0 &= ~((0x1U << (number + SDADC_ADC_CTL_0_ADCP_POWER_ENABLE_SHIFT)) |
397 (0x1U << (number + SDADC_ADC_CTL_0_ADCN_POWER_ENABLE_SHIFT)));
398 }
399 }
400 }
401
402 /*!
403 * @brief This function is used to enable or disable the reference power.
404 *
405 * @param base SDADC peripheral base address.
406 * @param enable Indicates enable or disable the reference power.
407 * - @b true Enable
408 * - @b false Disable
409 */
SDADC_ControlReferencePowerEnable(SDADC_Type * base,bool enable)410 static inline void SDADC_ControlReferencePowerEnable(SDADC_Type *base, bool enable)
411 {
412 if (enable)
413 {
414 base->REF_CTL |= SDADC_REF_CTL_REF_POWER_ENABLE_MASK;
415 }
416 else
417 {
418 base->REF_CTL &= ~SDADC_REF_CTL_REF_POWER_ENABLE_MASK;
419 }
420 }
421
422 /*!
423 * @brief This function is used to configure the reference mode.
424 *
425 * @note Setting the reference to fast charge mode is mainly used during startup where fast startup
426 * is required, the current consumption in this mode is the largest, so, it is recommended to switch
427 * to other modes to minimize current consumption. If the ADC works on the single-end mode, recommend
428 * switching to the low-noise mode, if the ADC works on the differential mode, recommend switching to
429 * the retain mode.
430 *
431 * @param base SDADC peripheral base address.
432 * @param referenceMode Reference mode to be configured, see @ref sdadc_ref_mode_t for details.
433 */
SDADC_ConfigureReferenceMode(SDADC_Type * base,sdadc_ref_mode_t referenceMode)434 static inline void SDADC_ConfigureReferenceMode(SDADC_Type *base, sdadc_ref_mode_t referenceMode)
435 {
436 base->REF_CTL =
437 ((base->REF_CTL & (~(SDADC_REF_CTL_FAST_REF_ENABLE_MASK | SDADC_REF_CTL_PWR_FAST_REF_ENABLE_MASK))) |
438 ((((referenceMode & 0x2U) != 0UL) ? SDADC_REF_CTL_PWR_FAST_REF_ENABLE_MASK : 0U) |
439 (((referenceMode & 0x1U) != 0UL) ? SDADC_REF_CTL_FAST_REF_ENABLE_MASK : 0U)));
440 }
441
442 /*!
443 * @brief This function is used to enable or disable the LDO power.
444 *
445 * @param base SDADC peripheral base address.
446 * @param enable Indicates enable or disable the LDO power.
447 * - @b true Enable
448 * - @b false Disable
449 */
SDADC_ControlLdoPowerEnable(SDADC_Type * base,bool enable)450 static inline void SDADC_ControlLdoPowerEnable(SDADC_Type *base, bool enable)
451 {
452 if (enable)
453 {
454 base->LDO_CTL |= SDADC_LDO_CTL_LDO_POWER_ENABLE_MASK;
455 }
456 else
457 {
458 base->LDO_CTL &= ~SDADC_LDO_CTL_LDO_POWER_ENABLE_MASK;
459 }
460 }
461
462 /*!
463 * @brief This function is used to configure the drive capability.
464 *
465 * @param base SDADC peripheral base address.
466 * @param capability SDADC LDO drive capability to be set, see @ref sdadc_ldo_drive_capability_t for details.
467 */
SDADC_ConfigureLdoDriveCapability(SDADC_Type * base,sdadc_ldo_drive_capability_t capability)468 static inline void SDADC_ConfigureLdoDriveCapability(SDADC_Type *base, sdadc_ldo_drive_capability_t capability)
469 {
470 base->LDO_CTL = ((base->LDO_CTL & (~SDADC_LDO_CTL_LDO_SETTING_MASK)) | (SDADC_LDO_CTL_LDO_SETTING(capability)));
471 }
472 /*!
473 * @}
474 */
475
476 /*!
477 * @name SDADC channel mode, DAC compensation, modulator DC Loop, decimator DC Filter configuration.
478 * @{
479 */
480 /*!
481 * @brief This function is used to configure the channel mode.
482 *
483 * @param base SDADC peripheral base address.
484 * @param number channel number, refer @ref sdadc_channel_number_t for details.
485 * @param mode channel mode, refer @ref sdadc_channel_mode_t for details.
486 */
SDADC_ConfigureChannelMode(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_mode_t mode)487 static inline void SDADC_ConfigureChannelMode(SDADC_Type *base,
488 sdadc_channel_number_t number,
489 sdadc_channel_mode_t mode)
490 {
491 if (kSDADC_SingleEnd_Mode == mode)
492 {
493 base->ADC_CTL_1 &= ~(0x01U << (SDADC_ADC_CTL_1_DIFF_ENABLE_SHIFT + number));
494 }
495 else
496 {
497 base->ADC_CTL_1 |= (0x01U << (SDADC_ADC_CTL_1_DIFF_ENABLE_SHIFT + number));
498 }
499 }
500
501 /*!
502 * @brief This function is used to enable or disable the DAC compensation function.
503 *
504 * @param base SDADC peripheral base address.
505 * @param number channel number, refer @ref sdadc_channel_number_t for details.
506 * @param type channel type, refer @ref sdadc_channel_type_t for details.
507 * @param enable Decides whether to enable or disable.
508 * - @b true Enable
509 * - @b false Disable
510 */
SDADC_ControlDacCompensationEnable(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool enable)511 static inline void SDADC_ControlDacCompensationEnable(SDADC_Type *base,
512 sdadc_channel_number_t number,
513 sdadc_channel_type_t type,
514 bool enable)
515 {
516 if (enable)
517 {
518 if (type == kSDADC_Channel_PSide_Type)
519 {
520 base->ADC_CTL_0 |= (0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_SHIFT));
521 }
522 else if (type == kSDADC_Channel_NSide_Type)
523 {
524 base->ADC_CTL_0 |= (0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_SHIFT));
525 }
526 else
527 {
528 base->ADC_CTL_0 |= ((0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_SHIFT)) |
529 (0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_SHIFT)));
530 }
531 }
532 else
533 {
534 if (type == kSDADC_Channel_PSide_Type)
535 {
536 base->ADC_CTL_0 &= ~(0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_SHIFT));
537 }
538 else if (type == kSDADC_Channel_NSide_Type)
539 {
540 base->ADC_CTL_0 &= ~(0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_SHIFT));
541 }
542 else
543 {
544 base->ADC_CTL_0 &= ~((0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCP_ENABLE_SHIFT)) |
545 (0x1U << (number + SDADC_ADC_CTL_0_COMP_ADCN_ENABLE_SHIFT)));
546 }
547 }
548 }
549
550 /*!
551 * @brief This function is used to enable or disable the modulator DC Loop function.
552 *
553 * @param base SDADC peripheral base address.
554 * @param number channel number, refer @ref sdadc_channel_number_t for details.
555 * @param type channel type, refer @ref sdadc_channel_type_t for details.
556 * @param enable Decides whether to enable or disable.
557 * - @b true Enable
558 * - @b false Disable
559 */
SDADC_ControlModulatorDcLoopEnable(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool enable)560 static inline void SDADC_ControlModulatorDcLoopEnable(SDADC_Type *base,
561 sdadc_channel_number_t number,
562 sdadc_channel_type_t type,
563 bool enable)
564 {
565 if (enable)
566 {
567 if (type == kSDADC_Channel_PSide_Type)
568 {
569 base->ADC_CTL_1 |= (0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_SHIFT));
570 base->DC_LOOP_CTL_0 |= (0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_SHIFT));
571 }
572 else if (type == kSDADC_Channel_NSide_Type)
573 {
574 base->ADC_CTL_1 |= (0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_SHIFT));
575 base->DC_LOOP_CTL_0 |= (0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_SHIFT));
576 }
577 else
578 {
579 base->ADC_CTL_1 |= ((0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_SHIFT)) |
580 (0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_SHIFT)));
581 base->DC_LOOP_CTL_0 |= ((0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_SHIFT)) |
582 (0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_SHIFT)));
583 }
584 }
585 else
586 {
587 if (type == kSDADC_Channel_PSide_Type)
588 {
589 base->ADC_CTL_1 &= ~(0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_SHIFT));
590 base->DC_LOOP_CTL_0 &= ~(0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_SHIFT));
591 }
592 else if (type == kSDADC_Channel_NSide_Type)
593 {
594 base->ADC_CTL_1 &= ~(0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_SHIFT));
595 base->DC_LOOP_CTL_0 &= ~(0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_SHIFT));
596 }
597 else
598 {
599 base->ADC_CTL_1 &= ~((0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_P_ANA_ENABLE_SHIFT)) |
600 (0x1U << (number + SDADC_ADC_CTL_1_DCLOOP_N_ANA_ENABLE_SHIFT)));
601 base->DC_LOOP_CTL_0 &= ~((0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_P_ENABLE_SHIFT)) |
602 (0x1U << (number + SDADC_DC_LOOP_CTL_0_DCLOOP_N_ENABLE_SHIFT)));
603 }
604 }
605 }
606
607 /*!
608 * @brief This function is used to enable or disable the decimator DC Filter function.
609 *
610 * @param base SDADC peripheral base address.
611 * @param number channel number, refer @ref sdadc_channel_number_t for details.
612 * @param type channel type, refer @ref sdadc_channel_type_t for details.
613 * @param enable Decides whether to enable or disable.
614 * - @b true Enable
615 * - @b false Disable
616 */
SDADC_ControlDecimatorDcFilterEnable(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool enable)617 static inline void SDADC_ControlDecimatorDcFilterEnable(SDADC_Type *base,
618 sdadc_channel_number_t number,
619 sdadc_channel_type_t type,
620 bool enable)
621 {
622 if (enable)
623 {
624 if (type == kSDADC_Channel_PSide_Type)
625 {
626 base->DECIMATOR_CTL_0 |= (0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_SHIFT));
627 }
628 else if (type == kSDADC_Channel_NSide_Type)
629 {
630 base->DECIMATOR_CTL_0 |= (0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_SHIFT));
631 }
632 else
633 {
634 base->DECIMATOR_CTL_0 |= ((0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_SHIFT)) |
635 (0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_SHIFT)));
636 }
637 }
638 else
639 {
640 if (type == kSDADC_Channel_PSide_Type)
641 {
642 base->DECIMATOR_CTL_0 &= ~(0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_SHIFT));
643 }
644 else if (type == kSDADC_Channel_NSide_Type)
645 {
646 base->DECIMATOR_CTL_0 &= ~(0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_SHIFT));
647 }
648 else
649 {
650 base->DECIMATOR_CTL_0 &= ~((0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_P_ENABLE_SHIFT)) |
651 (0x1U << (number + SDADC_DECIMATOR_CTL_0_DCFILTI_N_ENABLE_SHIFT)));
652 }
653 }
654 }
655
656 /*!
657 * @brief This function is used to enable or disable the decimator output invert.
658 *
659 * @param base SDADC peripheral base address.
660 * @param number channel number, refer @ref sdadc_channel_number_t for details.
661 * @param type channel type, refer @ref sdadc_channel_type_t for details.
662 * @param enable Decides whether to enable or disable.
663 * - @b true Enable
664 * - @b false Disable
665 */
SDADC_ControlDecimatorOutputInvertEnable(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool enable)666 static inline void SDADC_ControlDecimatorOutputInvertEnable(SDADC_Type *base,
667 sdadc_channel_number_t number,
668 sdadc_channel_type_t type,
669 bool enable)
670 {
671 if (enable)
672 {
673 if (type == kSDADC_Channel_PSide_Type)
674 {
675 base->DECIMATOR_CTL_0 |= (0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_SHIFT));
676 }
677 else if (type == kSDADC_Channel_NSide_Type)
678 {
679 base->DECIMATOR_CTL_0 |= (0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_SHIFT));
680 }
681 else
682 {
683 base->DECIMATOR_CTL_0 |= ((0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_SHIFT)) |
684 (0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_SHIFT)));
685 }
686 }
687 else
688 {
689 if (type == kSDADC_Channel_PSide_Type)
690 {
691 base->DECIMATOR_CTL_0 &= ~(0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_SHIFT));
692 }
693 else if (type == kSDADC_Channel_NSide_Type)
694 {
695 base->DECIMATOR_CTL_0 &= ~(0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_SHIFT));
696 }
697 else
698 {
699 base->DECIMATOR_CTL_0 &= ~((0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_P_ENABLE_SHIFT)) |
700 (0x1U << (number + SDADC_DECIMATOR_CTL_0_POL_INV_N_ENABLE_SHIFT)));
701 }
702 }
703 }
704
705 /*!
706 * @brief This function is used to configure the decimator volume.
707 *
708 * @param base SDADC peripheral base address.
709 * @param number channel number, refer @ref sdadc_channel_number_t for details.
710 * @param type channel type, refer @ref sdadc_channel_type_t for details.
711 * @param volume Volume level, see @ref sdadc_volume_control_t for details.
712 */
SDADC_ConfigureDecimatorVolume(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,sdadc_volume_control_t volume)713 static inline void SDADC_ConfigureDecimatorVolume(SDADC_Type *base,
714 sdadc_channel_number_t number,
715 sdadc_channel_type_t type,
716 sdadc_volume_control_t volume)
717 {
718 uint8_t registerOffset = number / 2U;
719 uint8_t bitfieldOffset = number % 2U * 16U;
720
721 if (type == kSDADC_Channel_PSide_Type)
722 {
723 (*((&(base->DECIMATOR_CTL_2)) + registerOffset)) =
724 (((*((&(base->DECIMATOR_CTL_2)) + registerOffset)) & (~(SDADC_DECIMATOR_VOL_CTRL_P_MASK(bitfieldOffset)))) |
725 SDADC_DECIMATOR_VOL_CTRL_P(volume.pSideVolume, bitfieldOffset));
726 }
727 else if (type == kSDADC_Channel_NSide_Type)
728 {
729 (*((&(base->DECIMATOR_CTL_2)) + registerOffset)) =
730 (((*((&(base->DECIMATOR_CTL_2)) + registerOffset)) & (~(SDADC_DECIMATOR_VOL_CTRL_N_MASK(bitfieldOffset)))) |
731 SDADC_DECIMATOR_VOL_CTRL_N(volume.nSideVolume, bitfieldOffset));
732 }
733 else
734 {
735 (*((&(base->DECIMATOR_CTL_2)) + registerOffset)) =
736 (((*((&(base->DECIMATOR_CTL_2)) + registerOffset)) &
737 (~(SDADC_DECIMATOR_VOL_CTRL_P_MASK(bitfieldOffset) | SDADC_DECIMATOR_VOL_CTRL_N_MASK(bitfieldOffset)))) |
738 (SDADC_DECIMATOR_VOL_CTRL_P(volume.pSideVolume, bitfieldOffset) |
739 SDADC_DECIMATOR_VOL_CTRL_N(volume.nSideVolume, bitfieldOffset)));
740 }
741 }
742
743 /*!
744 * @brief This function is used to configure the decimator sample rate.
745 *
746 * @param base SDADC peripheral base address.
747 * @param number channel number, refer @ref sdadc_channel_number_t for details.
748 * @param type channel type, refer @ref sdadc_channel_type_t for details.
749 * @param sampleRate Sample rate, see @ref sdadc_sample_rate_t for details.
750 */
SDADC_ConfigureDecimatorSampleRate(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,sdadc_sample_rate_t sampleRate)751 static inline void SDADC_ConfigureDecimatorSampleRate(SDADC_Type *base,
752 sdadc_channel_number_t number,
753 sdadc_channel_type_t type,
754 sdadc_sample_rate_t sampleRate)
755 {
756 if (type == kSDADC_Channel_PSide_Type)
757 {
758 base->DECIMATOR_CTL_4 = ((base->DECIMATOR_CTL_4 & (~SDADC_DECIMATOR_SET_SPEED_P_MASK(number))) |
759 SDADC_DECIMATOR_SET_SPEED_P(sampleRate.pSideSampleRate, number));
760 }
761 else if (type == kSDADC_Channel_NSide_Type)
762 {
763 base->DECIMATOR_CTL_4 = ((base->DECIMATOR_CTL_4 & (~SDADC_DECIMATOR_SET_SPEED_N_MASK(number))) |
764 SDADC_DECIMATOR_SET_SPEED_N(sampleRate.nSideSampleRate, number));
765 }
766 else
767 {
768 base->DECIMATOR_CTL_4 =
769 ((base->DECIMATOR_CTL_4 &
770 (~(SDADC_DECIMATOR_SET_SPEED_P_MASK(number) | SDADC_DECIMATOR_SET_SPEED_N_MASK(number)))) |
771 (SDADC_DECIMATOR_SET_SPEED_P(sampleRate.pSideSampleRate, number) |
772 SDADC_DECIMATOR_SET_SPEED_N(sampleRate.nSideSampleRate, number)));
773 }
774 }
775
776 /*!
777 * @brief This function is used to set the dither amplitude.
778 *
779 * @details In the ADC conversion process, adding dither can improve the ADC dynamic performance, but too large a dither
780 * will cause the input signal to overflow, the user needs to set the appropriate dither amplitude according to their
781 * own needs.
782 *
783 * @param base SDADC peripheral base address.
784 * @param number channel number, refer @ref sdadc_channel_number_t for details.
785 * @param ditherAmplitude The dither amplitude that will be introduced, the range is from 000b to 111b, 000b means
786 * disable the dither.
787 */
SDADC_ConfigureDitherAmplitude(SDADC_Type * base,sdadc_channel_number_t number,uint8_t ditherAmplitude)788 static inline void SDADC_ConfigureDitherAmplitude(SDADC_Type *base,
789 sdadc_channel_number_t number,
790 uint8_t ditherAmplitude)
791 {
792 base->ADC_CTL_2 = ((base->ADC_CTL_2 & (~SDADC_ADC_CTL_2_SET_DITHER_MASK(number))) |
793 (SDADC_ADC_CTL_2_SET_DITHER(ditherAmplitude, number)));
794 }
795 /*!
796 * @}
797 */
798
799 /*!
800 * @name SDADC modulator, decimator, and modulator DC Loop reset and release reset.
801 * @{
802 */
803 /*!
804 * @brief This function is used to reset or release reset for the SDADC specific channel's P-Side or N-Side sigma-delta
805 * modulator.
806 *
807 * @note Needs to be reset for at least 15us after start-up, and then release the reset.
808 *
809 * @param base SDADC peripheral base address.
810 * @param number channel number, refer @ref sdadc_channel_number_t for details.
811 * @param type channel type, refer @ref sdadc_channel_type_t for details.
812 * @param reset Indicates reset or release reset for the sigma-delta modulator.
813 * - @b true Reset
814 * - @b false Release reset
815 */
SDADC_ControlModulatorReset(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool reset)816 static inline void SDADC_ControlModulatorReset(SDADC_Type *base,
817 sdadc_channel_number_t number,
818 sdadc_channel_type_t type,
819 bool reset)
820 {
821 if (reset)
822 {
823 if (type == kSDADC_Channel_PSide_Type)
824 {
825 base->ADC_CTL_0 &= ~(0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCP_SHIFT));
826 }
827 else if (type == kSDADC_Channel_NSide_Type)
828 {
829 base->ADC_CTL_0 &= ~(0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCN_SHIFT));
830 }
831 else
832 {
833 base->ADC_CTL_0 &= ~((0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCP_SHIFT)) |
834 (0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCN_SHIFT)));
835 }
836 }
837 else
838 {
839 if (type == kSDADC_Channel_PSide_Type)
840 {
841 base->ADC_CTL_0 |= (0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCP_SHIFT));
842 }
843 else if (type == kSDADC_Channel_NSide_Type)
844 {
845 base->ADC_CTL_0 |= (0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCN_SHIFT));
846 }
847 else
848 {
849 base->ADC_CTL_0 |= ((0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCP_SHIFT)) |
850 (0x1U << (number + SDADC_ADC_CTL_0_RST_AN_ADCN_SHIFT)));
851 }
852 }
853 }
854
855 /*!
856 * @brief This function is used to reset or release reset for the SDADC channeln's P-Side or/and N-Side decimator.
857 *
858 * @param base SDADC peripheral base address.
859 * @param number channel number, refer @ref sdadc_channel_number_t for details.
860 * @param type channel type, refer @ref sdadc_channel_type_t for details.
861 * @param reset Indicates reset or release reset for the decimator.
862 * - @b true Reset
863 * - @b false Release reset
864 */
SDADC_ControlDecimatorReset(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool reset)865 static inline void SDADC_ControlDecimatorReset(SDADC_Type *base,
866 sdadc_channel_number_t number,
867 sdadc_channel_type_t type,
868 bool reset)
869 {
870 if (reset)
871 {
872 if (type == kSDADC_Channel_PSide_Type)
873 {
874 base->DECIMATOR_CTL_1 &= ~(0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_SHIFT));
875 }
876 else if (type == kSDADC_Channel_NSide_Type)
877 {
878 base->DECIMATOR_CTL_1 &= ~(0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_SHIFT));
879 }
880 else
881 {
882 base->DECIMATOR_CTL_1 &= ~((0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_SHIFT)) |
883 (0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_SHIFT)));
884 }
885 }
886 else
887 {
888 if (type == kSDADC_Channel_PSide_Type)
889 {
890 base->DECIMATOR_CTL_1 |= (0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_SHIFT));
891 }
892 else if (type == kSDADC_Channel_NSide_Type)
893 {
894 base->DECIMATOR_CTL_1 |= (0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_SHIFT));
895 }
896 else
897 {
898 base->DECIMATOR_CTL_1 |= ((0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_P_SHIFT)) |
899 (0x1U << (number + SDADC_DECIMATOR_CTL_1_FUNC_LOCAL_RST_AN_DEC_N_SHIFT)));
900 }
901 }
902 }
903
904 /*!
905 * @brief This function is used to reset or release reset for the SDADC channeln's P-Side or/and N-Side madulator DC
906 * Loop.
907 *
908 * @param base SDADC peripheral base address.
909 * @param number channel number, refer @ref sdadc_channel_number_t for details.
910 * @param type channel type, refer @ref sdadc_channel_type_t for details.
911 * @param reset Indicates whether reset or release reset for the madulator DC Loop.
912 * - @b true Reset
913 * - @b false Release reset
914 */
SDADC_ConfigureModulatorDcLoopReset(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,bool reset)915 static inline void SDADC_ConfigureModulatorDcLoopReset(SDADC_Type *base,
916 sdadc_channel_number_t number,
917 sdadc_channel_type_t type,
918 bool reset)
919 {
920 if (reset)
921 {
922 if (type == kSDADC_Channel_PSide_Type)
923 {
924 base->DC_LOOP_CTL_1 &= ~(0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_SHIFT));
925 }
926 else if (type == kSDADC_Channel_NSide_Type)
927 {
928 base->DC_LOOP_CTL_1 &= ~(0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_SHIFT));
929 }
930 else
931 {
932 base->DC_LOOP_CTL_1 &= ~((0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_SHIFT)) |
933 (0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_SHIFT)));
934 }
935 }
936 else
937 {
938 if (type == kSDADC_Channel_PSide_Type)
939 {
940 base->DC_LOOP_CTL_1 |= (0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_SHIFT));
941 }
942 else if (type == kSDADC_Channel_NSide_Type)
943 {
944 base->DC_LOOP_CTL_1 |= (0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_SHIFT));
945 }
946 else
947 {
948 base->DC_LOOP_CTL_1 |= ((0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_P_SHIFT)) |
949 (0x1U << (number + SDADC_DC_LOOP_CTL_1_FUNC_LOCAL_RST_AN_DCLOOP_N_SHIFT)));
950 }
951 }
952 }
953 /*!
954 * @}
955 */
956
957 /*!
958 * @name SDADC FIFO related operations.
959 * @{
960 */
961 /*!
962 * @brief This function is used to enable or disable the global FIFO full interrupt.
963 *
964 * @param base SDADC peripheral base address.
965 * @param enable Indicates whether enable or disable the global FIFO full interrupt.
966 * - @b true Enable interrupt
967 * - @b false Disable interrupt
968 */
SDADC_ControlGlobalFifoIntEnable(SDADC_Type * base,bool enable)969 static inline void SDADC_ControlGlobalFifoIntEnable(SDADC_Type *base, bool enable)
970 {
971 if (enable)
972 {
973 base->FIFO_INTERRUPT |= SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN_MASK;
974 }
975 else
976 {
977 base->FIFO_INTERRUPT &= ~SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_EN_MASK;
978 }
979 }
980
981 /*!
982 * @brief This function is used to check whether the FIFO full interrupt has occurred.
983 *
984 * @param base SDADC peripheral base address.
985 *
986 * @return The FIFO full interrupt status flag.
987 * - @b true The FIFO full interrupt has occurred.
988 * - @b false The FIFO full interrupt has not occurred.
989 */
SDADC_CheckGlobalFifoInterrupted(SDADC_Type * base)990 static inline bool SDADC_CheckGlobalFifoInterrupted(SDADC_Type *base)
991 {
992 return (0UL != ((base->FIFO_INTERRUPT & SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_MASK) >>
993 SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_SHIFT));
994 }
995
996 /*!
997 * @brief This function is used to clear the FIFO full interrupt status flag.
998 *
999 * @param base SDADC peripheral base address.
1000 */
SDADC_ClearGlobalFifoIntStatusFlag(SDADC_Type * base)1001 static inline void SDADC_ClearGlobalFifoIntStatusFlag(SDADC_Type *base)
1002 {
1003 base->FIFO_INTERRUPT |= SDADC_FIFO_INTERRUPT_FIFO_INTERRUPT_MASK;
1004 }
1005
1006 /*!
1007 * @brief This function is used to enable or disable the FIFO full interrupt.
1008 *
1009 * @param base SDADC peripheral base address.
1010 * @param mask Mask value to enable or disable interrupt, please refer to @ref _sdadc_fifo_int_enable for details.
1011 * @param enable Indicates enable or disable the FIFO full interrupt.
1012 * - @b true Enable interrupt
1013 * - @b false Disable interrupt
1014 */
SDADC_ControlFifoIntEnable(SDADC_Type * base,uint32_t mask,bool enable)1015 static inline void SDADC_ControlFifoIntEnable(SDADC_Type *base, uint32_t mask, bool enable)
1016 {
1017 if (enable)
1018 {
1019 base->FIFO_WATERMARK_ERROR_CTL |= mask;
1020 }
1021 else
1022 {
1023 base->FIFO_WATERMARK_ERROR_CTL &= ~mask;
1024 }
1025 }
1026
1027 /*!
1028 * @brief This function is used to enable or disable the FIFO watermark.
1029 *
1030 * @param base SDADC peripheral base address.
1031 * @param mask Mask value to enable or disable watermark, please refer to @ref _sdadc_fifo_watermark_enable for details.
1032 * @param enable Indicates enable or disable the FIFO watermark.
1033 * - @b true Enable watermark
1034 * - @b false Disable watermark
1035 */
SDADC_ControlFifoWatermarkEnable(SDADC_Type * base,uint32_t mask,bool enable)1036 static inline void SDADC_ControlFifoWatermarkEnable(SDADC_Type *base, uint32_t mask, bool enable)
1037 {
1038 if (enable)
1039 {
1040 base->FIFO_WATERMARK_ERROR_CTL |= mask;
1041 }
1042 else
1043 {
1044 base->FIFO_WATERMARK_ERROR_CTL &= ~mask;
1045 }
1046 }
1047
1048 /*!
1049 * @brief This function is used to get the FIFO full interrupt status flags.
1050 *
1051 * @param base SDADC peripheral base address.
1052 *
1053 * @return Status flags of the FIFO full interrupt.
1054 */
SDADC_GetFifoIntStatusFlags(SDADC_Type * base)1055 static inline uint8_t SDADC_GetFifoIntStatusFlags(SDADC_Type *base)
1056 {
1057 return (uint8_t)((base->FIFO_WATERMARK_ERROR_ST & SDADC_FIFO_FULL_INT_STATUS_MASK) >>
1058 SDADC_FIFO_FULL_INT_STATUS_SHIFT);
1059 }
1060
1061 /*!
1062 * @brief This function is used to get the FIFO watermark status flags.
1063 *
1064 * @param base SDADC peripheral base address.
1065 *
1066 * @return Status flags of the FIFO watermark.
1067 */
SDADC_GetFifoWatermarkStatusFlags(SDADC_Type * base)1068 static inline uint8_t SDADC_GetFifoWatermarkStatusFlags(SDADC_Type *base)
1069 {
1070 return (uint8_t)((base->FIFO_WATERMARK_ERROR_ST & SDADC_FIFO_WATERMARK_STATUS_MASK) >>
1071 SDADC_FIFO_WATERMARK_STATUS_SHIFT);
1072 }
1073
1074 /*!
1075 * @brief This function is used to configure FIFO watermark.
1076 *
1077 * @param base SDADC peripheral base address.
1078 * @param number channel number, refer @ref sdadc_channel_number_t for details.
1079 * @param type channel type, refer @ref sdadc_channel_type_t for details.
1080 * @param waterMark WaterMark value, see @ref sdadc_watermark_t for details.
1081 */
SDADC_ConfigureFifoWatermark(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,sdadc_watermark_t waterMark)1082 static inline void SDADC_ConfigureFifoWatermark(SDADC_Type *base,
1083 sdadc_channel_number_t number,
1084 sdadc_channel_type_t type,
1085 sdadc_watermark_t waterMark)
1086 {
1087 if (type == kSDADC_Channel_PSide_Type)
1088 {
1089 base->FIFO_WATERMARK_CTL = ((base->FIFO_WATERMARK_CTL & (~SDADC_FIFO_WATERMARK_CTL_P_MASK(number))) |
1090 SDADC_FIFO_WATERMARK_CTL_P(waterMark.pSideWatermark, number));
1091 }
1092 else if (type == kSDADC_Channel_NSide_Type)
1093 {
1094 base->FIFO_WATERMARK_CTL = ((base->FIFO_WATERMARK_CTL & (~SDADC_FIFO_WATERMARK_CTL_N_MASK(number))) |
1095 SDADC_FIFO_WATERMARK_CTL_N(waterMark.nSideWatermark, number));
1096 }
1097 else
1098 {
1099 base->FIFO_WATERMARK_CTL =
1100 ((base->FIFO_WATERMARK_CTL &
1101 (~(SDADC_FIFO_WATERMARK_CTL_P_MASK(number) | SDADC_FIFO_WATERMARK_CTL_N_MASK(number)))) |
1102 (SDADC_FIFO_WATERMARK_CTL_P(waterMark.pSideWatermark, number) |
1103 SDADC_FIFO_WATERMARK_CTL_N(waterMark.nSideWatermark, number)));
1104 }
1105 }
1106
1107 /*!
1108 * @brief This function is used to reset the specific channel side FIFO's read or/and write pointer.
1109 *
1110 * @param base SDADC peripheral base address.
1111 * @param number channel number, refer @ref sdadc_channel_number_t for details.
1112 * @param type channel type, refer @ref sdadc_channel_type_t for details.
1113 * @param operation Indicates which reset operation to do, refer @ref sdadc_fifo_reset_operation_t for details.
1114 */
SDADC_ControlFifoReadWriteReset(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type,sdadc_fifo_reset_operation_t operation)1115 static inline void SDADC_ControlFifoReadWriteReset(SDADC_Type *base,
1116 sdadc_channel_number_t number,
1117 sdadc_channel_type_t type,
1118 sdadc_fifo_reset_operation_t operation)
1119 {
1120 if (type == kSDADC_Channel_PSide_Type)
1121 {
1122 base->FIFO_WR_RD_CTL |= (operation << ((number * 4U) + SDADC_FIFO_WR_RD_CTL_WR_0_P_RST_SHIFT));
1123 }
1124 else if (type == kSDADC_Channel_NSide_Type)
1125 {
1126 base->FIFO_WR_RD_CTL |= (operation << ((number * 4U) + SDADC_FIFO_WR_RD_CTL_WR_0_N_RST_SHIFT));
1127 }
1128 else
1129 {
1130 base->FIFO_WR_RD_CTL |= ((operation << ((number * 4U) + SDADC_FIFO_WR_RD_CTL_WR_0_P_RST_SHIFT)) |
1131 (operation << ((number * 4U) + SDADC_FIFO_WR_RD_CTL_WR_0_N_RST_SHIFT)));
1132 }
1133 }
1134
1135 /*!
1136 * @brief This function is used to get the specific channel side FIFO's available entries.
1137 *
1138 * @note In the differential mode, the bit stream is converted to 24bit data (FIFO_x_P[23:0]) by the P-Side decimator,
1139 * the output of N-Side decimator (FIFO_x_N[23:0]) is not valid.
1140 *
1141 * @param base SDADC peripheral base address.
1142 * @param number channel number, refer @ref sdadc_channel_number_t for details.
1143 * @param type channel type, refer @ref sdadc_channel_type_t for details.
1144 *
1145 * @return The available entries of the specified FIFO, note that only the lower 5 bits of the returned data are valid.
1146 */
SDADC_GetConvChannelFifoAvailableEntries(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type)1147 static inline uint8_t SDADC_GetConvChannelFifoAvailableEntries(SDADC_Type *base,
1148 sdadc_channel_number_t number,
1149 sdadc_channel_type_t type)
1150 {
1151 uint8_t registerOffset = number / 2U;
1152 uint8_t bitfieldOffset = number % 2U * 16U;
1153 uint8_t temp = 0U;
1154
1155 if (type == kSDADC_Channel_PSide_Type)
1156 {
1157 temp =
1158 (((*((&(base->FIFO_ENTRIES_AVAIL_0)) + registerOffset)) >> bitfieldOffset) & SDADC_FIFO_ENTRIES_AVAIL_MASK);
1159 }
1160 else if (type == kSDADC_Channel_NSide_Type)
1161 {
1162 temp = (((*((&(base->FIFO_ENTRIES_AVAIL_0)) + registerOffset)) >> (bitfieldOffset + 8U)) &
1163 SDADC_FIFO_ENTRIES_AVAIL_MASK);
1164 }
1165
1166 return temp;
1167 }
1168
1169 /*!
1170 * @brief This function is used to get the specific channel side FIFO's raw data.
1171 *
1172 * @note In the differential mode, the bit stream is converted to 24bit data (FIFO_x_P[23:0]) by the P-Side decimator,
1173 * the output of N-Side decimator (FIFO_x_N[23:0]) is not valid. So the type that needs to be passed in in differential
1174 * mode is @ref kSDADC_Channel_PSide_Type.
1175 *
1176 * @param base SDADC peripheral base address.
1177 * @param number channel number, refer @ref sdadc_channel_number_t for details.
1178 * @param type channel type, refer @ref sdadc_channel_type_t for details.
1179 *
1180 * @return The raw data of the specified FIFO.
1181 */
SDADC_GetConvChannelFifoRawData(SDADC_Type * base,sdadc_channel_number_t number,sdadc_channel_type_t type)1182 static inline uint32_t SDADC_GetConvChannelFifoRawData(SDADC_Type *base,
1183 sdadc_channel_number_t number,
1184 sdadc_channel_type_t type)
1185 {
1186 uint8_t offset = 0U;
1187
1188 if (type == kSDADC_Channel_PSide_Type)
1189 {
1190 offset = number * 2U;
1191 }
1192 else if (type == kSDADC_Channel_NSide_Type)
1193 {
1194 offset = number * 2U + 1U;
1195 }
1196 else
1197 {
1198 assert(false);
1199 }
1200
1201 return (((*((&(base->FIFO_0_P)) + offset)) & SDADC_FIFO_MASK) >> SDADC_FIFO_SHIFT);
1202 }
1203
1204 /*!
1205 * @brief This function is used to copy specific conversion channels' data from FIFO to buffer.
1206 *
1207 * @note This function will copy all 16 entries in the specified FIFO.
1208 *
1209 * @param base SDADC peripheral base address.
1210 * @param group Indicates which group of channels data to obtain.
1211 * @param count Indicates how many channels in the specified group.
1212 * @param buffer The buffer which stores conversion data.
1213 */
1214 void SDADC_CopyConvChannelFifoToBuffer(SDADC_Type *base, sdadc_channel_group *group, uint8_t count, void *buffer);
1215 /*!
1216 * @}
1217 */
1218
1219 #if defined(__cplusplus)
1220 }
1221 #endif
1222
1223 /*!
1224 * @}
1225 */
1226
1227 #endif /* FSL_SDADC_H_ */
1228
