1/*
2 * Copyright 2021, 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <xtensa/xtensa.dtsi>
8#include <mem.h>
9#include <zephyr/dt-bindings/clock/imx_ccm.h>
10#include <zephyr/dt-bindings/dai/esai.h>
11#include <zephyr/dt-bindings/power/imx_scu_rsrc.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "cdns,tensilica-xtensa-lx6";
21			reg = <0>;
22
23			#address-cells = <1>;
24			#size-cells = <0>;
25
26			clic: interrupt-controller@0 {
27				compatible = "cdns,xtensa-core-intc";
28				reg = <0>;
29				interrupt-controller;
30				#interrupt-cells = <3>;
31			};
32		};
33	};
34
35	scu: system-controller {
36		ccm: clock-controller {
37			compatible = "nxp,imx-ccm";
38			#clock-cells = <3>;
39		};
40
41		iomuxc: iomuxc {
42			compatible = "nxp,imx-iomuxc-scu";
43			pinctrl: pinctrl {
44				compatible = "nxp,imx8-pinctrl";
45			};
46		};
47
48		power-domains {
49			#address-cells = <1>;
50			#size-cells = <0>;
51
52			irqstr_pd: pd@0 {
53				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
54				reg = <0>;
55				nxp,resource-id = <IMX_SC_R_IRQSTR_DSP>;
56				#power-domain-cells = <0>;
57			};
58
59			edma0_ch6_pd: pd@1 {
60				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
61				reg = <1>;
62				nxp,resource-id = <IMX_SC_R_DMA_0_CH6>;
63				#power-domain-cells = <0>;
64			};
65
66			edma0_ch7_pd: pd@2 {
67				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
68				reg = <2>;
69				nxp,resource-id = <IMX_SC_R_DMA_0_CH7>;
70				#power-domain-cells = <0>;
71			};
72
73			edma0_ch14_pd: pd@3 {
74				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
75				reg = <3>;
76				nxp,resource-id = <IMX_SC_R_DMA_0_CH14>;
77				#power-domain-cells = <0>;
78			};
79
80			edma0_ch15_pd: pd@4 {
81				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
82				reg = <4>;
83				nxp,resource-id = <IMX_SC_R_DMA_0_CH15>;
84				#power-domain-cells = <0>;
85			};
86
87			edma2_ch6_pd: pd@5 {
88				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
89				reg = <5>;
90				nxp,resource-id = <IMX_SC_R_DMA_2_CH6>;
91				#power-domain-cells = <0>;
92			};
93
94			edma2_ch7_pd: pd@6 {
95				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
96				reg = <6>;
97				nxp,resource-id = <IMX_SC_R_DMA_2_CH7>;
98				#power-domain-cells = <0>;
99			};
100
101			edma2_ch14_pd: pd@7 {
102				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
103				reg = <7>;
104				nxp,resource-id = <IMX_SC_R_DMA_2_CH14>;
105				#power-domain-cells = <0>;
106			};
107
108			edma2_ch15_pd: pd@8 {
109				compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
110				reg = <8>;
111				nxp,resource-id = <IMX_SC_R_DMA_2_CH15>;
112				#power-domain-cells = <0>;
113			};
114		};
115	};
116
117	sram0: memory@92400000 {
118		device_type = "memory";
119		compatible = "mmio-sram";
120		reg = <0x92400000 DT_SIZE_K(512)>;
121	};
122
123	sram1: memory@92c00000 {
124		device_type = "memory";
125		compatible = "mmio-sram";
126		reg = <0x92c00000 DT_SIZE_K(512)>;
127	};
128
129	edma0: dma@591f0000 {
130		compatible = "nxp,edma";
131		reg = <0x591f0000 (DT_SIZE_K(64) * 33)>;
132		valid-channels = <6>, <7>, <14>, <15>;
133		power-domains = <&edma0_ch6_pd>, <&edma0_ch7_pd>,
134				<&edma0_ch14_pd>, <&edma0_ch15_pd>;
135		interrupts-extended = <&master6 58>, <&master6 58>,
136				<&master5 29>, <&master5 29>;
137		#dma-cells = <2>;
138		status = "disabled";
139	};
140
141	sai1: dai@59050000 {
142		compatible = "nxp,dai-sai";
143		reg = <0x59050000 DT_SIZE_K(64)>;
144		interrupt-parent = <&master5>;
145		interrupts = <28>;
146		clocks = <&ccm IMX_CCM_SAI1_CLK 0x0 0x0>;
147		clock-names = "bus";
148		dai-index = <1>;
149		dmas = <&edma0 15 0>, <&edma0 14 0>;
150		dma-names = "tx", "rx";
151		status = "disabled";
152	};
153
154	esai0: dai@59010000 {
155		compatible = "nxp,dai-esai";
156		reg = <0x59010000 DT_SIZE_K(64)>;
157		dmas = <&edma0 7 0>, <&edma0 6 0>;
158		dma-names = "tx", "rx";
159		esai-pin-modes = <ESAI_PIN_HCKR ESAI_PIN_DISCONNECTED>,
160				<ESAI_PIN_HCKT ESAI_PIN_DISCONNECTED>,
161				<ESAI_PIN_SDO4_SDI1 ESAI_PIN_DISCONNECTED>,
162				<ESAI_PIN_SDO3_SDI2 ESAI_PIN_DISCONNECTED>,
163				<ESAI_PIN_SDO2_SDI3 ESAI_PIN_DISCONNECTED>,
164				<ESAI_PIN_SDO1 ESAI_PIN_DISCONNECTED>;
165		status = "disabled";
166	};
167
168	/* LSIO MU2, used to interact with the SCFW */
169	scu_mu: mailbox@5d1d0000 {
170		reg = <0x5d1d0000 DT_SIZE_K(64)>;
171	};
172
173	lpuart2: serial@5a080000 {
174		compatible = "nxp,imx-lpuart", "nxp,lpuart";
175		reg = <0x5a080000 DT_SIZE_K(4)>;
176		interrupt-parent = <&master4>;
177		interrupts = <3>;
178		/* this is actually LPUART2 clock but the macro indexing starts at 1 */
179		clocks = <&ccm IMX_CCM_LPUART3_CLK 0x0 0x0>;
180		status = "disabled";
181	};
182
183	mailbox0: mailbox@5d310000 {
184		compatible = "nxp,imx-mu";
185		reg = <0x5d310000 0x10000>;
186		interrupt-parent = <&clic>;
187		interrupts = <7 0 0>;
188		rdc = <0>;
189		status = "disabled";
190	};
191};
192