1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SYSCON_STRUCT_H_ 15 #define _SOC_SYSCON_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct syscon_dev_s { 24 union { 25 struct { 26 uint32_t pre_div: 10; 27 uint32_t clk_320m_en: 1; 28 uint32_t clk_en: 1; 29 uint32_t rst_tick: 1; 30 uint32_t quick_clk_chng: 1; 31 uint32_t reserved14: 18; 32 }; 33 uint32_t val; 34 }clk_conf; 35 union { 36 struct { 37 uint32_t xtal_tick: 8; 38 uint32_t reserved8: 24; 39 }; 40 uint32_t val; 41 }xtal_tick_conf; 42 union { 43 struct { 44 uint32_t pll_tick: 8; 45 uint32_t reserved8: 24; 46 }; 47 uint32_t val; 48 }pll_tick_conf; 49 union { 50 struct { 51 uint32_t ck8m_tick: 8; 52 uint32_t reserved8: 24; 53 }; 54 uint32_t val; 55 }ck8m_tick_conf; 56 union { 57 struct { 58 uint32_t start_force: 1; 59 uint32_t start: 1; 60 uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/ 61 uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ 62 uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ 63 uint32_t sar_clk_gated: 1; 64 uint32_t sar_clk_div: 8; /*SAR clock divider*/ 65 uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ 66 uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ 67 uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ 68 uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ 69 uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ 70 uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ 71 uint32_t reserved27: 5; 72 }; 73 uint32_t val; 74 }saradc_ctrl; 75 union { 76 struct { 77 uint32_t meas_num_limit: 1; 78 uint32_t max_meas_num: 8; /*max conversion number*/ 79 uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ 80 uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ 81 uint32_t reserved11: 21; 82 }; 83 uint32_t val; 84 }saradc_ctrl2; 85 union { 86 struct { 87 uint32_t rstb_wait: 8; 88 uint32_t standby_wait: 8; 89 uint32_t start_wait: 8; 90 uint32_t sample_cycle: 8; /*sample cycles*/ 91 }; 92 uint32_t val; 93 }saradc_fsm; 94 uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 3 for ADC1 pattern table*/ 95 uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 3 for ADC2 pattern table*/ 96 union { 97 struct { 98 uint32_t apll_tick: 8; 99 uint32_t reserved8: 24; 100 }; 101 uint32_t val; 102 }apll_tick_conf; 103 uint32_t reserved_40; 104 uint32_t reserved_44; 105 uint32_t reserved_48; 106 uint32_t reserved_4c; 107 uint32_t reserved_50; 108 uint32_t reserved_54; 109 uint32_t reserved_58; 110 uint32_t reserved_5c; 111 uint32_t reserved_60; 112 uint32_t reserved_64; 113 uint32_t reserved_68; 114 uint32_t reserved_6c; 115 uint32_t reserved_70; 116 uint32_t reserved_74; 117 uint32_t reserved_78; 118 uint32_t date; /**/ 119 } syscon_dev_t; 120 121 #ifdef __cplusplus 122 } 123 #endif 124 extern syscon_dev_t SYSCON; 125 #endif /* _SOC_SYSCON_STRUCT_H_ */ 126
