1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 typedef volatile struct apb_saradc_dev_s { 15 union { 16 struct { 17 uint32_t start_force: 1; 18 uint32_t start: 1; 19 uint32_t reserved2: 4; /*0: single mode 1: double mode 2: alternate mode*/ 20 uint32_t sar_clk_gated: 1; 21 uint32_t sar_clk_div: 8; /*SAR clock divider*/ 22 uint32_t sar_patt_len: 3; /*0 ~ 15 means length 1 ~ 16*/ 23 uint32_t reserved18: 5; 24 uint32_t sar_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ 25 uint32_t reserved24: 3; 26 uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ 27 uint32_t reserved29: 1; 28 uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ 29 }; 30 uint32_t val; 31 } ctrl; 32 union { 33 struct { 34 uint32_t meas_num_limit: 1; 35 uint32_t max_meas_num: 8; /*max conversion number*/ 36 uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ 37 uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ 38 uint32_t reserved11: 1; /*1: select saradc timer 0: i2s_ws trigger*/ 39 uint32_t timer_target: 12; /*to set saradc timer target*/ 40 uint32_t timer_en: 1; /*to enable saradc timer trigger*/ 41 uint32_t reserved25: 7; 42 }; 43 uint32_t val; 44 } ctrl2; 45 union { 46 struct { 47 uint32_t reserved0: 26; 48 uint32_t filter_factor1: 3; 49 uint32_t filter_factor0: 3; 50 }; 51 uint32_t val; 52 } filter_ctrl1; 53 union { 54 struct { 55 uint32_t xpd_wait: 8; 56 uint32_t rstb_wait: 8; 57 uint32_t standby_wait: 8; 58 uint32_t reserved24: 8; 59 }; 60 uint32_t val; 61 } fsm_wait; 62 uint32_t sar1_status; /**/ 63 uint32_t sar2_status; /**/ 64 union { 65 struct { 66 uint32_t sar_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ 67 uint32_t reserved24: 8; 68 }; 69 uint32_t val; 70 } sar_patt_tab[2]; 71 union { 72 struct { 73 uint32_t reserved0: 23; 74 uint32_t onetime_atten: 2; 75 uint32_t onetime_channel: 4; 76 uint32_t onetime_start: 1; 77 uint32_t adc2_onetime_sample: 1; 78 uint32_t adc1_onetime_sample: 1; 79 }; 80 uint32_t val; 81 } onetime_sample; 82 union { 83 struct { 84 uint32_t reserved0: 2; 85 uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ 86 uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ 87 uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ 88 uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ 89 uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ 90 uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ 91 uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ 92 uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ 93 uint32_t reserved13: 19; 94 }; 95 uint32_t val; 96 } apb_adc_arb_ctrl; 97 union { 98 struct { 99 uint32_t reserved0: 18; 100 uint32_t filter_channel1: 4; 101 uint32_t filter_channel0: 4; /*apb_adc1_filter_factor*/ 102 uint32_t reserved26: 5; 103 uint32_t filter_reset: 1; /*enable apb_adc1_filter*/ 104 }; 105 uint32_t val; 106 } filter_ctrl0; 107 union { 108 struct { 109 uint32_t adc1_data: 17; 110 uint32_t reserved17:15; 111 }; 112 uint32_t val; 113 } apb_saradc1_data_status; 114 union { 115 struct { 116 uint32_t adc2_data: 17; 117 uint32_t reserved17:15; 118 }; 119 uint32_t val; 120 } apb_saradc2_data_status; 121 union { 122 struct { 123 uint32_t thres0_channel: 4; 124 uint32_t reserved4: 1; 125 uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/ 126 uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/ 127 uint32_t reserved31: 1; 128 }; 129 uint32_t val; 130 } thres0_ctrl; 131 union { 132 struct { 133 uint32_t thres1_channel: 4; 134 uint32_t reserved4: 1; 135 uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/ 136 uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/ 137 uint32_t reserved31: 1; 138 }; 139 uint32_t val; 140 } thres1_ctrl; 141 union { 142 struct { 143 uint32_t reserved0: 27; 144 uint32_t thres_all_en: 1; 145 uint32_t reserved28: 2; 146 uint32_t thres1_en: 1; 147 uint32_t thres0_en: 1; 148 }; 149 uint32_t val; 150 } thres_ctrl; 151 union { 152 struct { 153 uint32_t reserved0: 26; 154 uint32_t thres1_low: 1; 155 uint32_t thres0_low: 1; 156 uint32_t thres1_high: 1; 157 uint32_t thres0_high: 1; 158 uint32_t adc2_done: 1; 159 uint32_t adc1_done: 1; 160 }; 161 uint32_t val; 162 } int_ena; 163 union { 164 struct { 165 uint32_t reserved0: 26; 166 uint32_t thres1_low: 1; 167 uint32_t thres0_low: 1; 168 uint32_t thres1_high: 1; 169 uint32_t thres0_high: 1; 170 uint32_t adc2_done: 1; 171 uint32_t adc1_done: 1; 172 }; 173 uint32_t val; 174 } int_raw; 175 union { 176 struct { 177 uint32_t reserved0: 26; 178 uint32_t thres1_low: 1; 179 uint32_t thres0_low: 1; 180 uint32_t thres1_high: 1; 181 uint32_t thres0_high: 1; 182 uint32_t adc2_done: 1; 183 uint32_t adc1_done: 1; 184 }; 185 uint32_t val; 186 } int_st; 187 union { 188 struct { 189 uint32_t reserved0: 26; 190 uint32_t thres1_low: 1; 191 uint32_t thres0_low: 1; 192 uint32_t thres1_high: 1; 193 uint32_t thres0_high: 1; 194 uint32_t adc2_done: 1; 195 uint32_t adc1_done: 1; 196 }; 197 uint32_t val; 198 } int_clr; 199 union { 200 struct { 201 uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ 202 uint32_t reserved16: 14; 203 uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ 204 uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ 205 }; 206 uint32_t val; 207 } dma_conf; 208 union { 209 struct { 210 uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ 211 uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ 212 uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ 213 uint32_t clk_en: 1; 214 uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ 215 uint32_t reserved23: 9; 216 }; 217 uint32_t val; 218 } apb_adc_clkm_conf; 219 union { 220 struct { 221 uint32_t tsens_out: 8; 222 uint32_t reserved8: 5; 223 uint32_t tsens_in_inv: 1; 224 uint32_t tsens_clk_div: 8; 225 uint32_t tsens_pu: 1; 226 uint32_t reserved23: 9; 227 }; 228 uint32_t val; 229 } apb_tsens_ctrl; 230 union { 231 struct { 232 uint32_t tsens_xpd_wait: 12; 233 uint32_t tsens_xpd_force: 2; 234 uint32_t tsens_clk_inv: 1; 235 uint32_t tsens_clk_sel: 1; 236 uint32_t reserved16: 16; 237 }; 238 uint32_t val; 239 } apb_tsens_ctrl2; 240 union { 241 struct { 242 uint32_t cali_cfg: 17; 243 uint32_t reserved17:15; 244 }; 245 uint32_t val; 246 } cali; 247 uint32_t reserved_64; 248 uint32_t reserved_68; 249 uint32_t reserved_6c; 250 uint32_t reserved_70; 251 uint32_t reserved_74; 252 uint32_t reserved_78; 253 uint32_t reserved_7c; 254 uint32_t reserved_80; 255 uint32_t reserved_84; 256 uint32_t reserved_88; 257 uint32_t reserved_8c; 258 uint32_t reserved_90; 259 uint32_t reserved_94; 260 uint32_t reserved_98; 261 uint32_t reserved_9c; 262 uint32_t reserved_a0; 263 uint32_t reserved_a4; 264 uint32_t reserved_a8; 265 uint32_t reserved_ac; 266 uint32_t reserved_b0; 267 uint32_t reserved_b4; 268 uint32_t reserved_b8; 269 uint32_t reserved_bc; 270 uint32_t reserved_c0; 271 uint32_t reserved_c4; 272 uint32_t reserved_c8; 273 uint32_t reserved_cc; 274 uint32_t reserved_d0; 275 uint32_t reserved_d4; 276 uint32_t reserved_d8; 277 uint32_t reserved_dc; 278 uint32_t reserved_e0; 279 uint32_t reserved_e4; 280 uint32_t reserved_e8; 281 uint32_t reserved_ec; 282 uint32_t reserved_f0; 283 uint32_t reserved_f4; 284 uint32_t reserved_f8; 285 uint32_t reserved_fc; 286 uint32_t reserved_100; 287 uint32_t reserved_104; 288 uint32_t reserved_108; 289 uint32_t reserved_10c; 290 uint32_t reserved_110; 291 uint32_t reserved_114; 292 uint32_t reserved_118; 293 uint32_t reserved_11c; 294 uint32_t reserved_120; 295 uint32_t reserved_124; 296 uint32_t reserved_128; 297 uint32_t reserved_12c; 298 uint32_t reserved_130; 299 uint32_t reserved_134; 300 uint32_t reserved_138; 301 uint32_t reserved_13c; 302 uint32_t reserved_140; 303 uint32_t reserved_144; 304 uint32_t reserved_148; 305 uint32_t reserved_14c; 306 uint32_t reserved_150; 307 uint32_t reserved_154; 308 uint32_t reserved_158; 309 uint32_t reserved_15c; 310 uint32_t reserved_160; 311 uint32_t reserved_164; 312 uint32_t reserved_168; 313 uint32_t reserved_16c; 314 uint32_t reserved_170; 315 uint32_t reserved_174; 316 uint32_t reserved_178; 317 uint32_t reserved_17c; 318 uint32_t reserved_180; 319 uint32_t reserved_184; 320 uint32_t reserved_188; 321 uint32_t reserved_18c; 322 uint32_t reserved_190; 323 uint32_t reserved_194; 324 uint32_t reserved_198; 325 uint32_t reserved_19c; 326 uint32_t reserved_1a0; 327 uint32_t reserved_1a4; 328 uint32_t reserved_1a8; 329 uint32_t reserved_1ac; 330 uint32_t reserved_1b0; 331 uint32_t reserved_1b4; 332 uint32_t reserved_1b8; 333 uint32_t reserved_1bc; 334 uint32_t reserved_1c0; 335 uint32_t reserved_1c4; 336 uint32_t reserved_1c8; 337 uint32_t reserved_1cc; 338 uint32_t reserved_1d0; 339 uint32_t reserved_1d4; 340 uint32_t reserved_1d8; 341 uint32_t reserved_1dc; 342 uint32_t reserved_1e0; 343 uint32_t reserved_1e4; 344 uint32_t reserved_1e8; 345 uint32_t reserved_1ec; 346 uint32_t reserved_1f0; 347 uint32_t reserved_1f4; 348 uint32_t reserved_1f8; 349 uint32_t reserved_1fc; 350 uint32_t reserved_200; 351 uint32_t reserved_204; 352 uint32_t reserved_208; 353 uint32_t reserved_20c; 354 uint32_t reserved_210; 355 uint32_t reserved_214; 356 uint32_t reserved_218; 357 uint32_t reserved_21c; 358 uint32_t reserved_220; 359 uint32_t reserved_224; 360 uint32_t reserved_228; 361 uint32_t reserved_22c; 362 uint32_t reserved_230; 363 uint32_t reserved_234; 364 uint32_t reserved_238; 365 uint32_t reserved_23c; 366 uint32_t reserved_240; 367 uint32_t reserved_244; 368 uint32_t reserved_248; 369 uint32_t reserved_24c; 370 uint32_t reserved_250; 371 uint32_t reserved_254; 372 uint32_t reserved_258; 373 uint32_t reserved_25c; 374 uint32_t reserved_260; 375 uint32_t reserved_264; 376 uint32_t reserved_268; 377 uint32_t reserved_26c; 378 uint32_t reserved_270; 379 uint32_t reserved_274; 380 uint32_t reserved_278; 381 uint32_t reserved_27c; 382 uint32_t reserved_280; 383 uint32_t reserved_284; 384 uint32_t reserved_288; 385 uint32_t reserved_28c; 386 uint32_t reserved_290; 387 uint32_t reserved_294; 388 uint32_t reserved_298; 389 uint32_t reserved_29c; 390 uint32_t reserved_2a0; 391 uint32_t reserved_2a4; 392 uint32_t reserved_2a8; 393 uint32_t reserved_2ac; 394 uint32_t reserved_2b0; 395 uint32_t reserved_2b4; 396 uint32_t reserved_2b8; 397 uint32_t reserved_2bc; 398 uint32_t reserved_2c0; 399 uint32_t reserved_2c4; 400 uint32_t reserved_2c8; 401 uint32_t reserved_2cc; 402 uint32_t reserved_2d0; 403 uint32_t reserved_2d4; 404 uint32_t reserved_2d8; 405 uint32_t reserved_2dc; 406 uint32_t reserved_2e0; 407 uint32_t reserved_2e4; 408 uint32_t reserved_2e8; 409 uint32_t reserved_2ec; 410 uint32_t reserved_2f0; 411 uint32_t reserved_2f4; 412 uint32_t reserved_2f8; 413 uint32_t reserved_2fc; 414 uint32_t reserved_300; 415 uint32_t reserved_304; 416 uint32_t reserved_308; 417 uint32_t reserved_30c; 418 uint32_t reserved_310; 419 uint32_t reserved_314; 420 uint32_t reserved_318; 421 uint32_t reserved_31c; 422 uint32_t reserved_320; 423 uint32_t reserved_324; 424 uint32_t reserved_328; 425 uint32_t reserved_32c; 426 uint32_t reserved_330; 427 uint32_t reserved_334; 428 uint32_t reserved_338; 429 uint32_t reserved_33c; 430 uint32_t reserved_340; 431 uint32_t reserved_344; 432 uint32_t reserved_348; 433 uint32_t reserved_34c; 434 uint32_t reserved_350; 435 uint32_t reserved_354; 436 uint32_t reserved_358; 437 uint32_t reserved_35c; 438 uint32_t reserved_360; 439 uint32_t reserved_364; 440 uint32_t reserved_368; 441 uint32_t reserved_36c; 442 uint32_t reserved_370; 443 uint32_t reserved_374; 444 uint32_t reserved_378; 445 uint32_t reserved_37c; 446 uint32_t reserved_380; 447 uint32_t reserved_384; 448 uint32_t reserved_388; 449 uint32_t reserved_38c; 450 uint32_t reserved_390; 451 uint32_t reserved_394; 452 uint32_t reserved_398; 453 uint32_t reserved_39c; 454 uint32_t reserved_3a0; 455 uint32_t reserved_3a4; 456 uint32_t reserved_3a8; 457 uint32_t reserved_3ac; 458 uint32_t reserved_3b0; 459 uint32_t reserved_3b4; 460 uint32_t reserved_3b8; 461 uint32_t reserved_3bc; 462 uint32_t reserved_3c0; 463 uint32_t reserved_3c4; 464 uint32_t reserved_3c8; 465 uint32_t reserved_3cc; 466 uint32_t reserved_3d0; 467 uint32_t reserved_3d4; 468 uint32_t reserved_3d8; 469 uint32_t reserved_3dc; 470 uint32_t reserved_3e0; 471 uint32_t reserved_3e4; 472 uint32_t reserved_3e8; 473 uint32_t reserved_3ec; 474 uint32_t reserved_3f0; 475 uint32_t reserved_3f4; 476 uint32_t reserved_3f8; 477 uint32_t apb_ctrl_date; /**/ 478 } apb_saradc_dev_t; 479 extern apb_saradc_dev_t APB_SARADC; 480 #ifdef __cplusplus 481 } 482 #endif 483
