1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer 2 * and temperature (MFD) sensor driver 3 */ 4 5 /* 6 * Copyright (c) 2016 Intel Corporation 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 11 #ifndef ZEPHYR_DRIVERS_SENSOR_LSM9DS0_MFD_LSM9DS0_MFD_H_ 12 #define ZEPHYR_DRIVERS_SENSOR_LSM9DS0_MFD_LSM9DS0_MFD_H_ 13 14 #include <zephyr/types.h> 15 #include <zephyr/sys/util.h> 16 #include <zephyr/drivers/i2c.h> 17 18 #define LSM9DS0_MFD_REG_OUT_TEMP_L_XM 0x05 19 #define LSM9DS0_MFD_REG_OUT_TEMP_H_XM 0x06 20 21 #define LSM9DS0_MFD_REG_STATUS_REG_M 0x07 22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7) 23 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZYXMOR 7 24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6) 25 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZMOR 6 26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5) 27 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_YMOR 5 28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4) 29 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_XMOR 4 30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3) 31 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZYXMDA 3 32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2) 33 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZMDA 2 34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1) 35 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_YMDA 1 36 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMDA BIT(0) 37 #define LSM9DS0_MFD_SHIFT_STATUS_REG_XMDA 0 38 39 #define LSM9DS0_MFD_REG_OUT_X_L_M 0x08 40 #define LSM9DS0_MFD_REG_OUT_X_H_M 0x09 41 #define LSM9DS0_MFD_REG_OUT_Y_L_M 0x0A 42 #define LSM9DS0_MFD_REG_OUT_Y_H_M 0x0B 43 #define LSM9DS0_MFD_REG_OUT_Z_L_M 0x0C 44 #define LSM9DS0_MFD_REG_OUT_Z_H_M 0x0D 45 46 #define LSM9DS0_MFD_REG_WHO_AM_I_XM 0x0F 47 #define LSM9DS0_MFD_VAL_WHO_AM_I_XM 0x49 48 49 #define LSM9DS0_MFD_REG_INT_CTRL_REG_M 0x12 50 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_XMIEN BIT(7) 51 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_XMIEN 7 52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6) 53 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_YMIEN 6 54 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_ZMIEN BIT(5) 55 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_ZMIEN 5 56 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_PP_OD BIT(4) 57 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_PP_OD 4 58 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_IEA BIT(3) 59 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_IEA 3 60 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_IEL BIT(2) 61 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_IEL 2 62 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_4D BIT(1) 63 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_4D 1 64 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_MIEN BIT(0) 65 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_MIEN 0 66 67 #define LSM9DS0_MFD_REG_INT_SRC_REG_M 0x13 68 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_X BIT(7) 69 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_X 7 70 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Y BIT(6) 71 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_Y 6 72 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Z BIT(5) 73 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_Z 5 74 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_NTH_X BIT(4) 75 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_NTH_X 4 76 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_NTH_Y BIT(3) 77 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_NTH_Y 3 78 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_NTH_Z BIT(2) 79 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_NTH_Z 2 80 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_MROI BIT(1) 81 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_MROI 1 82 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_MINT BIT(0) 83 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_MINT 0 84 85 #define LSM9DS0_MFD_REG_INT_THS_L_M 0x14 86 #define LSM9DS0_MFD_REG_INT_THS_H_M 0x15 87 #define LSM9DS0_MFD_REG_OFFSET_X_L_M 0x16 88 #define LSM9DS0_MFD_REG_OFFSET_X_H_M 0x17 89 #define LSM9DS0_MFD_REG_OFFSET_Y_L_M 0x18 90 #define LSM9DS0_MFD_REG_OFFSET_Y_H_M 0x19 91 #define LSM9DS0_MFD_REG_OFFSET_Z_L_M 0x1A 92 #define LSM9DS0_MFD_REG_OFFSET_Z_H_M 0x1B 93 94 #define LSM9DS0_MFD_REG_REFERENCE_X 0x1C 95 #define LSM9DS0_MFD_REG_REFERENCE_Y 0x1D 96 #define LSM9DS0_MFD_REG_REFERENCE_Z 0x1E 97 98 #define LSM9DS0_MFD_REG_CTRL_REG0_XM 0x1F 99 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_BOOT BIT(7) 100 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_BOOT 7 101 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_FIFO_EN BIT(6) 102 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_FIFO_EN 6 103 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_WTM_EN BIT(5) 104 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_WTM_EN 5 105 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_HP_C BIT(2) 106 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_HP_C 2 107 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_HPIS1 BIT(1) 108 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_HPIS1 1 109 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_HPIS2 BIT(0) 110 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_HPIS2 0 111 112 #define LSM9DS0_MFD_REG_CTRL_REG1_XM 0x20 113 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \ 114 BIT(4)) 115 #define LSM9DS0_MFD_SHIFT_CTRL_REG1_XM_AODR 4 116 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_BDU BIT(3) 117 #define LSM9DS0_MFD_SHIFT_CTRL_REG1_XM_BDU 3 118 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AZEN BIT(2) 119 #define LSM9DS0_MFD_SHIFT_CTRL_REG1_XM_AZEN 2 120 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AYEN BIT(1) 121 #define LSM9DS0_MFD_SHIFT_CTRL_REG1_XM_AYEN 1 122 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AXEN BIT(0) 123 #define LSM9DS0_MFD_SHIFT_CTRL_REG1_XM_AXEN 0 124 125 #define LSM9DS0_MFD_REG_CTRL_REG2_XM 0x21 126 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_ABW (BIT(7) | BIT(6)) 127 #define LSM9DS0_MFD_SHIFT_CTRL_REG2_XM_ABW 6 128 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_AFS (BIT(5) | BIT(4) | BIT(3)) 129 #define LSM9DS0_MFD_SHIFT_CTRL_REG2_XM_AFS 3 130 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_AST (BIT(2) | BIT(1)) 131 #define LSM9DS0_MFD_SHIFT_CTRL_REG2_XM_AST 1 132 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_SIM BIT(0) 133 #define LSM9DS0_MFD_SHIFT_CTRL_REG2_XM_SIM 0 134 135 #define LSM9DS0_MFD_REG_CTRL_REG3_XM 0x22 136 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_BOOT BIT(7) 137 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_BOOT 7 138 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_TAP BIT(6) 139 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_TAP 6 140 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INT1 BIT(5) 141 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_INT1 5 142 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INT2 BIT(4) 143 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_INT2 4 144 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_INTM BIT(3) 145 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_INTM 3 146 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_DRDYA BIT(2) 147 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_DRDYA 2 148 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_DRDYM BIT(1) 149 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_DRDYM 1 150 #define LSM9DS0_MFD_MASK_CTRL_REG3_XM_P1_EMPTY BIT(0) 151 #define LSM9DS0_MFD_SHIFT_CTRL_REG3_XM_P1_EMPTY 0 152 153 #define LSM9DS0_MFD_REG_CTRL_REG4_XM 0x23 154 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_TAP BIT(7) 155 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_TAP 7 156 #define LMS9DS0_MFD_MASK_CTRL_REG4_XM_P2_INT1 BIT(6) 157 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_INT1 6 158 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_INT2 BIT(5) 159 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_INT2 5 160 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_INTM BIT(4) 161 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_INTM 4 162 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_DRDYA BIT(3) 163 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_DRDYA 3 164 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_DRDYM BIT(2) 165 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_DRDYM 2 166 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_OVR BIT(1) 167 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_OVR 1 168 #define LSM9DS0_MFD_MASK_CTRL_REG4_XM_P2_WTM BIT(0) 169 #define LSM9DS0_MFD_SHIFT_CTRL_REG4_XM_P2_WTM 0 170 171 #define LSM9DS0_MFD_REG_CTRL_REG5_XM 0x24 172 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_TEMP_EN BIT(7) 173 #define LSM9DS0_MFD_SHIFT_CTRL_REG5_XM_TEMP_EN 7 174 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_M_RES (BIT(6) | BIT(5)) 175 #define LSM9DS0_MFD_SHIFT_CTRL_REG5_XM_M_RES 5 176 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_M_ODR (BIT(4) | BIT(3) | BIT(2)) 177 #define LSM9DS0_MFD_SHIFT_CTRL_REG5_XM_M_ODR 2 178 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_LIR2 BIT(1) 179 #define LSM9DS0_MFD_SHIFT_CTRL_REG5_XM_LIR2 1 180 #define LSM9DS0_MFD_MASK_CTRL_REG5_XM_LIR1 BIT(0) 181 #define LSM9DS0_MFD_SHIFT_CTRL_REG5_XM_LIR1 0 182 183 #define LSM9DS0_MFD_REG_CTRL_REG6_XM 0x25 184 #define LSM9DS0_MFD_MASK_CTRL_REG6_XM_MFS (BIT(6) | BIT(5)) 185 #define LSM9DS0_MFD_SHIFT_CTRL_REG6_XM_MFS 5 186 187 #define LSM9DS0_MFD_REG_CTRL_REG7_XM 0x26 188 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_AHPM (BIT(7) | BIT(6)) 189 #define LSM9DS0_MFD_SHIFT_CTRL_REG7_XM_AHPM 6 190 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_AFDS BIT(5) 191 #define LSM9DS0_MFD_SHIFT_CTRL_REG7_XM_AFDS 5 192 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_MLP BIT(2) 193 #define LSM9DS0_MFD_SHIFT_CTRL_REG7_XM_MLP 2 194 #define LSM9DS0_MFD_MASK_CTRL_REG7_XM_MD (BIT(1) | BIT(0)) 195 #define LSM9DS0_MFD_SHIFT_CTRL_REG7_XM_MD 0 196 197 #define LSM9DS0_MFD_REG_STATUS_REG_A 0x27 198 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZYXAOR BIT(7) 199 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_ZYXAOR 7 200 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZAOR BIT(6) 201 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_ZAOR 6 202 #define LSM9DS0_MFD_MASK_STATUS_REG_A_YAOR BIT(5) 203 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_YAOR 5 204 #define LSM9DS0_MFD_MASK_STATUS_REG_A_XAOR BIT(4) 205 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_XAOR 4 206 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZYXADA BIT(3) 207 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_ZYXADA 3 208 #define LSM9DS0_MFD_MASK_STATUS_REG_A_ZADA BIT(2) 209 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_ZADA 2 210 #define LSM9DS0_MFD_MASK_STATUS_REG_A_YADA BIT(1) 211 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_YADA 1 212 #define LSM9DS0_MFD_MASK_STATUS_REG_A_XADA BIT(0) 213 #define LSM9DS0_MFD_SHIFT_STATUS_REG_A_XADA 0 214 215 #define LSM9DS0_MFD_REG_OUT_X_L_A 0x28 216 #define LSM9DS0_MFD_REG_OUT_X_H_A 0x29 217 #define LSM9DS0_MFD_REG_OUT_Y_L_A 0x2A 218 #define LSM9DS0_MFD_REG_OUT_Y_H_A 0x2B 219 #define LSM9DS0_MFD_REG_OUT_Z_L_A 0x2C 220 #define LSM9DS0_MFD_REG_OUT_Z_H_A 0x2D 221 222 #define LSM9DS0_MFD_REG_FIFO_CTRL_REG 0x2E 223 #define LSM9DS0_MFD_MASK_FIFO_CTRL_REG_FM (BIT(7) | BIT(6) | BIT(5)) 224 #define LSM9DS0_MFD_SHIFT_FIFO_CTRL_REG_FM 5 225 #define LSM9DS0_MFD_MASK_FIFO_CTRL_REG_FTH (BIT(4) | BIT(3) | BIT(2) | \ 226 BIT(1) | BIT(0)) 227 #define LSM9DS0_MFD_SHIFT_FIFO_CTRL_REG_FTH 0 228 229 #define LSM9DS0_MFD_REG_FIFO_SRC_REG 0x2F 230 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_WTM BIT(7) 231 #define LMS9DS0_MFD_SHIFT_FIFO_SRC_REG_WTM 7 232 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_OVRN BIT(6) 233 #define LSM9DS0_MFD_SHIFT_FIFO_SRC_REG_OVRN 6 234 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_EMPTY BIT(5) 235 #define LMS9DS0_MFD_SHIFT_FIFO_SRC_REG_EMPTY 5 236 #define LSM9DS0_MFD_MASK_FIFO_SRC_REG_FSS (BIT(4) | BIT(3) | BIT(2) | \ 237 BIT(1) | BIT(0)) 238 #define LSM9DS0_MFD_SHIFT_FIFO_SRC_REG_FSS 0 239 240 #define LSM9DS0_MFD_REG_INT_GEN_1_REG 0x30 241 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_AOI BIT(7) 242 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_AOI 7 243 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_6D BIT(6) 244 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_6D 6 245 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_ZHIE BIT(5) 246 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_ZHIE 5 247 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_ZLIE BIT(4) 248 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_ZLIE 4 249 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_YHIE BIT(3) 250 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_YHIE 3 251 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_YLIE BIT(2) 252 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_YLIE 2 253 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_XHIE BIT(1) 254 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_XHIE 1 255 #define LSM9DS0_MFD_MASK_INT_GEN_1_REG_XLIE BIT(0) 256 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_REG_XLIE 0 257 258 #define LSM9DS0_MFD_REG_INT_GEN_1_SRC 0x31 259 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_IA BIT(6) 260 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_IA 6 261 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_ZH BIT(5) 262 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_ZH 5 263 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_ZL BIT(4) 264 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_ZL 4 265 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_YH BIT(3) 266 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_YH 3 267 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_YL BIT(2) 268 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_YL 2 269 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_XH BIT(1) 270 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_XH 1 271 #define LSM9DS0_MFD_MASK_INT_GEN_1_SRC_XL BIT(0) 272 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_SRC_XL 0 273 274 #define LSM9DS0_MFD_REG_INT_GEN_1_THS 0x32 275 #define LSM9DS0_MFD_MASK_INT_GEN_1_THS_THS (BIT(6) | BIT(5) | BIT(4) | \ 276 BIT(3) | BIT(2) | BIT(1) | \ 277 BIT(0)) 278 #define LSM9DS0_MFD_SHIFT_INT_GEN_1_THS_THS 0 279 280 #define LSM9DS0_MFD_REG_INT_GEN_1_DURATION 0x33 281 #define LSM9DS0_MFD_MASK_INT_GEN_1_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \ 282 BIT(3) | BIT(2) | BIT(1) | \ 283 BIT(0)) 284 #define LMS9DS0_MFD_SHIFT_INT_GEN_1_DURATION_D 0 285 286 #define LSM9DS0_MFD_REG_INT_GEN_2_REG 0x34 287 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_AOI BIT(7) 288 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_AOI 7 289 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_6D BIT(6) 290 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_6D 6 291 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_ZHIE BIT(5) 292 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_ZHIE 5 293 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_ZLIE BIT(4) 294 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_ZLIE 4 295 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_YHIE BIT(3) 296 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_YHIE 3 297 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_YLIE BIT(2) 298 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_YLIE 2 299 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_XHIE BIT(1) 300 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_REG_XHIE 1 301 #define LSM9DS0_MFD_MASK_INT_GEN_2_REG_XLIE BIT(0) 302 #define LMS9Ds0_MFD_SHIFT_INT_GEN_2_REG_XLIE 0 303 304 #define LSM9DS0_MFD_REG_INT_GEN_2_SRC 0x35 305 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_IA BIT(6) 306 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_IA 6 307 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_ZH BIT(5) 308 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_ZH 5 309 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_ZL BIT(4) 310 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_ZL 4 311 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_YH BIT(3) 312 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_YH 3 313 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_YL BIT(2) 314 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_YL 2 315 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_XH BIT(1) 316 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_XH 1 317 #define LSM9DS0_MFD_MASK_INT_GEN_2_SRC_XL BIT(0) 318 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_SRC_XL 0 319 320 #define LSM9DS0_MFD_REG_INT_GEN_2_THS 0x36 321 #define LSM9DS0_MFD_MASK_INT_GEN_2_THS_THS (BIT(6) | BIT(5) | BIT(4) | \ 322 BIT(3) | BIT(2) | BIT(1) | \ 323 BIT(0)) 324 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_THS_THS 0 325 326 #define LSM9DS0_MFD_REG_INT_GEN_2_DURATION 0x37 327 #define LSM9DS0_MFD_MASK_INT_GEN_2_DURATION_D (BIT(6) | BIT(5) | BIT(4) | \ 328 BIT(3) | BIT(2) | BIT(1) | \ 329 ensor_ BIT(0)) 330 #define LSM9DS0_MFD_SHIFT_INT_GEN_2_DURATION_D 0 331 332 #define LSM9DS0_MFD_REG_CLICK_CFG 0x38 333 #define LSM9DS0_MFD_MASK_CLICK_CFG_ZD BIT(5) 334 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_ZD 5 335 #define LSM9DS0_MFD_MASK_CLICK_CFG_ZS BIT(4) 336 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_ZS 4 337 #define LSM9DS0_MFD_MASK_CLICK_CFG_YD BIT(3) 338 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_YD 3 339 #define LSM9DS0_MFD_MASK_CLICK_CFG_YS BIT(2) 340 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_YS 2 341 #define LSM9DS0_MFD_MASK_CLICK_CFG_XD BIT(1) 342 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_XD 1 343 #define LSM9DS0_MFD_MASK_CLICK_CFG_XS BIT(0) 344 #define LSM9DS0_MFD_SHIFT_CLICK_CFG_XS 0 345 346 #define LSM9DS0_MFD_REG_CLICK_SRC 0x39 347 #define LSM9DS0_MFD_MASK_CLICK_SRC_IA BIT(6) 348 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_IA 6 349 #define LSM9DS0_MFD_MASK_CLICK_SRC_DC BIT(5) 350 #define LMS9DS0_MFD_SHIFT_CLICK_SRC_DC 5 351 #define LSM9DS0_MFD_MASK_CLICK_SRC_SC BIT(4) 352 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_SC 4 353 #define LSM9DS0_MFD_MASK_CLICK_SRC_S BIT(3) 354 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_S 3 355 #define LSM9DS0_MFD_MASK_CLICK_SRC_Z BIT(2) 356 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_Z 2 357 #define LSM9DS0_MFD_MASK_CLICK_SRC_Y BIT(1) 358 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_Y 1 359 #define LSM9DS0_MFD_MASK_CLICK_SRC_X BIT(0) 360 #define LSM9DS0_MFD_SHIFT_CLICK_SRC_X 0 361 362 #define LSM9DS0_MFD_REG_CLICK_THS 0x3A 363 #define LSM9DS0_MFD_MASK_CLICK_THS_THS (BIT(6) | BIT(5) | BIT(4) | \ 364 BIT(3) | BIT(2) | BIT(1) | \ 365 BIT(0)) 366 #define LSM9DS0_MFD_SHIFT_CLICK_THS_THS 0 367 368 #define LSM9DS0_MFD_REG_TIME_LIMIT 0x3B 369 #define LSM9DS0_MFD_MASK_TIME_LIMIT_TLI (BIT(6) | BIT(5) | BIT(4) | \ 370 BIT(3) | BIT(2) | BIT(1) | \ 371 BIT(0)) 372 #define LMS9DS0_MFD_SHIFT_TIME_LIMIT_TLI 0 373 374 #define LSM9DS0_MFD_REG_TIME_LATENCY 0x3C 375 #define LSM9DS0_MFD_MASK_TIME_LATENCY_TLA (BIT(7) | BIT(6) | BIT(5) | \ 376 BIT(4) | BIT(3) | BIT(2) | \ 377 BIT(1) | BIT(0)) 378 #define LSM9DS0_MFD_SHIFT_TIME_LATENCY_TLA 0 379 380 #define LSM9DS0_MFD_REG_TIME_WINDOW 0x3D 381 #define LSM9DS0_MFD_MASK_TIME_WINDOW_TW (BIT(7) | BIT(6) | BIT(5) | \ 382 BIT(4) | BIT(3) | BIT(2) | \ 383 BIT(1) | BIT(0)) 384 #define LSM9DS0_MFD_SHIFT_TIME_WINDOW_TW 0 385 386 #define LSM9DS0_MFD_REG_ACT_THS 0x3E 387 #define LSM9DS0_MFD_MASK_ACT_THS_ACTHS (BIT(6) | BIT(5) | BIT(4) | \ 388 BIT(3) | BIT(2) | BIT(1) | \ 389 BIT(0)) 390 #define LSM9DS0_MFD_SHIFT_ACT_THS_ACTHS 0 391 392 #define LSM9DS0_MFD_REG_ACT_DUR 0x3F 393 #define LSM9DS0_MFD_MASK_ACT_DUR_ACTD (BIT(7) | BIT(6) | BIT(5) | \ 394 BIT(4) | BIT(3) | BIT(2) | \ 395 BIT(1) | BIT(0)) 396 #define LMS9DS0_MFD_SHIFT_ACT_DUR_ACTD 0 397 398 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_0) 399 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 0 400 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_3_125) 401 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 1 402 #define LSM9DS0_MFD_ACCEL_FORCE_MAX_MODR_50 403 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_6_25) 404 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 2 405 #define LSM9DS0_MFD_ACCEL_FORCE_MAX_MODR_50 406 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_12_5) 407 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 3 408 #define LSM9DS0_MFD_ACCEL_FORCE_MAX_MODR_50 409 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_25) 410 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 4 411 #define LSM9DS0_MFD_ACCEL_FORCE_MAX_MODR_50 412 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_50) 413 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 5 414 #define LSM9DS0_MFD_ACCEL_FORCE_MAX_MODR_50 415 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_100) 416 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 6 417 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_200) 418 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 7 419 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_400) 420 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 8 421 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_800) 422 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 9 423 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_1600) 424 #define LSM9DS0_MFD_ACCEL_DEFAULT_AODR 10 425 #endif 426 427 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_2) 428 #define LSM9DS0_MFD_ACCEL_DEFAULT_FS 0 429 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_4) 430 #define LSM9DS0_MFD_ACCEL_DEFAULT_FS 1 431 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_6) 432 #define LSM9DS0_MFD_ACCEL_DEFAULT_FS 2 433 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_8) 434 #define LSM9DS0_MFD_ACCEL_DEFAULT_FS 3 435 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_16) 436 #define LSM9DS0_MFD_ACCEL_DEFAULT_FS 4 437 #endif 438 439 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_X) 440 #define LSM9DS0_MFD_ACCEL_ENABLE_X 1 441 #else 442 #define LSM9DS0_MFD_ACCEL_ENABLE_X 0 443 #endif 444 445 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Y) 446 #define LSM9DS0_MFD_ACCEL_ENABLE_Y 1 447 #else 448 #define LSM9DS0_MFD_ACCEL_ENABLE_Y 0 449 #endif 450 451 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Z) 452 #define LSM9DS0_MFD_ACCEL_ENABLE_Z 1 453 #else 454 #define LSM9DS0_MFD_ACCEL_ENABLE_Z 0 455 #endif 456 457 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_RUNTIME) || \ 458 defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_RUNTIME) 459 #define LSM9DS0_MFD_ATTR_SET_ACCEL 460 #endif 461 462 #if defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_3_125) 463 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 0 464 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_6_25) 465 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 1 466 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_12_5) 467 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 2 468 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_25) 469 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 3 470 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_50) 471 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 4 472 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_100) 473 #if defined(LSM9DS0_MFD_ACCEL_FORCE_MAX_MODR_50) 474 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 4 475 #else 476 #define LSM9DS0_MFD_MAGN_DEFAULT_M_ODR 5 477 #endif 478 #endif 479 480 #if defined(CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_2) 481 #define LSM9DS0_MFD_MAGN_DEFAULT_FS 0 482 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_4) 483 #define LSM9DS0_MFD_MAGN_DEFAULT_FS 1 484 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_8) 485 #define LSM9DS0_MFD_MAGN_DEFAULT_FS 2 486 #elif defined(CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_12) 487 #define LSM9DS0_MFD_MAGN_DEFAULT_FS 3 488 #endif 489 490 #if defined(CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_RUNTIME) || \ 491 defined(CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_RUNTIME) 492 #define LSM9DS0_MFD_ATTR_SET_MAGN 493 #endif 494 495 #if !defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_X) && \ 496 !defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Y) && \ 497 !defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Z) 498 #define LSM9DS0_MFD_ACCEL_DISABLED 499 #elif defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_0) && \ 500 !defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_RUNTIME) 501 #define LSM9DS0_MFD_ACCEL_DISABLED 502 #elif !defined(CONFIG_LSM9DS0_MFD_ACCEL_ENABLE) 503 #define LSM9DS0_MFD_ACCEL_DISABLED 504 #endif 505 506 #if !defined(CONFIG_LSM9DS0_MFD_MAGN_ENABLE) 507 #define LSM9DS0_MFD_MAGN_DISABLED 508 #endif 509 510 #if !defined(CONFIG_LSM9DS0_MFD_TEMP_ENABLE) 511 #define LSM9DS0_MFD_TEMP_DISABLED 512 #endif 513 514 #if defined(LSM9DS0_MFD_ATTR_SET_ACCEL) && defined(LSM9DS0_MFD_ACCEL_DISABLED) 515 #undef LSM9DS0_MFD_ATTR_SET_ACCEL 516 #endif 517 518 #if defined(LSM9DS0_MFD_ATTR_SET_MAGN) && defined(LSM9DS0_MFD_MAGN_DISABLED) 519 #undef LSM9DS0_MFD_ATTR_SET_MAGN 520 #endif 521 522 #if defined(LSM9DS0_MFD_ATTR_SET_ACCEL) || defined(LSM9DS0_MFD_ATTR_SET_MAGN) 523 #define LSM9DS0_MFD_ATTR_SET 524 #endif 525 526 struct lsm9ds0_mfd_config { 527 struct i2c_dt_spec i2c; 528 }; 529 530 struct lsm9ds0_mfd_data { 531 #if !defined(LSM9DS0_MFD_ACCEL_DISABLED) 532 int sample_accel_x, sample_accel_y, sample_accel_z; 533 #endif 534 535 #if !defined(LSM9DS0_MFD_MAGN_DISABLED) 536 int sample_magn_x, sample_magn_y, sample_magn_z; 537 #endif 538 539 #if !defined(LSM9DS0_MFD_TEMP_DISABLED) 540 int sample_temp; 541 #endif 542 543 #if defined(CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_RUNTIME) 544 #if !defined(LSM9DS0_MFD_ACCEL_DISABLED) 545 uint8_t accel_fs, sample_accel_fs; 546 #endif 547 #endif 548 549 #if defined(CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_RUNTIME) 550 #if !defined(LSM9DS0_MFD_MAGN_DISABLED) 551 uint8_t magn_fs, sample_magn_fs; 552 #endif 553 #endif 554 }; 555 556 #endif /* ZEPHYR_DRIVERS_SENSOR_LSM9DS0_MFD_LSM9DS0_MFD_H_ */ 557
