1 /* 2 * Copyright (c) 2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 /** 9 * \file sam_reg_map.h 10 * \brief Register map of Arm Security Alarm Manager (SAM). 11 */ 12 13 #ifndef __SAM_REG_MAP_H__ 14 #define __SAM_REG_MAP_H__ 15 16 #include <stdint.h> 17 #include "tfm_hal_device_header.h" 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 /** 23 * \brief SAM register map. 24 */ 25 struct sam_reg_map_t { 26 __IM uint32_t sambc; 27 /**< Offset: 0x000 (R/ ) SAM Build Configuration register */ 28 __IM uint32_t sames[2]; 29 /**< Offset: 0x004 (R/ ) SAM Event Status registers */ 30 __OM uint32_t samecl[2]; 31 /**< Offset: 0x00C ( /W) SAM Event Clear registers */ 32 __IOM uint32_t samem[2]; 33 /**< Offset: 0x014 (R/W) SAM Export Mask registers */ 34 __IOM uint32_t samim[2]; 35 /**< Offset: 0x01C (R/W) SAM Input Mask registers */ 36 __IOM uint32_t samrrls[8]; 37 /**< Offset: 0x024 (R/W) SAM Response Routing Logic Setup registers */ 38 __IOM uint32_t samec[8]; 39 /**< Offset: 0x044 (R/W) SAM Event Counter registers */ 40 __IOM uint32_t samectiv; 41 /**< Offset: 0x064 (R/W) SAM Event Counters Timer Initial Value register */ 42 __IOM uint32_t samwdciv; 43 /**< Offset: 0x068 (R/W) SAM Watchdog Counter Initial Value register */ 44 __IOM uint32_t samrl; 45 /**< Offset: 0x06C (R/W) SAM Registers Lock register */ 46 __IOM uint32_t samicv; 47 /**< Offset: 0x070 (R/W) SAM Integrity Check Value register */ 48 __IOM uint32_t samcdres; 49 /**< Offset: 0x074 (R/W) SAM Processor DCLS Reported Errors Status registers */ 50 __IOM uint32_t samrres[3]; 51 /**< Offset: 0x078 (R/W) SAM Processor RAS Reported Errors Status registers */ 52 __IOM uint32_t vmpwca[4]; 53 /**< Offset: 0x084 (R/W) VM<n> Partial Write Captured Address registers */ 54 __IOM uint32_t vmsceeca[4]; 55 /**< Offset: 0x094 (R/W) VM<n> Single Corrected ECC Error Captured Address registers */ 56 __IOM uint32_t vmdueeca[4]; 57 /**< Offset: 0x0A4 (R/W) VM<n> Double Uncorrected ECC Error Captured Address registers */ 58 __IOM uint32_t tramsceeca; 59 /**< Offset: 0x0B4 (R/W) TRAM Single Corrected ECC Error Captured Address register */ 60 __IOM uint32_t tramdueeca; 61 /**< Offset: 0x0B8 (R/W) TRAM Double Uncorrected ECC Error Captured Address register */ 62 const volatile uint32_t _reserved0[0x3C5]; 63 /**< Offset: 0x0BC (RAZ/WI) Reserved */ 64 __IM uint32_t pidr4; 65 /**< Offset: 0xFD0 (R/ ) Peripheral ID 4 register */ 66 const volatile uint32_t _reserved1[0x3]; 67 /**< Offset: 0xFD4 (RAZ/WI) Reserved */ 68 __IM uint32_t pidr[4]; 69 /**< Offset: 0xFE0 (R/ ) Peripheral ID 0-3 registers */ 70 __IM uint32_t cidr[4]; 71 /**< Offset: 0xFF0 (R/ ) Component ID 0-3 registers */ 72 }; 73 #ifdef __cplusplus 74 } 75 #endif 76 77 #endif /* __SAM_REG_MAP_H__ */ 78
