1 /*
2 * Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT atmel_sam0_eic
8
9 #include <zephyr/device.h>
10 #include <zephyr/irq.h>
11 #include <soc.h>
12 #include <zephyr/drivers/interrupt_controller/sam0_eic.h>
13 #include "intc_sam0_eic_priv.h"
14
15 struct sam0_eic_line_assignment {
16 uint8_t pin : 5;
17 uint8_t port : 2;
18 uint8_t enabled : 1;
19 };
20
21 struct sam0_eic_port_data {
22 sam0_eic_callback_t cb;
23 void *data;
24 };
25
26 struct sam0_eic_data {
27 struct sam0_eic_port_data ports[PORT_GROUPS];
28 struct sam0_eic_line_assignment lines[EIC_EXTINT_NUM];
29 };
30
wait_synchronization(void)31 static void wait_synchronization(void)
32 {
33 #ifdef REG_EIC_SYNCBUSY
34 while (EIC->SYNCBUSY.reg) {
35 }
36 #else
37 while (EIC->STATUS.bit.SYNCBUSY) {
38 }
39 #endif
40 }
41
set_eic_enable(bool on)42 static inline void set_eic_enable(bool on)
43 {
44 #ifdef REG_EIC_CTRLA
45 EIC->CTRLA.bit.ENABLE = on;
46 #else
47 EIC->CTRL.bit.ENABLE = on;
48 #endif
49 }
50
sam0_eic_isr(const struct device * dev)51 static void sam0_eic_isr(const struct device *dev)
52 {
53 struct sam0_eic_data *const dev_data = dev->data;
54 uint16_t bits = EIC->INTFLAG.reg;
55 uint32_t line_index;
56
57 /* Acknowledge all interrupts */
58 EIC->INTFLAG.reg = bits;
59
60 /* No clz on M0, so just do a quick test */
61 #if __CORTEX_M >= 3
62 line_index = __CLZ(__RBIT(bits));
63 bits >>= line_index;
64 #else
65 if (bits & 0xFF) {
66 line_index = 0;
67 } else {
68 line_index = 8;
69 bits >>= 8;
70 }
71 #endif
72
73 /*
74 * Map the EIC lines to the port pin masks based on which port is
75 * selected in the line data.
76 */
77 for (; bits; bits >>= 1, line_index++) {
78 if (!(bits & 1)) {
79 continue;
80 }
81
82 /*
83 * These could be aggregated together into one call, but
84 * usually on a single one will be set, so just call them
85 * one by one.
86 */
87 struct sam0_eic_line_assignment *line_assignment =
88 &dev_data->lines[line_index];
89 struct sam0_eic_port_data *port_data =
90 &dev_data->ports[line_assignment->port];
91
92 port_data->cb(BIT(line_assignment->pin), port_data->data);
93 }
94 }
95
sam0_eic_acquire(int port,int pin,enum sam0_eic_trigger trigger,bool filter,sam0_eic_callback_t cb,void * data)96 int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
97 bool filter, sam0_eic_callback_t cb, void *data)
98 {
99 const struct device *const dev = DEVICE_DT_INST_GET(0);
100 struct sam0_eic_data *dev_data = dev->data;
101 struct sam0_eic_port_data *port_data;
102 struct sam0_eic_line_assignment *line_assignment;
103 uint32_t mask;
104 int line_index;
105 int config_index;
106 int config_shift;
107 unsigned int key;
108 uint32_t config;
109
110 line_index = sam0_eic_map_to_line(port, pin);
111 if (line_index < 0) {
112 return line_index;
113 }
114
115 mask = BIT(line_index);
116 config_index = line_index / 8;
117 config_shift = (line_index % 8) * 4;
118
119 /* Lock everything so it's safe to reconfigure */
120 key = irq_lock();
121 /* Disable the EIC for reconfiguration */
122 set_eic_enable(0);
123
124 line_assignment = &dev_data->lines[line_index];
125
126 /* Check that the required line is available */
127 if (line_assignment->enabled) {
128 if (line_assignment->port != port ||
129 line_assignment->pin != pin) {
130 goto err_in_use;
131 }
132 }
133
134 /* Set the EIC configuration data */
135 port_data = &dev_data->ports[port];
136 port_data->cb = cb;
137 port_data->data = data;
138 line_assignment->pin = pin;
139 line_assignment->port = port;
140 line_assignment->enabled = 1;
141
142 config = EIC->CONFIG[config_index].reg;
143 config &= ~(0xF << config_shift);
144 switch (trigger) {
145 case SAM0_EIC_RISING:
146 config |= EIC_CONFIG_SENSE0_RISE << config_shift;
147 break;
148 case SAM0_EIC_FALLING:
149 config |= EIC_CONFIG_SENSE0_FALL << config_shift;
150 break;
151 case SAM0_EIC_BOTH:
152 config |= EIC_CONFIG_SENSE0_BOTH << config_shift;
153 break;
154 case SAM0_EIC_HIGH:
155 config |= EIC_CONFIG_SENSE0_HIGH << config_shift;
156 break;
157 case SAM0_EIC_LOW:
158 config |= EIC_CONFIG_SENSE0_LOW << config_shift;
159 break;
160 }
161
162 if (filter) {
163 config |= EIC_CONFIG_FILTEN0 << config_shift;
164 }
165
166 /* Apply the config to the EIC itself */
167 EIC->CONFIG[config_index].reg = config;
168
169 set_eic_enable(1);
170 wait_synchronization();
171 /*
172 * Errata: The EIC generates a spurious interrupt for the newly
173 * enabled pin after being enabled, so clear it before re-enabling
174 * the IRQ.
175 */
176 EIC->INTFLAG.reg = mask;
177 irq_unlock(key);
178 return 0;
179
180 err_in_use:
181 set_eic_enable(1);
182 wait_synchronization();
183 irq_unlock(key);
184 return -EBUSY;
185 }
186
sam0_eic_check_ownership(int port,int pin,int line_index)187 static bool sam0_eic_check_ownership(int port, int pin, int line_index)
188 {
189 const struct device *const dev = DEVICE_DT_INST_GET(0);
190 struct sam0_eic_data *dev_data = dev->data;
191 struct sam0_eic_line_assignment *line_assignment =
192 &dev_data->lines[line_index];
193
194 if (!line_assignment->enabled) {
195 return false;
196 }
197
198 if (line_assignment->port != port ||
199 line_assignment->pin != pin) {
200 return false;
201 }
202
203 return true;
204 }
205
sam0_eic_release(int port,int pin)206 int sam0_eic_release(int port, int pin)
207 {
208 const struct device *const dev = DEVICE_DT_INST_GET(0);
209 struct sam0_eic_data *dev_data = dev->data;
210 uint32_t mask;
211 int line_index;
212 int config_index;
213 int config_shift;
214 unsigned int key;
215
216 line_index = sam0_eic_map_to_line(port, pin);
217 if (line_index < 0) {
218 return line_index;
219 }
220
221 mask = BIT(line_index);
222 config_index = line_index / 8;
223 config_shift = (line_index % 8) * 4;
224
225 /* Lock everything so it's safe to reconfigure */
226 key = irq_lock();
227 /* Disable the EIC */
228 set_eic_enable(0);
229 wait_synchronization();
230
231 /*
232 * Check to make sure the requesting actually owns the line and do
233 * nothing if it does not.
234 */
235 if (!sam0_eic_check_ownership(port, pin, line_index)) {
236 goto done;
237 }
238
239 dev_data->lines[line_index].enabled = 0;
240
241 /* Clear the EIC config, including the trigger condition */
242 EIC->CONFIG[config_index].reg &= ~(0xF << config_shift);
243
244 /* Clear any pending interrupt for it */
245 EIC->INTENCLR.reg = mask;
246 EIC->INTFLAG.reg = mask;
247
248 done:
249 set_eic_enable(1);
250 wait_synchronization();
251 irq_unlock(key);
252 return 0;
253 }
254
sam0_eic_enable_interrupt(int port,int pin)255 int sam0_eic_enable_interrupt(int port, int pin)
256 {
257 uint32_t mask;
258 int line_index;
259
260 line_index = sam0_eic_map_to_line(port, pin);
261 if (line_index < 0) {
262 return line_index;
263 }
264
265 if (!sam0_eic_check_ownership(port, pin, line_index)) {
266 return -EBUSY;
267 }
268
269 mask = BIT(line_index);
270 EIC->INTFLAG.reg = mask;
271 EIC->INTENSET.reg = mask;
272
273 return 0;
274 }
275
sam0_eic_disable_interrupt(int port,int pin)276 int sam0_eic_disable_interrupt(int port, int pin)
277 {
278 uint32_t mask;
279 int line_index;
280
281 line_index = sam0_eic_map_to_line(port, pin);
282 if (line_index < 0) {
283 return line_index;
284 }
285
286 if (!sam0_eic_check_ownership(port, pin, line_index)) {
287 return -EBUSY;
288 }
289
290 mask = BIT(line_index);
291 EIC->INTENCLR.reg = mask;
292 EIC->INTFLAG.reg = mask;
293
294 return 0;
295 }
296
sam0_eic_interrupt_pending(int port)297 uint32_t sam0_eic_interrupt_pending(int port)
298 {
299 const struct device *const dev = DEVICE_DT_INST_GET(0);
300 struct sam0_eic_data *dev_data = dev->data;
301 struct sam0_eic_line_assignment *line_assignment;
302 uint32_t set = EIC->INTFLAG.reg;
303 uint32_t mask = 0;
304
305 for (int line_index = 0; line_index < EIC_EXTINT_NUM; line_index++) {
306 line_assignment = &dev_data->lines[line_index];
307
308 if (!line_assignment->enabled) {
309 continue;
310 }
311
312 if (line_assignment->port != port) {
313 continue;
314 }
315
316 if (!(set & BIT(line_index))) {
317 continue;
318 }
319
320 mask |= BIT(line_assignment->pin);
321 }
322
323 return mask;
324 }
325
326
327 #define SAM0_EIC_IRQ_CONNECT(n) \
328 do { \
329 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, n, irq), \
330 DT_INST_IRQ_BY_IDX(0, n, priority), \
331 sam0_eic_isr, DEVICE_DT_INST_GET(0), 0); \
332 irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
333 } while (false)
334
sam0_eic_init(const struct device * dev)335 static int sam0_eic_init(const struct device *dev)
336 {
337 ARG_UNUSED(dev);
338
339 #ifdef MCLK
340 /* Enable the EIC clock in APBAMASK */
341 MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
342
343 /* Enable the GCLK */
344 GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0 |
345 GCLK_PCHCTRL_CHEN;
346 #else
347 /* Enable the EIC clock in PM */
348 PM->APBAMASK.bit.EIC_ = 1;
349
350 /* Enable the GCLK */
351 GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 |
352 GCLK_CLKCTRL_CLKEN;
353 #endif
354
355 #if DT_INST_IRQ_HAS_CELL(0, irq)
356 SAM0_EIC_IRQ_CONNECT(0);
357 #endif
358 #if DT_INST_IRQ_HAS_IDX(0, 1)
359 SAM0_EIC_IRQ_CONNECT(1);
360 #endif
361 #if DT_INST_IRQ_HAS_IDX(0, 2)
362 SAM0_EIC_IRQ_CONNECT(2);
363 #endif
364 #if DT_INST_IRQ_HAS_IDX(0, 3)
365 SAM0_EIC_IRQ_CONNECT(3);
366 #endif
367 #if DT_INST_IRQ_HAS_IDX(0, 4)
368 SAM0_EIC_IRQ_CONNECT(4);
369 #endif
370 #if DT_INST_IRQ_HAS_IDX(0, 5)
371 SAM0_EIC_IRQ_CONNECT(5);
372 #endif
373 #if DT_INST_IRQ_HAS_IDX(0, 6)
374 SAM0_EIC_IRQ_CONNECT(6);
375 #endif
376 #if DT_INST_IRQ_HAS_IDX(0, 7)
377 SAM0_EIC_IRQ_CONNECT(7);
378 #endif
379 #if DT_INST_IRQ_HAS_IDX(0, 8)
380 SAM0_EIC_IRQ_CONNECT(8);
381 #endif
382 #if DT_INST_IRQ_HAS_IDX(0, 9)
383 SAM0_EIC_IRQ_CONNECT(9);
384 #endif
385 #if DT_INST_IRQ_HAS_IDX(0, 10)
386 SAM0_EIC_IRQ_CONNECT(10);
387 #endif
388 #if DT_INST_IRQ_HAS_IDX(0, 11)
389 SAM0_EIC_IRQ_CONNECT(11);
390 #endif
391 #if DT_INST_IRQ_HAS_IDX(0, 12)
392 SAM0_EIC_IRQ_CONNECT(12);
393 #endif
394 #if DT_INST_IRQ_HAS_IDX(0, 13)
395 SAM0_EIC_IRQ_CONNECT(13);
396 #endif
397 #if DT_INST_IRQ_HAS_IDX(0, 14)
398 SAM0_EIC_IRQ_CONNECT(14);
399 #endif
400 #if DT_INST_IRQ_HAS_IDX(0, 15)
401 SAM0_EIC_IRQ_CONNECT(15);
402 #endif
403
404 set_eic_enable(1);
405 wait_synchronization();
406
407 return 0;
408 }
409
410 static struct sam0_eic_data eic_data;
411 DEVICE_DT_INST_DEFINE(0, sam0_eic_init,
412 NULL, &eic_data, NULL,
413 PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
414 NULL);
415
