1  /*
2   * Copyright (c) 2015, Freescale Semiconductor, Inc.
3   * Copyright 2016-2017 NXP.
4   *
5   * Redistribution and use in source and binary forms, with or without modification,
6   * are permitted provided that the following conditions are met:
7   *
8   * o Redistributions of source code must retain the above copyright notice, this list
9   *   of conditions and the following disclaimer.
10   *
11   * o Redistributions in binary form must reproduce the above copyright notice, this
12   *   list of conditions and the following disclaimer in the documentation and/or
13   *   other materials provided with the distribution.
14   *
15   * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16   *   contributors may be used to endorse or promote products derived from this
17   *   software without specific prior written permission.
18   *
19   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20   * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21   * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23   * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24   * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25   * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26   * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28   * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29   */
30  #ifndef _FSL_XCVR_H_
31  /* clang-format off */
32  #define _FSL_XCVR_H_
33  /* clang-format on */
34  
35  #include "fsl_device_registers.h"
36  #include "fsl_xcvr_trim.h"
37  
38  #if gMWS_UseCoexistence_d
39  #include "MWS.h"
40  #endif /* gMWS_UseCoexistence_d */
41  /*!
42   * @addtogroup xcvr
43   * @{
44   */
45  
46  /*! @file*/
47  
48  /*******************************************************************************
49   * Definitions
50   ******************************************************************************/
51  /* KW4xZ/KW3xZ/KW2xZ Radio type */
52  #define RADIO_IS_GEN_2P0  (1)
53  
54  /* Default RF OSC definition. Allows for compile time clock frequency definition */
55  #ifdef CLOCK_MAIN
56  
57  #else
58  #if RF_OSC_26MHZ == 1
59  #define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */
60  #else
61  #define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */
62  #endif /* RF_OSC_26MHZ == 1 */
63  #endif /* CLOCK_MAIN */
64  
65  #define TBD_ZERO                (0)
66  #define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0))
67  
68  #define B0(x)   (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU)
69  #define B1(x)   (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U)
70  #define B2(x)   (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U)
71  #define B3(x)   (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U)
72  
73  #define USE_DEFAULT_PRE_REF             (0)
74  #define TRIM_BBA_DCOC_DAC_AT_INIT       (1)
75  #define PRESLOW_ENA                     (1)
76  
77  /* GEN3 TSM defines */
78  #if RADIO_IS_GEN_3P0
79  
80  /* TSM timings initializations for Gen3 radio */
81  /* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */
82  /* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */
83  /* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */
84  #if RF_OSC_26MHZ == 1
85  #define TSM_TIMING00init  (0x6d006f00U) /* (bb_ldo_hf_en) */
86  #define TSM_TIMING01init  (0x6d006f00U) /* (bb_ldo_adcdac_en) */
87  #define TSM_TIMING02init  (0x6d00ffffU) /* (bb_ldo_bba_en) */
88  #define TSM_TIMING03init  (0x6d006f00U) /* (bb_ldo_pd_en) */
89  #define TSM_TIMING04init  (0x6d006f00U) /* (bb_ldo_fdbk_en) */
90  #define TSM_TIMING05init  (0x6d006f00U) /* (bb_ldo_vcolo_en) */
91  #define TSM_TIMING06init  (0x6d006f00U) /* (bb_ldo_vtref_en) */
92  #define TSM_TIMING07init  (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */
93  #define TSM_TIMING08init  (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */
94  #define TSM_TIMING09init  (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */
95  #define TSM_TIMING10init  (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */
96  #define TSM_TIMING11init  (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */
97  #define TSM_TIMING12init  (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */
98  #define TSM_TIMING13init  (0x18004c00U) /* (sy_vco_autotune_en) */
99  #define TSM_TIMING14init  (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */
100  #define TSM_TIMING15init  (0x6d036f03U) /* (sy_vco_en) */
101  #define TSM_TIMING16init  (0x6d20ffffU) /* (sy_lo_rx_buf_en) */
102  #define TSM_TIMING17init  (0xffff6f58U) /* (sy_lo_tx_buf_en) */
103  #define TSM_TIMING18init  (0x6d056f05U) /* (sy_divn_en) */
104  #define TSM_TIMING19init  (0x18034c03U) /* (sy_pd_filter_charge_en) */
105  #define TSM_TIMING20init  (0x6d036f03U) /* (sy_pd_en) */
106  #define TSM_TIMING21init  (0x6d046f04U) /* (sy_lo_divn_en) */
107  #define TSM_TIMING22init  (0x6d04ffffU) /* (sy_lo_rx_en) */
108  #define TSM_TIMING23init  (0xffff6f04U) /* (sy_lo_tx_en) */
109  #define TSM_TIMING24init  (0x18004c00U) /* (sy_divn_cal_en) */
110  #define TSM_TIMING25init  (0x6d21ffffU) /* (rx_lna_mixer_en) */
111  #define TSM_TIMING26init  (0xffff6e58U) /* (tx_pa_en) */
112  #define TSM_TIMING27init  (0x6d24ffffU) /* (rx_adc_i_q_en) */
113  #define TSM_TIMING28init  (0x2524ffffU) /* (rx_adc_reset_en) */
114  #define TSM_TIMING29init  (0x6d22ffffU) /* (rx_bba_i_q_en) */
115  #define TSM_TIMING30init  (0x6d24ffffU) /* (rx_bba_pdet_en) */
116  #define TSM_TIMING31init  (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */
117  #define TSM_TIMING32init  (0x6d21ffffU) /* (rx_tza_i_q_en) */
118  #define TSM_TIMING33init  (0x6d24ffffU) /* (rx_tza_pdet_en) */
119  #define TSM_TIMING34init  (0x6d076f07U) /* (pll_dig_en) */
120  #define TSM_TIMING35init  (0xffff6f5fU) /* (tx_dig_en) */
121  #define TSM_TIMING36init  (0x6d6affffU) /* (rx_dig_en) */
122  #define TSM_TIMING37init  (0x6b6affffU) /* (rx_init) */
123  #define TSM_TIMING38init  (0x6d0e6f42U) /* (sigma_delta_en) */
124  #define TSM_TIMING39init  (0x6d6affffU) /* (rx_phy_en) */
125  #define TSM_TIMING40init  (0x6d2affffU) /* (dcoc_en) */
126  #define TSM_TIMING41init  (0x2b2affffU) /* (dcoc_init) */
127  #define TSM_TIMING42init  (0xffffffffU) /* (sar_adc_trig_en) */
128  #define TSM_TIMING43init  (0xffffffffU) /* (tsm_spare0_en) */
129  #define TSM_TIMING44init  (0xffffffffU) /* (tsm_spare1_en) */
130  #define TSM_TIMING45init  (0xffffffffU) /* (tsm_spare2_en) */
131  #define TSM_TIMING46init  (0xffffffffU) /* (tsm_spare3_en) */
132  #define TSM_TIMING47init  (0xffffffffU) /* (gpio0_trig_en) */
133  #define TSM_TIMING48init  (0xffffffffU) /* (gpio1_trig_en) */
134  #define TSM_TIMING49init  (0xffffffffU) /* (gpio2_trig_en) */
135  #define TSM_TIMING50init  (0xffffffffU) /* (gpio3_trig_en) */
136  #define TSM_TIMING51init  (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */
137  #define TSM_TIMING52init  (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */
138  #define TSM_TIMING53init  (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */
139  #define TSM_TIMING54init  (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */
140  #define TSM_TIMING55init  (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */
141  #define TSM_TIMING56init  (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */
142  #define TSM_TIMING57init  (0x1a03ffffU) /* (rxtx_rccal_en) */
143  #define TSM_TIMING58init  (0xffff6f03U) /* (tx_hpm_dac_en) */
144  #define END_OF_SEQinit    (0x6d6c6f67U) /*  */
145  #define TX_RX_ON_DELinit  (0x00008a86U) /*  */
146  #define TX_RX_SYNTH_init  (0x00002318U) /*  */
147  #else
148  #define TSM_TIMING00init  (0x69006f00U) /* (bb_ldo_hf_en) */
149  #define TSM_TIMING01init  (0x69006f00U) /* (bb_ldo_adcdac_en) */
150  #define TSM_TIMING02init  (0x6900ffffU) /* (bb_ldo_bba_en) */
151  #define TSM_TIMING03init  (0x69006f00U) /* (bb_ldo_pd_en) */
152  #define TSM_TIMING04init  (0x69006f00U) /* (bb_ldo_fdbk_en) */
153  #define TSM_TIMING05init  (0x69006f00U) /* (bb_ldo_vcolo_en) */
154  #define TSM_TIMING06init  (0x69006f00U) /* (bb_ldo_vtref_en) */
155  #define TSM_TIMING07init  (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */
156  #define TSM_TIMING08init  (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */
157  #define TSM_TIMING09init  (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */
158  #define TSM_TIMING10init  (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */
159  #define TSM_TIMING11init  (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */
160  #define TSM_TIMING12init  (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */
161  #define TSM_TIMING13init  (0x18004c00U) /* (sy_vco_autotune_en) */
162  #define TSM_TIMING14init  (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */
163  #define TSM_TIMING15init  (0x69036f03U) /* (sy_vco_en) */
164  #define TSM_TIMING16init  (0x691cffffU) /* (sy_lo_rx_buf_en) */
165  #define TSM_TIMING17init  (0xffff6f58U) /* (sy_lo_tx_buf_en) */
166  #define TSM_TIMING18init  (0x69056f05U) /* (sy_divn_en) */
167  #define TSM_TIMING19init  (0x18034c03U) /* (sy_pd_filter_charge_en) */
168  #define TSM_TIMING20init  (0x69036f03U) /* (sy_pd_en) */
169  #define TSM_TIMING21init  (0x69046f04U) /* (sy_lo_divn_en) */
170  #define TSM_TIMING22init  (0x6904ffffU) /* (sy_lo_rx_en) */
171  #define TSM_TIMING23init  (0xffff6f04U) /* (sy_lo_tx_en) */
172  #define TSM_TIMING24init  (0x18004c00U) /* (sy_divn_cal_en) */
173  #define TSM_TIMING25init  (0x691dffffU) /* (rx_lna_mixer_en) */
174  #define TSM_TIMING26init  (0xffff6e58U) /* (tx_pa_en) */
175  #define TSM_TIMING27init  (0x6920ffffU) /* (rx_adc_i_q_en) */
176  #define TSM_TIMING28init  (0x2120ffffU) /* (rx_adc_reset_en) */
177  #define TSM_TIMING29init  (0x691effffU) /* (rx_bba_i_q_en) */
178  #define TSM_TIMING30init  (0x6920ffffU) /* (rx_bba_pdet_en) */
179  #define TSM_TIMING31init  (0x691fffffU) /* (rx_bba_tza_dcoc_en) */
180  #define TSM_TIMING32init  (0x691dffffU) /* (rx_tza_i_q_en) */
181  #define TSM_TIMING33init  (0x6920ffffU) /* (rx_tza_pdet_en) */
182  #define TSM_TIMING34init  (0x69076f07U) /* (pll_dig_en) */
183  #define TSM_TIMING35init  (0xffff6f5fU) /* (tx_dig_en) */
184  #define TSM_TIMING36init  (0x6966ffffU) /* (rx_dig_en) */
185  #define TSM_TIMING37init  (0x6766ffffU) /* (rx_init) */
186  #define TSM_TIMING38init  (0x690e6f42U) /* (sigma_delta_en) */
187  #define TSM_TIMING39init  (0x6966ffffU) /* (rx_phy_en) */
188  #define TSM_TIMING40init  (0x6926ffffU) /* (dcoc_en) */
189  #define TSM_TIMING41init  (0x2726ffffU) /* (dcoc_init) */
190  #define TSM_TIMING42init  (0xffffffffU) /* (sar_adc_trig_en) */
191  #define TSM_TIMING43init  (0xffffffffU) /* (tsm_spare0_en) */
192  #define TSM_TIMING44init  (0xffffffffU) /* (tsm_spare1_en) */
193  #define TSM_TIMING45init  (0xffffffffU) /* (tsm_spare2_en) */
194  #define TSM_TIMING46init  (0xffffffffU) /* (tsm_spare3_en) */
195  #define TSM_TIMING47init  (0xffffffffU) /* (gpio0_trig_en) */
196  #define TSM_TIMING48init  (0xffffffffU) /* (gpio1_trig_en) */
197  #define TSM_TIMING49init  (0xffffffffU) /* (gpio2_trig_en) */
198  #define TSM_TIMING50init  (0xffffffffU) /* (gpio3_trig_en) */
199  #define TSM_TIMING51init  (0x6903ffffU) /* (rxtx_auxpll_bias_en) */
200  #define TSM_TIMING52init  (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */
201  #define TSM_TIMING53init  (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */
202  #define TSM_TIMING54init  (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */
203  #define TSM_TIMING55init  (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */
204  #define TSM_TIMING56init  (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */
205  #define TSM_TIMING57init  (0x1a03ffffU) /* (rxtx_rccal_en) */
206  #define TSM_TIMING58init  (0xffff6f03U) /* (tx_hpm_dac_en) */
207  #define END_OF_SEQinit    (0x69686f67U) /*  */
208  #define TX_RX_ON_DELinit  (0x00008a86U) /*  */
209  #define TX_RX_SYNTH_init  (0x00002318U) /*  */
210  #endif /* RF_OSC_26MHZ == 1 */
211  
212  #define AUX_PLL_DELAY       (0)
213  /* TSM bitfield shift and value definitions */
214  #define TX_DIG_EN_ASSERT    (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */
215  #define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */
216  /* EDIT THIS LINE TO CONTROL PA_RAMP! */
217  #define PA_RAMP_TIME        (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */
218  #define PA_RAMP_SEL_0US     (0)
219  #define PA_RAMP_SEL_1US     (1)
220  #define PA_RAMP_SEL_2US     (2)
221  #define PA_RAMP_SEL_4US     (3)
222  #if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4))
223  #error "Invalid value for PA_RAMP_TIME macro"
224  #endif /* Error check of PA RAMP TIME */
225  
226  #define ADD_FOR_26MHZ           (4)
227  #define END_OF_TX_WU_NORAMP     (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
228  #define END_OF_TX_WD_NORAMP     (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
229  /* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */
230  /* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */
231  #if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2))
232      #define END_OF_TX_WU   (END_OF_TX_WU_NORAMP)
233      #define END_OF_TX_WD   (END_OF_TX_WD_NORAMP)
234      #if (PA_RAMP_TIME == 0)
235          #define PA_RAMP_SEL PA_RAMP_SEL_0US
236          #define DATA_PADDING_EN (0)
237      #else
238          #define DATA_PADDING_EN (1)
239          #if (PA_RAMP_TIME == 1)
240              #define PA_RAMP_SEL PA_RAMP_SEL_1US
241          #else
242              #define PA_RAMP_SEL PA_RAMP_SEL_2US
243          #endif /* (PA_RAMP_TIME == 1) */
244      #endif /* (PA_RAMP_TIME == 0) */
245  #else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */
246      #if (PA_RAMP_TIME == 4)
247          #define END_OF_TX_WU    (END_OF_TX_WU_NORAMP + 2)
248          #define END_OF_TX_WD    (END_OF_TX_WD_NORAMP + 4)
249          #define PA_RAMP_SEL PA_RAMP_SEL_4US
250          #define DATA_PADDING_EN (1)
251      #else /* (PA_RAMP_TIME == 4) */
252          #error "Invalid value for PA_RAMP_TIME macro"
253      #endif /* (PA_RAMP_TIME == 4) */
254  #endif/* (PA_RAMP_TIME == 4) */
255  
256  #define END_OF_RX_WU    (104 + AUX_PLL_DELAY)
257  
258  #if RF_OSC_26MHZ == 1
259  #define END_OF_RX_WD    (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */
260  #else
261  #define END_OF_RX_WD    (END_OF_RX_WU + 1)
262  #endif /* RF_OSC_26MHZ == 1 */
263  
264  #define END_OF_RX_WU_26MHZ  (END_OF_RX_WU + ADD_FOR_26MHZ)
265  #define END_OF_RX_WD_26MHZ  (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)
266  
267  /* PA Bias Table - Gen3 version */
268  #define PA_RAMP_0 0x1
269  #define PA_RAMP_1 0x2
270  #define PA_RAMP_2 0x4
271  #define PA_RAMP_3 0x6
272  #define PA_RAMP_4 0x8
273  #define PA_RAMP_5 0xc
274  #define PA_RAMP_6 0x10
275  #define PA_RAMP_7 0x14
276  #define PA_RAMP_8 0x18
277  #define PA_RAMP_9 0x1c
278  #define PA_RAMP_10 0x22
279  #define PA_RAMP_11 0x28
280  #define PA_RAMP_12 0x2c
281  #define PA_RAMP_13 0x30
282  #define PA_RAMP_14 0x36
283  #define PA_RAMP_15 0x3c
284  
285  #else /* Gen2 TSM definitions */
286  /* GEN2 TSM defines */
287  #define AUX_PLL_DELAY       (0)
288  /* TSM bitfield shift and value definitions */
289  #define TX_DIG_EN_ASSERT    (95)
290  #define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */
291  /* EDIT THIS LINE TO CONTROL PA_RAMP! */
292  #define PA_RAMP_TIME        (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */
293  #define PA_RAMP_SEL_0US     (0)
294  #define PA_RAMP_SEL_2US     (1)
295  #define PA_RAMP_SEL_4US     (2)
296  #define PA_RAMP_SEL_8US     (3)
297  
298  #if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8))
299  #error "Invalid value for PA_RAMP_TIME macro"
300  #endif /* Error check of PA RAMP TIME */
301  #define ADD_FOR_26MHZ           (4)
302  #define END_OF_TX_WU_NORAMP     (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
303  #define END_OF_TX_WD_NORAMP     (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
304  /* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */
305  /* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */
306  #if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2))
307      #define END_OF_TX_WU   (END_OF_TX_WU_NORAMP)
308      #define END_OF_TX_WD   (END_OF_TX_WD_NORAMP)
309      #define TX_SYNTH_DELAY_ADJ       (0)
310      #define PD_CYCLE_SLIP_TX_HI_ADJ  (0)
311      #define PD_CYCLE_SLIP_TX_LO_ADJ  (1)
312      #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */
313      #if (PA_RAMP_TIME == 0)
314          #define PA_RAMP_SEL PA_RAMP_SEL_0US
315          #define DATA_PADDING_EN     (0)
316          #define TX_DIG_EN_TX_HI_ADJ (-2)
317      #else
318          #define DATA_PADDING_EN     (1)
319          #define TX_DIG_EN_TX_HI_ADJ (0)
320          #define PA_RAMP_SEL PA_RAMP_SEL_2US
321      #endif /* (PA_RAMP_TIME == 0) */
322  #else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */
323      #if (PA_RAMP_TIME == 4)
324          #define END_OF_TX_WU    (END_OF_TX_WU_NORAMP + 2)
325          #define END_OF_TX_WD    (END_OF_TX_WD_NORAMP + 4)
326          #define TX_SYNTH_DELAY_ADJ       (2)
327          #define PD_CYCLE_SLIP_TX_HI_ADJ  (2)
328          #define PD_CYCLE_SLIP_TX_LO_ADJ  (1)
329          #define TX_DIG_EN_TX_HI_ADJ      (0)
330          #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */
331          #define PA_RAMP_SEL PA_RAMP_SEL_4US
332          #define DATA_PADDING_EN (1)
333      #else /* (PA_RAMP_TIME==4) */
334          #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0))
335              #define END_OF_TX_WU    (END_OF_TX_WU_NORAMP + 6)
336              #define END_OF_TX_WD    (END_OF_TX_WD_NORAMP + 12)
337              #define TX_SYNTH_DELAY_ADJ       (6)
338              #define PD_CYCLE_SLIP_TX_HI_ADJ  (6)
339              #define PD_CYCLE_SLIP_TX_LO_ADJ  (1)
340              #define TX_DIG_EN_TX_HI_ADJ      (4)
341              #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */
342              #define PA_RAMP_SEL PA_RAMP_SEL_8US
343              #define DATA_PADDING_EN (1)
344          #else /* (PA_RAMP_TIME == 8) */
345              #error "Invalid value for PA_RAMP_TIME macro"
346          #endif /* (PA_RAMP_TIME == 8) */
347      #endif/* (PA_RAMP_TIME == 4) */
348  #endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */
349  
350  #define TX_DIG_EN_ASSERT_MSK500    (END_OF_TX_WU - 3)
351  
352  #define END_OF_RX_WU    (104 + AUX_PLL_DELAY)
353  #if RF_OSC_26MHZ == 1
354  #define END_OF_RX_WD    (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)  /* Need to handle normal signals extending when 26MHZ warmdown is extended */
355  #else
356  #define END_OF_RX_WD    (END_OF_RX_WU + 1)
357  #endif /* RF_OSC_26MHZ == 1 */
358  #define END_OF_RX_WU_26MHZ  (END_OF_RX_WU + ADD_FOR_26MHZ)
359  #define END_OF_RX_WD_26MHZ  (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)
360  
361  /* PA Bias Table */
362  #define PA_RAMP_0 0x1
363  #define PA_RAMP_1 0x2
364  #define PA_RAMP_2 0x4
365  #define PA_RAMP_3 0x8
366  #define PA_RAMP_4 0xe
367  #define PA_RAMP_5 0x16
368  #define PA_RAMP_6 0x22
369  #define PA_RAMP_7 0x2e
370  
371  /* BLE LL timing definitions */
372  #define TX_ON_DELAY     (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */
373  #define RX_ON_DELAY     (29 + END_OF_RX_WU)
374  #define RX_ON_DELAY_26MHZ     (29 + END_OF_RX_WU_26MHZ)
375  #define TX_RX_ON_DELAY_VAL  (TX_ON_DELAY << 8 | RX_ON_DELAY)
376  #define TX_RX_ON_DELAY_VAL_26MHZ  (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ)
377  #define TX_SYNTH_DELAY  (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */
378  #define RX_SYNTH_DELAY  (0x18)
379  #define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY)
380  
381  /* PHY reference waveform assembly */
382  #define RW0PS(loc, val)      (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */
383  #define RW1PS(loc, val)      (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */
384  #define RW2PS(loc, val)      (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */
385  #endif /* RADIO_IS_GEN_3P0 */
386  
387  /*! @brief  Error codes for the XCVR driver. */
388  typedef enum _xcvrStatus
389  {
390      gXcvrSuccess_c = 0,
391      gXcvrInvalidParameters_c,
392      gXcvrUnsupportedOperation_c,
393      gXcvrTrimFailure_c
394  } xcvrStatus_t;
395  
396  /*! @brief  Health status returned from PHY upon status check function return. */
397  typedef enum _healthStatus
398  {
399      NO_ERRORS = 0,
400      PLL_CTUNE_FAIL = 1,
401      PLL_CYCLE_SLIP_FAIL = 2,
402      PLL_FREQ_TARG_FAIL = 4,
403      PLL_TSM_ABORT_FAIL = 8,
404  } healthStatus_t;
405  
406  /*! @brief  Health status returned from PHY upon status check function return. */
407  typedef enum _ext_clock_config
408  {
409      EXT_CLK_32_MHZ = 0,
410      EXT_CLK_26_MHZ = 1,
411  } ext_clock_config_t;
412  
413  /*! @brief  Radio operating mode setting types. */
414  typedef enum _radio_mode
415  {
416      BLE_MODE = 0,
417      ZIGBEE_MODE = 1,
418      ANT_MODE = 2,
419  
420      /* BT=0.5, h=** */
421      GFSK_BT_0p5_h_0p5  = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */
422      GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/
423      GFSK_BT_0p5_h_0p7  = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */
424      GFSK_BT_0p5_h_1p0  = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */
425  
426      /* BT=** h=0.5 */
427      GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */
428      GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */
429  
430      MSK = 9,
431      NUM_RADIO_MODES = 10,
432  } radio_mode_t;
433  
434  /*! @brief  Link layer types. */
435  typedef enum _link_layer
436  {
437      BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */
438      ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */
439      ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */
440      GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */
441      UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */
442  } link_layer_t;
443  
444  /*! @brief  Data rate selections. */
445  typedef enum _data_rate
446  {
447      DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */
448      DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */
449      DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */
450  #if RADIO_IS_GEN_3P0
451      DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */
452  #endif /* RADIO_IS_GEN_3P0 */
453      DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */
454  } data_rate_t;
455  
456  /*! @brief  Control settings for Fast Antenna Diversity */
457  typedef enum  _FAD_LPPS_CTRL
458  {
459      NONE = 0,
460      FAD_ENABLED = 1,
461      LPPS_ENABLED = 2
462  } FAD_LPPS_CTRL_T;
463  
464  /*! @brief  XCVR XCVR Panic codes for indicating panic reason. */
465  typedef enum _XCVR_PANIC_ID
466  {
467      WRONG_RADIO_ID_DETECTED = 1,
468      CALIBRATION_INVALID = 2,
469  } XCVR_PANIC_ID_T;
470  
471  /*! @brief  Initialization or mode change selection for config routine. */
472  typedef enum _XCVR_INIT_MODE_CHG
473  {
474      XCVR_MODE_CHANGE = 0,
475      XCVR_FIRST_INIT = 1,
476  } XCVR_INIT_MODE_CHG_T;
477  
478  typedef enum _XCVR_COEX_PRIORITY
479  {
480      XCVR_COEX_LOW_PRIO = 0,
481      XCVR_COEX_HIGH_PRIO = 1
482  }   XCVR_COEX_PRIORITY_T;
483  
484  /*! @brief Current configuration of the radio. */
485  typedef struct xcvr_currConfig_tag
486  {
487      radio_mode_t radio_mode;
488      data_rate_t data_rate;
489  } xcvr_currConfig_t;
490  
491  /*!
492   * @brief XCVR RX_DIG channel filter coefficient storage
493   * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage.
494   */
495  typedef struct _xcvr_rx_chf_coeffs
496  {
497      uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */
498      uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */
499      uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */
500      uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */
501      uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */
502      uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */
503      uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */
504      uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */
505      uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */
506      uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */
507      uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */
508      uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */
509  } xcvr_rx_chf_coeffs_t;
510  
511  /*!
512   * @brief XCVR masked init type for 32 bit registers
513   * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position.
514   */
515  typedef struct _xcvr_masked_init_32
516  {
517      uint32_t mask;
518      uint32_t init;
519  } xcvr_masked_init_32_t;
520  
521  /*!
522   * @brief XCVR common configure structure
523   */
524  typedef struct _xcvr_common_config
525  {
526      /* XCVR_ANA configs */
527      xcvr_masked_init_32_t ana_sy_ctrl1;
528  
529      /* XCVR_PLL_DIG configs */
530      uint32_t pll_hpm_bump;
531      uint32_t pll_mod_ctrl;
532      uint32_t pll_chan_map;
533      uint32_t pll_lock_detect;
534      uint32_t pll_hpm_ctrl;
535  #if !RADIO_IS_GEN_2P1
536      uint32_t pll_hpmcal_ctrl;
537  #endif /* !RADIO_IS_GEN_2P1 */
538      uint32_t pll_hpm_sdm_res;
539      uint32_t pll_lpm_ctrl;
540      uint32_t pll_lpm_sdm_ctrl1;
541      uint32_t pll_delay_match;
542      uint32_t pll_ctune_ctrl;
543  
544      /* XCVR_RX_DIG configs */
545      uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
546      uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */
547      uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */
548      uint32_t dcoc_ctrl_1_init;
549      uint32_t dcoc_cal_gain_init;
550      uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */
551      uint32_t dcoc_cal_rcp_init;
552      uint32_t lna_gain_val_3_0;
553      uint32_t lna_gain_val_7_4;
554      uint32_t lna_gain_val_8;
555      uint32_t bba_res_tune_val_7_0;
556      uint32_t bba_res_tune_val_10_8;
557      uint32_t lna_gain_lin_val_2_0_init;
558      uint32_t lna_gain_lin_val_5_3_init;
559      uint32_t lna_gain_lin_val_8_6_init;
560      uint32_t lna_gain_lin_val_9_init;
561      uint32_t bba_res_tune_lin_val_3_0_init;
562      uint32_t bba_res_tune_lin_val_7_4_init;
563      uint32_t bba_res_tune_lin_val_10_8_init;
564      uint32_t dcoc_bba_step_init;
565      uint32_t dcoc_tza_step_00_init;
566      uint32_t dcoc_tza_step_01_init;
567      uint32_t dcoc_tza_step_02_init;
568      uint32_t dcoc_tza_step_03_init;
569      uint32_t dcoc_tza_step_04_init;
570      uint32_t dcoc_tza_step_05_init;
571      uint32_t dcoc_tza_step_06_init;
572      uint32_t dcoc_tza_step_07_init;
573      uint32_t dcoc_tza_step_08_init;
574      uint32_t dcoc_tza_step_09_init;
575      uint32_t dcoc_tza_step_10_init;
576  #if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
577      uint32_t dcoc_cal_fail_th_init;
578      uint32_t dcoc_cal_pass_th_init;
579  #endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
580      uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */
581      uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */
582      uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */
583      uint32_t agc_ctrl_3_init;
584      /* Other agc config inits moved to modeXdatarate config table */
585      uint32_t agc_gain_tbl_03_00_init;
586      uint32_t agc_gain_tbl_07_04_init;
587      uint32_t agc_gain_tbl_11_08_init;
588      uint32_t agc_gain_tbl_15_12_init;
589      uint32_t agc_gain_tbl_19_16_init;
590      uint32_t agc_gain_tbl_23_20_init;
591      uint32_t agc_gain_tbl_26_24_init;
592      uint32_t rssi_ctrl_0_init;
593  #if RADIO_IS_GEN_3P0
594      uint32_t rssi_ctrl_1_init;
595  #endif /* RADIO_IS_GEN_3P0 */
596      uint32_t cca_ed_lqi_ctrl_0_init;
597      uint32_t cca_ed_lqi_ctrl_1_init;
598  
599      /* XCVR_TSM configs */
600      uint32_t tsm_ctrl;
601      uint32_t tsm_ovrd2_init;
602      uint32_t end_of_seq_init_26mhz;
603      uint32_t end_of_seq_init_32mhz;
604  #if !RADIO_IS_GEN_2P1
605      uint32_t lpps_ctrl_init;
606  #endif /* !RADIO_IS_GEN_2P1 */
607      uint32_t tsm_fast_ctrl2_init_26mhz;
608      uint32_t tsm_fast_ctrl2_init_32mhz;
609      uint32_t recycle_count_init_26mhz;
610      uint32_t recycle_count_init_32mhz;
611      uint32_t pa_ramp_tbl_0_init;
612      uint32_t pa_ramp_tbl_1_init;
613  #if RADIO_IS_GEN_3P0
614      uint32_t pa_ramp_tbl_2_init;
615      uint32_t pa_ramp_tbl_3_init;
616  #endif /* RADIO_IS_GEN_3P0 */
617      uint32_t tsm_timing_00_init;
618      uint32_t tsm_timing_01_init;
619      uint32_t tsm_timing_02_init;
620      uint32_t tsm_timing_03_init;
621      uint32_t tsm_timing_04_init;
622      uint32_t tsm_timing_05_init;
623      uint32_t tsm_timing_06_init;
624      uint32_t tsm_timing_07_init;
625      uint32_t tsm_timing_08_init;
626      uint32_t tsm_timing_09_init;
627      uint32_t tsm_timing_10_init;
628      uint32_t tsm_timing_11_init;
629      uint32_t tsm_timing_12_init;
630      uint32_t tsm_timing_13_init;
631      uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */
632      uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */
633      uint32_t tsm_timing_15_init;
634      uint32_t tsm_timing_16_init_26mhz;
635      uint32_t tsm_timing_16_init_32mhz;
636      uint32_t tsm_timing_17_init;
637      uint32_t tsm_timing_18_init;
638      uint32_t tsm_timing_19_init;
639      uint32_t tsm_timing_20_init;
640      uint32_t tsm_timing_21_init;
641      uint32_t tsm_timing_22_init;
642      uint32_t tsm_timing_23_init;
643      uint32_t tsm_timing_24_init;
644      uint32_t tsm_timing_25_init_26mhz;
645      uint32_t tsm_timing_25_init_32mhz;
646      uint32_t tsm_timing_26_init;
647      uint32_t tsm_timing_27_init_26mhz;
648      uint32_t tsm_timing_27_init_32mhz;
649      uint32_t tsm_timing_28_init_26mhz;
650      uint32_t tsm_timing_28_init_32mhz;
651      uint32_t tsm_timing_29_init_26mhz;
652      uint32_t tsm_timing_29_init_32mhz;
653      uint32_t tsm_timing_30_init_26mhz;
654      uint32_t tsm_timing_30_init_32mhz;
655      uint32_t tsm_timing_31_init_26mhz;
656      uint32_t tsm_timing_31_init_32mhz;
657      uint32_t tsm_timing_32_init_26mhz;
658      uint32_t tsm_timing_32_init_32mhz;
659      uint32_t tsm_timing_33_init_26mhz;
660      uint32_t tsm_timing_33_init_32mhz;
661      uint32_t tsm_timing_34_init;
662      uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/
663      uint32_t tsm_timing_36_init_26mhz;
664      uint32_t tsm_timing_36_init_32mhz;
665      uint32_t tsm_timing_37_init_26mhz;
666      uint32_t tsm_timing_37_init_32mhz;
667      uint32_t tsm_timing_38_init;
668      uint32_t tsm_timing_39_init_26mhz;
669      uint32_t tsm_timing_39_init_32mhz;
670      uint32_t tsm_timing_40_init_26mhz;
671      uint32_t tsm_timing_40_init_32mhz;
672      uint32_t tsm_timing_41_init_26mhz;
673      uint32_t tsm_timing_41_init_32mhz;
674      uint32_t tsm_timing_51_init;
675      uint32_t tsm_timing_52_init_26mhz;
676      uint32_t tsm_timing_52_init_32mhz;
677      uint32_t tsm_timing_53_init;
678      uint32_t tsm_timing_54_init_26mhz;
679      uint32_t tsm_timing_54_init_32mhz;
680      uint32_t tsm_timing_55_init_26mhz;
681      uint32_t tsm_timing_55_init_32mhz;
682      uint32_t tsm_timing_56_init_26mhz;
683      uint32_t tsm_timing_56_init_32mhz;
684      uint32_t tsm_timing_57_init;
685      uint32_t tsm_timing_58_init;
686  
687      /* XCVR_TX_DIG configs */
688      uint32_t tx_ctrl;
689      uint32_t tx_data_padding;
690       uint32_t tx_dft_pattern;
691  #if !RADIO_IS_GEN_2P1
692      uint32_t rf_dft_bist_1;
693      uint32_t rf_dft_bist_2;
694  #endif /* !RADIO_IS_GEN_2P1 */
695  } xcvr_common_config_t;
696  
697  /*! @brief XCVR mode specific configure structure (varies by radio mode) */
698  typedef struct _xcvr_mode_config
699  {
700      radio_mode_t radio_mode;
701      uint32_t scgc5_clock_ena_bits;
702  
703      /* XCVR_MISC configs */
704      xcvr_masked_init_32_t xcvr_ctrl;
705  
706      /* XCVR_PHY configs */
707  #if RADIO_IS_GEN_3P0
708      uint32_t phy_fsk_pd_cfg0;
709      uint32_t phy_fsk_pd_cfg1;
710      uint32_t phy_fsk_cfg;
711      uint32_t phy_fsk_misc;
712      uint32_t phy_fad_ctrl;
713  #else
714      uint32_t phy_pre_ref0_init;
715      uint32_t phy_pre_ref1_init;
716      uint32_t phy_pre_ref2_init;
717      uint32_t phy_cfg1_init;
718      uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */
719  #endif /* RADIO_IS_GEN_3P0 */
720  
721      /* XCVR_RX_DIG configs */
722      uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
723      uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
724      uint32_t agc_ctrl_0_init; /* NOTE:  Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */
725  
726      /* XCVR_TSM configs */
727  #if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1)
728      uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */
729  #endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */
730  
731      /* XCVR_TX_DIG configs */
732      uint32_t tx_gfsk_ctrl;
733      uint32_t tx_gfsk_coeff1_26mhz;
734      uint32_t tx_gfsk_coeff2_26mhz;
735      uint32_t tx_gfsk_coeff1_32mhz;
736      uint32_t tx_gfsk_coeff2_32mhz;
737  } xcvr_mode_config_t;
738  
739  /*!
740   * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate)
741   * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay
742   * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate.
743   */
744  typedef struct _xcvr_mode_datarate_config
745  {
746      radio_mode_t radio_mode;
747      data_rate_t data_rate;
748  
749      /* XCVR_ANA configs */
750      xcvr_masked_init_32_t ana_sy_ctrl2;
751      xcvr_masked_init_32_t ana_rx_bba;
752      xcvr_masked_init_32_t ana_rx_tza;
753  
754      /* XCVR_PHY configs */
755  #if RADIO_IS_GEN_3P0
756      uint32_t phy_fsk_misc_mode_datarate;
757  #else
758      uint32_t phy_cfg2_init;
759  #endif /* RADIO_IS_GEN_3P0 */
760  
761      uint32_t agc_ctrl_2_init_26mhz;
762      uint32_t agc_ctrl_2_init_32mhz;
763      xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */
764      xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */
765      uint32_t rx_rccal_ctrl_0;
766      uint32_t rx_rccal_ctrl_1;
767  
768      /* XCVR_TX_DIG configs */
769      uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */
770      uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */
771  } xcvr_mode_datarate_config_t;
772  
773  /*!
774   * @brief XCVR datarate specific configure structure (varies by data rate)
775   * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay
776   * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate.
777   */
778  typedef struct _xcvr_datarate_config
779  {
780      data_rate_t data_rate;
781  
782      /* XCVR_PHY configs */
783      uint32_t phy_el_cfg_init; /* Note: EL_ENABLE  is set in xcvr_mode_config_t settings */
784  
785      /* XCVR_RX_DIG configs */
786      uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
787      uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
788      uint32_t agc_ctrl_1_init_26mhz;
789      uint32_t agc_ctrl_1_init_32mhz;
790      uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */
791      uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */
792      uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */
793      uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */
794      uint32_t dcoc_ctrl_2_init_26mhz;
795      uint32_t dcoc_ctrl_2_init_32mhz;
796      uint32_t dcoc_cal_iir_init_26mhz;
797      uint32_t dcoc_cal_iir_init_32mhz;
798      uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */
799      uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */
800  } xcvr_datarate_config_t;
801  
802  /*!
803   * @brief LPUART callback function type
804   *
805   * The panic callback function is defined by system if system need to be informed of XCVR fatal errors.
806   * refer to #XCVR_RegisterPanicCb
807   */
808  typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2);
809  
810  /* Make available const structures from config files */
811  extern const xcvr_common_config_t xcvr_common_config;
812  extern const xcvr_mode_config_t zgbe_mode_config;
813  extern const xcvr_mode_config_t ble_mode_config;
814  extern const xcvr_mode_config_t ant_mode_config;
815  extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config;
816  extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config;
817  extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config;
818  extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config;
819  extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config;
820  extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config;
821  extern const xcvr_mode_config_t msk_mode_config;
822  
823  #if RADIO_IS_GEN_3P0
824  extern const xcvr_datarate_config_t xcvr_2mbps_config;
825  #endif /* RADIO_IS_GEN_3P0 */
826  extern const xcvr_datarate_config_t xcvr_1mbps_config;
827  extern const xcvr_datarate_config_t xcvr_500kbps_config;
828  extern const xcvr_datarate_config_t xcvr_250kbps_config;
829  extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */
830  
831  #if RADIO_IS_GEN_3P0
832  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config;
833  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config;
834  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config;
835  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config;
836  extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config;
837  #endif /* RADIO_IS_GEN_3P0 */
838  extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config;
839  extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config;
840  extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config;
841  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config;
842  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config;
843  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config;
844  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config;
845  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config;
846  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config;
847  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config;
848  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config;
849  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config;
850  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config;
851  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config;
852  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config;
853  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config;
854  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config;
855  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config;
856  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config;
857  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config;
858  extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config;
859  extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config;
860  extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config;
861  extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config;
862  
863  /*******************************************************************************
864   * API
865   ******************************************************************************/
866  
867  #if defined(__cplusplus)
868  extern "C" {
869  #endif
870  
871  /*!
872   * @name XCVR functional Operation
873   * @{
874   */
875  
876  /*!
877   * @brief  Initializes an XCVR instance.
878   *
879   * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to
880   * start up the XCVR in most situations.
881   *
882   * @param radio_mode The radio mode for which the XCVR should be configured.
883   * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
884   * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions.
885   */
886  xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate);
887  
888  /*!
889   * @brief  Deinitializes an XCVR instance.
890   *
891   * This function gate the XCVR module clock and set all register value to reset value.
892   *
893   */
894  void XCVR_Deinit(void);
895  
896  /*!
897   * @brief  Initializes XCVR configure structure.
898   *
899   * This function updates pointers to the XCVR configure structures with default values.
900   * The configurations are divided into a common structure, a set of radio mode specific
901   * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at
902   * each datarate), and a set of data rate specific structures.
903   * The pointers provided by this routine point to const structures which can be
904   * copied to variable structures if changes to settings are required.
905   *
906   * @param radio_mode [in] The radio mode for which the configuration structures are requested.
907   * @param data_rate [in] The data rate for which the configuration structures are requested.
908   * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure.
909   * @param mode_config  [in,out] Pointer to a pointer to the mode specific configuration settings structure.
910   * @param mode_datarate_config  [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure.
911   * @param datarate_config  [in,out] Pointer to a pointer to the data rate specific configuration settings structure.
912   * @return 0 success, others failure
913   * @see XCVR_Configure
914   */
915  xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode,
916                                     data_rate_t data_rate,
917                                     const xcvr_common_config_t ** com_config,
918                                     const xcvr_mode_config_t ** mode_config,
919                                     const xcvr_mode_datarate_config_t ** mode_datarate_config,
920                                     const xcvr_datarate_config_t ** datarate_config);
921  
922  /*!
923   * @brief  Initializes an XCVR instance.
924   *
925   * This function initializes the XCVR module with user-defined settings.
926   *
927   * @param com_config Pointer to the common configuration settings structure.
928   * @param mode_config Pointer to the mode specific configuration settings structure.
929   * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure.
930   * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure.
931   * @param tempDegC temperature of the die in degrees C.
932   * @param ext_clk indicates the external clock setting, 32MHz or 26MHz.
933   * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0)
934   * @return 0 succeed, others failed
935   */
936  xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config,
937                              const xcvr_mode_config_t *mode_config,
938                              const xcvr_mode_datarate_config_t *mode_datarate_config,
939                              const xcvr_datarate_config_t *datarate_config,
940                              int16_t tempDegC,
941                              XCVR_INIT_MODE_CHG_T first_init);
942  
943  /*!
944   * @brief Set XCVR register to reset value.
945   *
946   * This function set XCVR register to the reset value.
947   *
948   */
949  void XCVR_Reset(void);
950  
951  /*!
952   * @brief  Change the operating mode of the radio.
953   *
954   * This function changes the XCVR to a new radio operating mode.
955   *
956   * @param new_radio_mode The radio mode for which the XCVR should be configured.
957   * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
958   * @return status of the mode change.
959   */
960   xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate);
961  
962  /*!
963   * @brief  Enable Narrowband RSSI measurement.
964   *
965   * This function enables the narrowband RSSI measurement
966   *
967   * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled.
968   */
969  void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable);
970  
971  /*!
972   * @brief  Set an arbitrary frequency for RX and TX for the radio.
973   *
974   * This function sets the radio frequency used for RX and RX..
975   *
976   * @param freq target frequency setting in Hz.
977   * @param refOsc reference oscillator setting in Hz.
978   * @return status of the frequency change.
979   * @details
980   */
981   xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc);
982  
983  /*!
984   * @brief  Register a callback from upper layers.
985   *
986   * This function registers a callback from the upper layers for the radio to call in case of fatal errors.
987   *
988   * @param fptr The function pointer to a panic callback.
989   */
990  void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */
991  
992  /*!
993   * @brief  Read the health status of the XCVR to detect errors.
994   *
995   * This function enables the upper layers to request the current radio health.
996   *
997   * @return The health status of the radio..
998   */
999  healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */
1000  
1001  /*!
1002   * @brief  Control FAD and LPPS features.
1003   *
1004   * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search.
1005   *
1006   * @param fptr control the FAD and LPPS settings.
1007   *
1008   */
1009   void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control);
1010  
1011  /*!
1012   * @brief  Change the mapping of the radio IRQs.
1013   *
1014   * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines.
1015   *
1016   * @param irq0_mapping  the LL which should be mapped to the INT0 line.
1017   * @param irq1_mapping  the LL which should be mapped to the INT1 line.
1018   * @return status of the mapping request.
1019   * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line.
1020   * @warning
1021   *  The same LL must NOT be mapped to both INT lines.
1022   */
1023   xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping);
1024  
1025  #if RADIO_IS_GEN_3P0
1026  /*!
1027   * @brief  Sets the network address used by the PHY during BLE Bit Streaming Mode.
1028   *
1029   * This function programs the register in the PHY which contains the network address used during BSM.
1030   *
1031   * @param bsm_ntw_address  the address to be used during BSM.
1032   * @ note This routine does NOT enable BSM.
1033   */
1034  void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address);
1035  
1036  /*!
1037   * @brief  Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode.
1038   *
1039   * This function reads the register in the PHY which contains the network address used during BSM.
1040   *
1041   * @return bsm_ntw_address  the address to be used during BSM.
1042   * @ note This routine does NOT enable BSM.
1043   */
1044  uint32_t XCVR_GetBSM_NTW_Address(void);
1045  #endif /* RADIO_IS_GEN_3P0 */
1046  
1047  /*!
1048   * @brief  Get the mapping of the one of the radio IRQs.
1049   *
1050   * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines.
1051   *
1052   * @param int_num the number, 0 or 1, of the INT line to fetched.
1053   * @return the mapping setting of the specified line.
1054   * @note Any value passed into this routine other than 0 will be treated as a 1.
1055   */
1056   link_layer_t XCVR_GetIRQMapping(uint8_t int_num);
1057  
1058  /*!
1059   * @brief  Get the current configuration of the XCVR.
1060   *
1061   * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc
1062   *
1063   * @param curr_config pointer to a structure to be updated with the current mode and data rate.
1064   * @return the status of the request, success or invalid parameter (null pointer).
1065   * @note This API will return meaningless results if called before the radio is initialized...
1066   */
1067  xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config);
1068  
1069  /*******************************************************************************
1070   * Customer level trim functions
1071   ******************************************************************************/
1072  /*!
1073   * @brief  Controls setting the XTAL trim value..
1074   *
1075   * This function enables the upper layers set a crystal trim compensation facor
1076   *
1077   * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error.
1078   * @return The health status of the radio..
1079   */
1080  xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim);
1081  
1082  /*!
1083   * @brief  Controls getting the XTAL trim value..
1084   *
1085   * This function enables the upper layers to read the current XTAL compensation factors.
1086   * The returned value is in the range 0..127 (7 bits).
1087   *
1088   * @return The XTAL trim compensation factors..
1089   */
1090  uint8_t  XCVR_GetXtalTrim(void);
1091  
1092  /*!
1093   * @brief  Controls setting the RSSI adjustment..
1094   *
1095   * This function enables the upper layers to set an RSSI adjustment value.
1096   *
1097   * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step.
1098   * @return The health status of the radio..
1099   */
1100  xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj);
1101  
1102  /*!
1103   * @brief  Controls getting the RSSI adjustment..
1104   *
1105   * This function enables the upper layers to read the current XCVR RSSI adjustment value.
1106   * The returned value is a signed 8-bit value, in 1/4 dBm step.
1107   *
1108   * @return The RSSI adjustment value..
1109   */
1110  int8_t  XCVR_GetRssiAdjustment(void);
1111  
1112  /*!
1113   * @brief  Controls setting the PLL to a particular channel.
1114   *
1115   * This function enables setting the radio channel for TX and RX.
1116   *
1117   * @param channel the channel number to set
1118   * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list..
1119   * @return The status of the channel over-ride.
1120   */
1121  xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel);
1122  
1123  /*!
1124   * @brief  Reads the current frequency for RX and TX for the radio.
1125   *
1126   * This function reads the radio frequency used for RX and RX..
1127   *
1128   * @return Current radio frequency setting.
1129   */
1130  uint32_t XCVR_GetFreq(void);
1131  
1132  /*!
1133   * @brief  Force receiver warmup.
1134   *
1135   * This function forces the initiation of a receiver warmup sequence.
1136   *
1137   */
1138  void XCVR_ForceRxWu(void);
1139  
1140  /*!
1141   * @brief  Force receiver warmdown.
1142   *
1143   * This function forces the initiation of a receiver warmdown sequence.
1144   *
1145   */
1146   void XCVR_ForceRxWd(void);
1147  
1148  /*!
1149   * @brief  Force transmitter warmup.
1150   *
1151   * This function forces the initiation of a transmit warmup sequence.
1152   *
1153   */
1154  void XCVR_ForceTxWu(void);
1155  
1156  /*!
1157   * @brief  Force transmitter warmdown.
1158   *
1159   * This function forces the initiation of a transmit warmdown sequence.
1160   *
1161   */
1162  void XCVR_ForceTxWd(void);
1163  
1164  /*!
1165   * @brief  Starts transmit with a TX pattern register data sequence.
1166   *
1167   * This function starts transmitting using the DFT pattern register mode.
1168   *
1169   * @param channel_num -  the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation.
1170   * @param radio_mode The radio mode for which the XCVR should be configured.
1171   * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
1172   * @param tx_pattern -  the data pattern to transmit on.
1173   * @return The status of the pattern reg transmit.
1174   * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode
1175   *   and data rate.
1176   */
1177  xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern);
1178  
1179  /*!
1180   * @brief  Starts transmit with a TX LFSR register data sequence.
1181   *
1182   * This function starts transmitting using the DFT LFSR register mode.
1183   *
1184   * @param channel_num -  the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation.
1185   * @param radio_mode The radio mode for which the XCVR should be configured.
1186   * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
1187   * @param lfsr_length -  the length of the LFSR sequence to use.
1188   * @return The status of the LFSR reg transmit.
1189   * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode
1190   *   and data rate.
1191   */
1192  xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length);
1193  
1194  /*!
1195   * @brief Controls clearing all TX DFT settings.
1196   *
1197   * This function reverts all TX DFT settings from the test modes to normal operating mode.
1198   *
1199   */
1200  void XCVR_DftTxOff(void);
1201  
1202  /*!
1203   * @brief  Controls setting the PA power level.
1204   *
1205   * This function enables setting the PA power level to a specific setting, overriding any link layer settings.
1206   *
1207   * @param pa_power -  the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive.
1208   * @return The status of the PA power over-ride.
1209   */
1210  xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power);
1211  
1212  /*!
1213   * @brief Starts CW TX.
1214   *
1215   * This function starts transmitting CW (no modulation).
1216   *
1217   * @param rf_channel_freq -  the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive.
1218   * @param protocol -  the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK).
1219   * @return The status of the CW transmit.
1220   */
1221  xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol);
1222  
1223  xcvrStatus_t XCVR_CoexistenceInit(void);
1224  xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority);
1225  xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings);
1226  
1227  /* @} */
1228  
1229  #if defined(__cplusplus)
1230  }
1231  #endif
1232  
1233  /*! @}*/
1234  
1235  #endif /* _FSL_XCVR_H_ */
1236  
1237