1 /***************************************************************************//**
2 * \file cy_i2s.h
3 * \version 2.30
4 *
5 * The header file of the I2S driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2020 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_i2s
27 * \{
28 * \note IP Supported: AUDIOSS
29 * \note Device Categories: CAT1A. Please refer <a href="usergroup1.html">Device Catalog</a>.
30 * The I2S driver provides a function API to manage Inter-IC Sound.
31 *
32 * The functions and other declarations used in this driver are in cy_i2s.h.
33 * You can include cy_pdl.h to get access to all functions
34 * and declarations in the PDL.
35 *
36 * I2S is used to send digital audio streaming data to external I2S devices,
37 * such as audio codecs or simple DACs. It can also receive digital audio streaming data.
38 *
39 * Features:
40 * * An industry standard NXP I2S interface.
41 * * Supports master/slave TX/RX operation.
42 * * Programmable Channel/Word Lengths.
43 * * Supports External Clock operation.
44 *
45 * The I2S bus is an industry standard. The hardware interface was
46 * developed by Philips Semiconductors (now NXP Semiconductors).
47 *
48 * \section group_i2s_configuration_considerations Configuration Considerations
49 *
50 * To set up an I2S, provide the configuration parameters in the
51 * \ref cy_stc_i2s_config_t structure.
52 *
53 * For example, for Tx configuration, set txEnabled to true, configure
54 * txDmaTrigger (depending on whether DMA is going to be used or not), set
55 * extClk (if an external clock is used), provide clkDiv, txMasterMode,
56 * txAlignment, txChannels (only are is supported in I2S and Left Justified modes)
57 * txSdoLatchingTime (for slave mode only), txChannelLength, txWordLength,
58 * txWsPulseWidth (for TMD modes only), txWatchdogEnable and txWatchdogValue
59 * (both for Slave mode only, and when the watchdog interrupt will be used),
60 * either txSckoInversion or txSckiInversion (based on txMasterMode setting),
61 * txFifoTriggerLevel (when the Trig interrupt will be used) and txOverheadValue
62 * (only when the word length is less than channel length).
63 * A similar setup is for the Rx configuration.
64 *
65 * To initialize the I2S block, call the \ref Cy_I2S_Init function, providing the
66 * filled \ref cy_stc_i2s_config_t structure.
67 * Before starting the transmission, clear the FIFO \ref Cy_I2S_ClearTxFifo, then
68 * fill the first Tx data frame by calling \ref Cy_I2S_WriteTxData once for each
69 * channel (e.g. twice for I2S mode with only two channels) with zero data. Then
70 * call the \ref Cy_I2S_EnableTx itself.
71 * For the reception the sequence is the same except for filling the first data
72 * frame. Only clearing RX FIFO is enough.
73 *
74 * For example:
75 * \snippet i2s/snippet/main.c snippet_Cy_I2S_Init
76 *
77 * If you use a DMA, the DMA channel should be previously configured. The I2S interrupts
78 * (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask.
79 *
80 * For example, if the trigger interrupt is used during operation, the ISR
81 * should call the \ref Cy_I2S_WriteTxData as many times as required for your
82 * FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt
83 * with appropriate parameters.
84 *
85 * The I2S/Left Justified data formats always contains two data channels.
86 * They are ordered one-by-one in the FIFOs and left always goes first.
87 * So in case of mono audio stream transmission, each sample can be put twice
88 * into the TX FIFO (in this case both channels will sound the same),
89 * or combined with zeroes: sample1-zero-sample2-zero (in this case only the
90 * left channel will finally sound, for a right-only case, zero should go first).
91 * The TDM frame word order in FIFOs is similar, one-by-one.
92 *
93 * If a DMA is used and the DMA channel is properly configured - no CPU activity
94 * (or any application code) is needed for I2S operation.
95 *
96 * The I2S frame appears as:
97 * \image html i2s_frame.png
98 * This is an example for the channel length = 32. A similar case exists for the rest
99 * channel lengths, with one limitation: the word length could be less than or equal
100 * to the channel length. See the device technical reference manual (TRM)
101 * for more details.
102 *
103 * \section group_i2s_more_information More Information
104 * See: the the I2S chapter of the device technical reference manual (TRM);
105 * I2S_PDL Component datasheet;
106 * CE218636 - PSOC 6 MCU INTER-IC SOUND (I2S) EXAMPLE.
107 *
108 * \section group_i2s_changelog Changelog
109 * <table class="doxtable">
110 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
111 * <tr>
112 * <td>2.30</td>
113 * <td>Update to configure MCLK.</td>
114 * <td>Update to configure i2S on core CM7.</td>
115 * </tr>
116 * <tr>
117 * <td>2.20</td>
118 * <td>Fixed/documented MISRA 2012 violations.</td>
119 * <td>MISRA 2012 compliance.</td>
120 * </tr>
121 * <tr>
122 * <td>2.10.1</td>
123 * <td>Minor documentation updates.</td>
124 * <td>Documentation enhancement.</td>
125 * </tr>
126 * <tr>
127 * <td rowspan="2">2.10</td>
128 * <td>Flattened the organization of the driver source code into the single
129 * source directory and the single include directory.
130 * </td>
131 * <td>Driver library directory-structure simplification.</td>
132 * </tr>
133 * <tr>
134 * <td>Added register access layer. Use register access macros instead
135 * of direct register access using dereferenced pointers.</td>
136 * <td>Makes register access device-independent, so that the PDL does
137 * not need to be recompiled for each supported part number.</td>
138 * </tr>
139 * <tr>
140 * <td>2.0.1</td>
141 * <td>Added Low Power Callback section</td>
142 * <td>Documentation update and clarification</td>
143 * </tr>
144 * <tr>
145 * <td>2.0</td>
146 * <td>The slave operation is added, Left Justified and TDM modes are added</td>
147 * <td></td>
148 * </tr>
149 * <tr>
150 * <td>1.0</td>
151 * <td>Initial version</td>
152 * <td></td>
153 * </tr>
154 * </table>
155 *
156 * \defgroup group_i2s_macros Macros
157 * \defgroup group_i2s_functions Functions
158 * \{
159 * \defgroup group_i2s_functions_syspm_callback Low Power Callback
160 * \}
161 * \defgroup group_i2s_data_structures Data Structures
162 * \defgroup group_i2s_enums Enumerated Types
163 */
164
165
166 #if !defined(CY_I2S_H)
167 #define CY_I2S_H
168
169 #include "cy_device.h"
170
171 #if (defined (AUDIOSS_I2S_PRESENT) || defined(CY_DOXYGEN))
172
173 #include <stddef.h>
174 #include <stdbool.h>
175 #include "cy_syslib.h"
176 #include "cy_syspm.h"
177
178 #ifdef __cplusplus
179 extern "C" {
180 #endif
181
182 /** \addtogroup group_i2s_macros
183 * \{
184 */
185
186 /** The driver major version */
187 #define CY_I2S_DRV_VERSION_MAJOR 2
188
189 /** The driver minor version */
190 #define CY_I2S_DRV_VERSION_MINOR 30
191
192 /** The I2S driver identifier */
193 #define CY_I2S_ID (CY_PDL_DRV_ID(0x20U))
194
195 /**
196 * \defgroup group_i2s_macros_interrupt_masks Interrupt Masks
197 * \{
198 */
199
200 /** Bit 0: Less entries in the TX FIFO than specified by Trigger Level. */
201 #define CY_I2S_INTR_TX_TRIGGER (I2S_INTR_TX_TRIGGER_Msk)
202 /** Bit 1: TX FIFO is not full. */
203 #define CY_I2S_INTR_TX_NOT_FULL (I2S_INTR_TX_NOT_FULL_Msk)
204 /** Bit 4: TX FIFO is empty, i.e. it has 0 entries. */
205 #define CY_I2S_INTR_TX_EMPTY (I2S_INTR_TX_EMPTY_Msk)
206 /** Bit 5: Attempt to write to a full TX FIFO. */
207 #define CY_I2S_INTR_TX_OVERFLOW (I2S_INTR_TX_OVERFLOW_Msk)
208 /** Bit 6: Attempt to read from an empty TX FIFO.
209 * This happens when the IP is ready to transfer data and TX_EMPTY is '1'. */
210 #define CY_I2S_INTR_TX_UNDERFLOW (I2S_INTR_TX_UNDERFLOW_Msk)
211 /** Bit 8: Tx watchdog event occurs. */
212 #define CY_I2S_INTR_TX_WD (I2S_INTR_TX_WD_Msk)
213 /** Bit 16: More entries in the RX FIFO than specified by Trigger Level. */
214 #define CY_I2S_INTR_RX_TRIGGER (I2S_INTR_RX_TRIGGER_Msk)
215 /** Bit 18: RX FIFO is not empty. */
216 #define CY_I2S_INTR_RX_NOT_EMPTY (I2S_INTR_RX_NOT_EMPTY_Msk)
217 /** Bit 19: RX FIFO is full. */
218 #define CY_I2S_INTR_RX_FULL (I2S_INTR_RX_FULL_Msk)
219 /** Bit 21: Attempt to write to a full RX FIFO. */
220 #define CY_I2S_INTR_RX_OVERFLOW (I2S_INTR_RX_OVERFLOW_Msk)
221 /** Bit 22: Attempt to read from an empty RX FIFO. */
222 #define CY_I2S_INTR_RX_UNDERFLOW (I2S_INTR_RX_UNDERFLOW_Msk)
223 /** Bit 24: Rx watchdog event occurs. */
224 #define CY_I2S_INTR_RX_WD (I2S_INTR_RX_WD_Msk)
225
226 /** \} group_i2s_macros_interrupt_masks */
227
228
229 /**
230 * \defgroup group_i2s_macros_current_state Current State
231 * \{
232 */
233
234 /** Transmission is active */
235 #define CY_I2S_TX_START (I2S_CMD_TX_START_Msk)
236 /** Transmission is paused */
237 #define CY_I2S_TX_PAUSE (I2S_CMD_TX_PAUSE_Msk)
238 /** Reception is active */
239 #define CY_I2S_RX_START (I2S_CMD_RX_START_Msk)
240
241 /** \} group_i2s_macros_current_state */
242
243 /** \} group_i2s_macros */
244
245 /**
246 * \addtogroup group_i2s_enums
247 * \{
248 */
249
250 /**
251 * I2S status definitions.
252 */
253
254 typedef enum
255 {
256 CY_I2S_SUCCESS = 0x00UL, /**< Successful. */
257 CY_I2S_BAD_PARAM = CY_I2S_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */
258 } cy_en_i2s_status_t;
259
260
261 /**
262 * I2S data alignment.
263 */
264 typedef enum
265 {
266 CY_I2S_LEFT_JUSTIFIED = 0U, /**< Left justified. */
267 CY_I2S_I2S_MODE = 1U, /**< I2S mode. */
268 CY_I2S_TDM_MODE_A = 2U, /**< TDM mode A. */
269 CY_I2S_TDM_MODE_B = 3U /**< TDM mode B. */
270 } cy_en_i2s_alignment_t;
271
272 /**
273 * I2S channel/word length.
274 */
275 typedef enum
276 {
277 CY_I2S_LEN8 = 0U, /**< Channel/word length: 8 bit. */
278 CY_I2S_LEN16 = 1U, /**< Channel/Word length: 16 bit. */
279 CY_I2S_LEN18 = 2U, /**< Channel/Word length: 18 bit. */
280 CY_I2S_LEN20 = 3U, /**< Channel/Word length: 20 bit. */
281 CY_I2S_LEN24 = 4U, /**< Channel/Word length: 24 bit. */
282 CY_I2S_LEN32 = 5U /**< Channel/Word length: 32 bit. */
283 } cy_en_i2s_len_t;
284
285 /**
286 * I2S TX overhead value.
287 */
288 typedef enum
289 {
290 CY_I2S_OVHDATA_ZERO = 0U, /**< Fill overhead bits by zeroes. */
291 CY_I2S_OVHDATA_ONE = 1U, /**< Fill overhead bits by ones. */
292 } cy_en_i2s_overhead_t;
293
294 /**
295 * I2S WS pulse width.
296 */
297 typedef enum
298 {
299 CY_I2S_WS_ONE_SCK_CYCLE = 0U, /**< WS pulse width is one SCK cycle. */
300 CY_I2S_WS_ONE_CHANNEL_LENGTH = 1U, /**< WS pulse width is one channel length. */
301 } cy_en_i2s_ws_pw_t;
302
303 #if (CY_IP_MXAUDIOSS_VERSION>=2)
304 typedef enum
305 {
306 CY_I2S_MCLK_DIV_1 = 0u, /**< Divide clk_audio_i2s by 1 (Bypass). */
307 CY_I2S_MCLK_DIV_2 = 1u, /**< Divide clk_audio_i2s by 2. */
308 CY_I2S_MCLK_DIV_4 = 2u, /**< Divide clk_audio_i2s by 4. */
309 CY_I2S_MCLK_DIV_8 = 3u, /**< Divide clk_audio_i2s by 8. */
310 } cy_en_i2s_mclk_div_t;
311 #endif
312
313 /** \} group_i2s_enums */
314
315 /**
316 * \addtogroup group_i2s_data_structures
317 * \{
318 */
319
320 /**
321 * I2S initialization configuration.
322 */
323 typedef struct
324 {
325 bool txEnabled; /**< Enables the I2S TX component: 'false': disabled. 'true': enabled. */
326 bool rxEnabled; /**< Enables the I2S RX component: 'false': disabled. 'true': enabled. */
327 bool txDmaTrigger; /**< 'false': TX DMA trigger disabled, 'true': TX DMA trigger enabled. */
328 bool rxDmaTrigger; /**< 'false': RX DMA trigger disabled, 'true': RX DMA trigger enabled. */
329 uint8_t clkDiv; /**< CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64. */
330 bool extClk; /**< 'false': internal clock, 'true': external clock. */
331 bool txMasterMode; /**< 'false': TX in slave mode, 'true': TX in master mode. */
332 cy_en_i2s_alignment_t txAlignment; /**< TX data alignment, see: #cy_en_i2s_alignment_t. */
333 cy_en_i2s_ws_pw_t txWsPulseWidth; /**< TX Word Select pulse width.
334 The value of this parameter is ignored in I2S and Left Justified modes
335 the WS pulse width is always "one channel length" in these modes. */
336 bool txWatchdogEnable; /**< 'false': TX watchdog disabled, 'true': TX watchdog enabled. */
337 uint32_t txWatchdogValue; /**< TX watchdog counter value (32 bit). */
338 bool txSdoLatchingTime; /**< 'false': SDO bit starts at falling edge (accordingly to the I2S
339 Standard, if txSckoInversion is false),
340 'true': SDO bit starts at rising edge which goes before the above
341 mentioned falling edge, i.e. the SDO signal is advanced by 0.5 SCK
342 period (if txSckoInversion is false).
343 If txSckoInversion is true - the rising/falling edges just swaps
344 in above explanations.
345 Effective only in slave mode, must be false in master mode.*/
346 bool txSckoInversion; /**< TX SCKO polarity:
347 'false': When transmitter is in master mode, serial data is
348 transmitted off the falling bit clock edge (accordingly to
349 the I2S Standard);
350 'true': When transmitter is in master mode, serial data is
351 transmitted off the rising bit clock edge.
352 Effective only in master mode. */
353 bool txSckiInversion; /**< TX SCKI polarity:
354 'false': When transmitter is in slave mode, serial data is
355 transmitted off the falling bit clock edge (accordingly to
356 the I2S Standard);
357 'true': When transmitter is in slave mode, serial data is
358 transmitted off the rising bit clock edge.
359 Effective only in slave mode. */
360 uint8_t txChannels; /**< Number of TX channels, valid range is 1...8 for TDM modes.
361 In the I2S and Left Justified modes the value of this parameter is
362 ignored - the real number of channels is always 2 in these modes. */
363 cy_en_i2s_len_t txChannelLength; /**< TX channel length, see #cy_en_i2s_len_t,
364 the value of this parameter is ignored in TDM modes, the real
365 channel length is 32 bit in these modes. */
366 cy_en_i2s_len_t txWordLength; /**< TX word length, see #cy_en_i2s_len_t,
367 must be less or equal to txChannelLength. */
368 cy_en_i2s_overhead_t txOverheadValue; /**< TX overhead bits value
369 when the word length is less than the channel length. */
370 uint8_t txFifoTriggerLevel; /**< TX FIFO interrupt trigger level (0, 1, ..., 255). */
371 bool rxMasterMode; /**< 'false': RX in slave mode, 'true': RX in master mode. */
372 cy_en_i2s_alignment_t rxAlignment; /**< RX data alignment, see: #cy_en_i2s_alignment_t. */
373 cy_en_i2s_ws_pw_t rxWsPulseWidth; /**< RX Word Select pulse width.
374 The value of this parameter is ignored in I2S and Left Justified modes
375 the WS pulse width is always "one channel length" in these modes. */
376 bool rxWatchdogEnable; /**< 'false': RX watchdog disabled, 'true': RX watchdog enabled. */
377 uint32_t rxWatchdogValue; /**< RX watchdog counter value (32 bit). */
378 bool rxSdiLatchingTime; /**< 'false': SDI bit starts at falling edge (accordingly to the I2S
379 Standard if rxSckoInversion is false),
380 'true': SDI bit starts at rising edge that goes after the above
381 mentioned falling edge, i.e. the SDI signal is delayed by 0.5 SCK
382 period (if rxSckoInversion is false).
383 If rxSckoInversion is true - the rising/falling edges just swaps
384 in above explanations.
385 Effective only in master mode, must be false in slave mode. */
386 bool rxSckoInversion; /**< RX SCKO polarity:
387 'false': When receiver is in master mode, serial data is
388 captured by the rising bit clock edge (accordingly to the
389 I2S Standard);
390 'true': When receiver is in master mode, serial data is
391 captured by the falling bit clock edge.
392 Effective only in master mode. */
393 bool rxSckiInversion; /**< RX SCKI polarity:
394 'false': When receiver is in slave mode, serial data is
395 captured by the rising bit clock edge (accordingly to the
396 I2S Standard);
397 'true': When receiver is in slave mode, serial data is
398 captured by the falling bit clock edge.
399 Effective only in slave mode. */
400 uint8_t rxChannels; /**< Number of RX channels, valid range is 1...8 for TDM modes.
401 In the I2S and Left Justified modes the value of this parameter is
402 ignored - the real number of channels is always 2 in these modes. */
403 cy_en_i2s_len_t rxChannelLength; /**< RX channel length, see #cy_en_i2s_len_t,
404 the value of this parameter is ignored in TDM modes, the real
405 channel length is 32 bit in these modes. */
406 cy_en_i2s_len_t rxWordLength; /**< RX word length, see #cy_en_i2s_len_t,
407 must be less or equal to rxChannelLength. */
408 bool rxSignExtension; /**< RX value sign extension (when the word length is less than 32 bits),
409 'false': all MSB are filled by zeroes,
410 'true': all MSB are filled by the original sign bit value. */
411 uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level
412 (0, 1, ..., (255 - (number of channels))). */
413 #if (CY_IP_MXAUDIOSS_VERSION>=2)
414 cy_en_i2s_mclk_div_t mclkDiv; /**< Selects clock divider for MCLK_OUT. */
415 bool mclkEn; /**< Enable MCLK - enables MCLK divider operation */
416 #endif
417 } cy_stc_i2s_config_t;
418
419
420 /**
421 * The I2S backup structure type to be used for the SysPm callback.
422 * \ref Cy_I2S_DeepSleepCallback context definition.
423 *
424 * \cond Also can be used for other purposes to store the current Tx/Rx
425 * operation state and interrupt settings - the factors that are usually
426 * changed on the fly. \endcond
427 */
428 typedef struct
429 {
430 uint32_t enableState; /**< Stores the I2S state */
431 uint32_t interruptMask; /**< Stores the I2S interrupt mask */
432 } cy_stc_i2s_context_t;
433
434 /** \} group_i2s_data_structures */
435
436 /** \cond INTERNAL */
437 /******************************************************************************
438 * Local definitions
439 *******************************************************************************/
440
441 #define CY_I2S_INTR_MASK (CY_I2S_INTR_TX_TRIGGER | \
442 CY_I2S_INTR_TX_NOT_FULL | \
443 CY_I2S_INTR_TX_EMPTY | \
444 CY_I2S_INTR_TX_OVERFLOW | \
445 CY_I2S_INTR_TX_UNDERFLOW | \
446 CY_I2S_INTR_TX_WD | \
447 CY_I2S_INTR_RX_TRIGGER | \
448 CY_I2S_INTR_RX_NOT_EMPTY | \
449 CY_I2S_INTR_RX_FULL | \
450 CY_I2S_INTR_RX_OVERFLOW | \
451 CY_I2S_INTR_RX_UNDERFLOW | \
452 CY_I2S_INTR_RX_WD)
453
454 /* Non-zero default values */
455 #define CY_I2S_TX_CTL_CH_NR_DEFAULT (0x1U)
456 #define CY_I2S_TX_CTL_I2S_MODE_DEFAULT (0x2U)
457 #define CY_I2S_TX_CTL_WS_PULSE_DEFAULT (0x1U)
458 #define CY_I2S_TX_CTL_CH_LEN_DEFAULT (0x4U)
459 #define CY_I2S_TX_CTL_WORD_LEN_DEFAULT (0x4U)
460
461 #define CY_I2S_TX_CTL_DEFAULT (_VAL2FLD(I2S_TX_CTL_CH_NR, CY_I2S_TX_CTL_CH_NR_DEFAULT) | \
462 _VAL2FLD(I2S_TX_CTL_I2S_MODE, CY_I2S_TX_CTL_I2S_MODE_DEFAULT) | \
463 _VAL2FLD(I2S_TX_CTL_WS_PULSE, CY_I2S_TX_CTL_WS_PULSE_DEFAULT) | \
464 _VAL2FLD(I2S_TX_CTL_CH_LEN, CY_I2S_TX_CTL_CH_LEN_DEFAULT) | \
465 _VAL2FLD(I2S_TX_CTL_WORD_LEN, CY_I2S_TX_CTL_WORD_LEN_DEFAULT))
466
467 #define CY_I2S_RX_CTL_CH_NR_DEFAULT (0x1U)
468 #define CY_I2S_RX_CTL_I2S_MODE_DEFAULT (0x2U)
469 #define CY_I2S_RX_CTL_WS_PULSE_DEFAULT (0x1U)
470 #define CY_I2S_RX_CTL_CH_LEN_DEFAULT (0x4U)
471 #define CY_I2S_RX_CTL_WORD_LEN_DEFAULT (0x4U)
472
473 #define CY_I2S_RX_CTL_DEFAULT (_VAL2FLD(I2S_RX_CTL_CH_NR, CY_I2S_RX_CTL_CH_NR_DEFAULT) | \
474 _VAL2FLD(I2S_RX_CTL_I2S_MODE, CY_I2S_RX_CTL_I2S_MODE_DEFAULT) | \
475 _VAL2FLD(I2S_RX_CTL_WS_PULSE, CY_I2S_RX_CTL_WS_PULSE_DEFAULT) | \
476 _VAL2FLD(I2S_RX_CTL_CH_LEN, CY_I2S_RX_CTL_CH_LEN_DEFAULT) | \
477 _VAL2FLD(I2S_RX_CTL_WORD_LEN, CY_I2S_RX_CTL_WORD_LEN_DEFAULT))
478
479 /* Macros for conditions used by CY_ASSERT calls */
480 #define CY_I2S_IS_ALIGNMENT_VALID(alignment) ((CY_I2S_LEFT_JUSTIFIED == (alignment)) || \
481 (CY_I2S_I2S_MODE == (alignment)) || \
482 (CY_I2S_TDM_MODE_A == (alignment)) || \
483 (CY_I2S_TDM_MODE_B == (alignment)))
484
485 #define CY_I2S_IS_LEN_VALID(length) ((CY_I2S_LEN8 == (length)) || \
486 (CY_I2S_LEN16 == (length)) || \
487 (CY_I2S_LEN18 == (length)) || \
488 (CY_I2S_LEN20 == (length)) || \
489 (CY_I2S_LEN24 == (length)) || \
490 (CY_I2S_LEN32 == (length)))
491
492 #define CY_I2S_IS_OVHDATA_VALID(overhead) ((CY_I2S_OVHDATA_ZERO == (overhead)) || \
493 (CY_I2S_OVHDATA_ONE == (overhead)))
494
495 #define CY_I2S_IS_WSPULSE_VALID(wsPulse) ((CY_I2S_WS_ONE_SCK_CYCLE == (wsPulse)) || \
496 (CY_I2S_WS_ONE_CHANNEL_LENGTH == (wsPulse)))
497
498 #define CY_I2S_IS_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 63U)
499 #define CY_I2S_IS_CHANNELS_VALID(channels) ((channels) <= 7UL)
500 #define CY_I2S_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_I2S_INTR_MASK)))
501
502 #define CY_I2S_IS_CHAN_WORD_VALID(channel, word) ((CY_I2S_IS_LEN_VALID(channel)) && \
503 (CY_I2S_IS_LEN_VALID(word)) && \
504 ((channel) >= (word)))
505 #define CY_I2S_IS_TRIG_LEVEL_VALID(trigLevel, channels) ((trigLevel) <= (255U - (channels)))
506
507 /** \endcond */
508
509
510 /**
511 * \addtogroup group_i2s_functions
512 * \{
513 */
514
515 cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config);
516 void Cy_I2S_DeInit(I2S_Type * base);
517
518 /** \addtogroup group_i2s_functions_syspm_callback
519 * The driver supports SysPm callback for Deep Sleep transition.
520 * \{
521 */
522 cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t const * callbackParams, cy_en_syspm_callback_mode_t mode);
523 /** \} */
524
525 __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base);
526 __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base);
527 __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base);
528 __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base);
529 __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base);
530 __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base);
531 __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base);
532
533 __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base);
534 __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base);
535 __STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data);
536 __STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base);
537 __STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base);
538 __STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base);
539 __STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base);
540
541 __STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base);
542 __STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base);
543 __STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base);
544 __STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base);
545 __STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base);
546 __STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base);
547 __STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base);
548 __STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base);
549
550 __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base);
551 __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt);
552 __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt);
553 __STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base);
554 __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt);
555 __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base);
556
557 /*******************************************************************************
558 * Function Name: Cy_I2S_EnableTx
559 ****************************************************************************//**
560 *
561 * Starts an I2S transmission. Interrupt enabling (by the
562 * \ref Cy_I2S_SetInterruptMask) is required after this function call, in case
563 * if any I2S interrupts are used in the application.
564 *
565 * \pre Cy_I2S_Init() must be called before.
566 *
567 * \param base The pointer to the I2S instance address.
568 *
569 * \funcusage
570 * \snippet i2s/snippet/main.c snippet_Cy_I2S_EnableTx
571 *
572 *******************************************************************************/
Cy_I2S_EnableTx(I2S_Type * base)573 __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base)
574 {
575 REG_I2S_CMD(base) |= I2S_CMD_TX_START_Msk;
576 }
577
578
579 /*******************************************************************************
580 * Function Name: Cy_I2S_PauseTx
581 ****************************************************************************//**
582 *
583 * Pauses an I2S transmission.
584 *
585 * \param base The pointer to the I2S instance address.
586 *
587 * \funcusage
588 * \snippet i2s/snippet/main.c snippet_Cy_I2S_PauseTx
589 *
590 *******************************************************************************/
Cy_I2S_PauseTx(I2S_Type * base)591 __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base)
592 {
593 REG_I2S_CMD(base) |= I2S_CMD_TX_PAUSE_Msk;
594 }
595
596
597 /*******************************************************************************
598 * Function Name: Cy_I2S_ResumeTx
599 ****************************************************************************//**
600 *
601 * Resumes an I2S transmission.
602 *
603 * \param base The pointer to the I2S instance address.
604 *
605 * \funcusage
606 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ResumeTx
607 *
608 *******************************************************************************/
Cy_I2S_ResumeTx(I2S_Type * base)609 __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base)
610 {
611 REG_I2S_CMD(base) &= (uint32_t) ~I2S_CMD_TX_PAUSE_Msk;
612 }
613
614
615 /*******************************************************************************
616 * Function Name: Cy_I2S_DisableTx
617 ****************************************************************************//**
618 *
619 * Stops an I2S transmission.
620 *
621 * \pre TX interrupt disabling (by the \ref Cy_I2S_SetInterruptMask) is required
622 * prior to this function call, in case any TX I2S interrupts are used.
623 *
624 * \param base The pointer to the I2S instance address.
625 *
626 * \funcusage
627 * \snippet i2s/snippet/main.c snippet_Cy_I2S_DisableTx
628 *
629 *******************************************************************************/
Cy_I2S_DisableTx(I2S_Type * base)630 __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base)
631 {
632 REG_I2S_CMD(base) &= (uint32_t) ~I2S_CMD_TX_START_Msk;
633 }
634
635
636 /*******************************************************************************
637 * Function Name: Cy_I2S_EnableRx
638 ****************************************************************************//**
639 *
640 * Starts an I2S reception. Interrupt enabling (by the
641 * \ref Cy_I2S_SetInterruptMask) is required after this function call, in case
642 * any I2S interrupts are used in the application.
643 *
644 * \pre \ref Cy_I2S_Init() must be called before.
645 *
646 * \param base The pointer to the I2S instance address.
647 *
648 * \funcusage
649 * \snippet i2s/snippet/main.c snippet_Cy_I2S_EnableRx
650 *
651 *******************************************************************************/
Cy_I2S_EnableRx(I2S_Type * base)652 __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base)
653 {
654 REG_I2S_CMD(base) |= I2S_CMD_RX_START_Msk;
655 }
656
657
658 /*******************************************************************************
659 * Function Name: Cy_I2S_DisableRx
660 ****************************************************************************//**
661 *
662 * Stops an I2S reception.
663 *
664 * \pre RX interrupt disabling (by the \ref Cy_I2S_SetInterruptMask) is required
665 * prior to this function call, in case any RX I2S interrupts are used.
666 *
667 * \param base The pointer to the I2S instance address.
668 *
669 * \funcusage
670 * \snippet i2s/snippet/main.c snippet_Cy_I2S_DisableRx
671 *
672 *******************************************************************************/
Cy_I2S_DisableRx(I2S_Type * base)673 __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base)
674 {
675 REG_I2S_CMD(base) &= (uint32_t) ~I2S_CMD_RX_START_Msk;
676 }
677
678
679 /*******************************************************************************
680 * Function Name: Cy_I2S_GetCurrentState
681 ****************************************************************************//**
682 *
683 * Returns the current I2S state (TX/RX running/paused/stopped).
684 *
685 * \param base The pointer to the I2S instance address.
686 *
687 * \return The current state \ref group_i2s_macros_current_state.
688 *
689 * \funcusage
690 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetCurrentState
691 *
692 *******************************************************************************/
Cy_I2S_GetCurrentState(I2S_Type const * base)693 __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base)
694 {
695 return (REG_I2S_CMD(base) & (I2S_CMD_TX_START_Msk | I2S_CMD_TX_PAUSE_Msk | I2S_CMD_RX_START_Msk));
696 }
697
698
699 /*******************************************************************************
700 * Function Name: Cy_I2S_ClearTxFifo
701 ****************************************************************************//**
702 *
703 * Clears the TX FIFO (resets the Read/Write FIFO pointers).
704 *
705 * \param base The pointer to the I2S instance address.
706 *
707 * \funcusage
708 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearTxFifo
709 *
710 *******************************************************************************/
Cy_I2S_ClearTxFifo(I2S_Type * base)711 __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base)
712 {
713 REG_I2S_TX_FIFO_CTL(base) |= I2S_TX_FIFO_CTL_CLEAR_Msk;
714 REG_I2S_TX_FIFO_CTL(base) &= (uint32_t) ~I2S_TX_FIFO_CTL_CLEAR_Msk;
715 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
716 (void) REG_I2S_TX_FIFO_CTL(base);
717 }
718
719
720 /*******************************************************************************
721 * Function Name: Cy_I2S_GetNumInTxFifo
722 ****************************************************************************//**
723 *
724 * Gets the number of used words in the TX FIFO.
725 *
726 * \param base The pointer to the I2S instance address.
727 *
728 * \return The current number of used words in the TX FIFO.
729 *
730 * \funcusage
731 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetNumInTxFifo
732 *
733 *******************************************************************************/
Cy_I2S_GetNumInTxFifo(I2S_Type const * base)734 __STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base)
735 {
736 return (_FLD2VAL(I2S_TX_FIFO_STATUS_USED, REG_I2S_TX_FIFO_STATUS(base)));
737 }
738
739
740 /*******************************************************************************
741 * Function Name: Cy_I2S_WriteTxData
742 ****************************************************************************//**
743 *
744 * Writes data to the TX FIFO. Increases the TX FIFO level.
745 *
746 * \param base The pointer to the I2S instance address.
747 *
748 * \param data Data to be written to the TX FIFO.
749 *
750 * \funcusage
751 * \snippet i2s/snippet/main.c snippet_Cy_I2S_WriteTxData
752 *
753 *******************************************************************************/
Cy_I2S_WriteTxData(I2S_Type * base,uint32_t data)754 __STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data)
755 {
756 REG_I2S_TX_FIFO_WR(base) = data;
757 }
758
759
760 /*******************************************************************************
761 * Function Name: Cy_I2S_GetTxReadPointer
762 ****************************************************************************//**
763 *
764 * Gets the TX FIFO Read pointer. This function is for debug purposes.
765 *
766 * \param base The pointer to the I2S instance address.
767 *
768 * \return The current TX Read pointer value.
769 *
770 * \funcusage
771 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetTxReadPointer
772 *
773 *******************************************************************************/
Cy_I2S_GetTxReadPointer(I2S_Type const * base)774 __STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base)
775 {
776 return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_RD_PTR, REG_I2S_TX_FIFO_STATUS(base)));
777 }
778
779
780 /*******************************************************************************
781 * Function Name: Cy_I2S_GetTxWritePointer
782 ****************************************************************************//**
783 *
784 * Gets the TX FIFO Write pointer. This function is for debug purposes.
785 *
786 * \param base The pointer to the I2S instance address.
787 *
788 * \return The current TX Write pointer value.
789 *
790 * \funcusage
791 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetTxWritePointer
792 *
793 *******************************************************************************/
Cy_I2S_GetTxWritePointer(I2S_Type const * base)794 __STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base)
795 {
796 return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_WR_PTR, REG_I2S_TX_FIFO_STATUS(base)));
797 }
798
799
800 /*******************************************************************************
801 * Function Name: Cy_I2S_FreezeTxFifo
802 ****************************************************************************//**
803 *
804 * Freezes the TX FIFO. This function is for debug purposes.
805 *
806 * \param base The pointer to the I2S instance address.
807 *
808 * \funcusage
809 * \snippet i2s/snippet/main.c snippet_Cy_I2S_FreezeTxFifo
810 *
811 *******************************************************************************/
Cy_I2S_FreezeTxFifo(I2S_Type * base)812 __STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base)
813 {
814 REG_I2S_TX_FIFO_CTL(base) |= I2S_TX_FIFO_CTL_FREEZE_Msk;
815 }
816
817
818 /*******************************************************************************
819 * Function Name: Cy_I2S_UnfreezeTxFifo
820 ****************************************************************************//**
821 *
822 * Unfreezes the TX FIFO. This function is for debug purposes.
823 *
824 * \param base The pointer to the I2S instance address.
825 *
826 * \funcusage
827 * \snippet i2s/snippet/main.c snippet_Cy_I2S_UnfreezeTxFifo
828 *
829 *******************************************************************************/
Cy_I2S_UnfreezeTxFifo(I2S_Type * base)830 __STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base)
831 {
832 REG_I2S_TX_FIFO_CTL(base) &= (uint32_t) ~I2S_TX_FIFO_CTL_FREEZE_Msk;
833 }
834
835
836 /*******************************************************************************
837 * Function Name: Cy_I2S_ClearRxFifo
838 ****************************************************************************//**
839 *
840 * Clears the RX FIFO (resets the Read/Write FIFO pointers).
841 *
842 * \param base The pointer to the I2S instance address.
843 *
844 * \funcusage
845 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearRxFifo
846 *
847 *******************************************************************************/
Cy_I2S_ClearRxFifo(I2S_Type * base)848 __STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base)
849 {
850 REG_I2S_RX_FIFO_CTL(base) |= I2S_RX_FIFO_CTL_CLEAR_Msk;
851 REG_I2S_RX_FIFO_CTL(base) &= (uint32_t) ~I2S_RX_FIFO_CTL_CLEAR_Msk;
852 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
853 (void) REG_I2S_RX_FIFO_CTL(base) ;
854 }
855
856
857 /*******************************************************************************
858 * Function Name: Cy_I2S_GetNumInRxFifo
859 ****************************************************************************//**
860 *
861 * Gets the number of used words in the RX FIFO.
862 *
863 * \param base The pointer to the I2S instance address.
864 *
865 * \return The current number of used words in rge RX FIFO.
866 *
867 * \funcusage
868 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetNumInRxFifo
869 *
870 *******************************************************************************/
Cy_I2S_GetNumInRxFifo(I2S_Type const * base)871 __STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base)
872 {
873 return (_FLD2VAL(I2S_RX_FIFO_STATUS_USED, REG_I2S_RX_FIFO_STATUS(base)));
874 }
875
876
877 /*******************************************************************************
878 * Function Name: Cy_I2S_ReadRxData
879 ****************************************************************************//**
880 *
881 * Reads data from the RX FIFO. Decreases the RX FIFO level.
882 *
883 * \param base The pointer to the I2S instance address.
884 *
885 * \return The read data.
886 *
887 * \funcusage
888 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ReadRxData
889 *
890 *******************************************************************************/
Cy_I2S_ReadRxData(I2S_Type const * base)891 __STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base)
892 {
893 return (REG_I2S_RX_FIFO_RD(base));
894 }
895
896
897 /*******************************************************************************
898 * Function Name: Cy_I2S_ReadRxDataSilent
899 ****************************************************************************//**
900 *
901 * Reads data from the RX FIFO without updating the RX FIFO read pointer.
902 * This function is for debug purposes.
903 *
904 * \param base The pointer to the I2S instance address.
905 *
906 * \return The read data.
907 *
908 * \funcusage
909 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ReadRxDataSilent
910 *
911 *******************************************************************************/
Cy_I2S_ReadRxDataSilent(I2S_Type const * base)912 __STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base)
913 {
914 return (REG_I2S_RX_FIFO_RD_SILENT(base));
915 }
916
917
918 /*******************************************************************************
919 * Function Name: Cy_I2S_GetRxReadPointer
920 ****************************************************************************//**
921 *
922 * Gets the RX FIFO Read pointer. This function is for debug purposes.
923 *
924 * \param base The pointer to the I2S instance address.
925 *
926 * \return The current RX Read pointer value.
927 *
928 * \funcusage
929 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetRxReadPointer
930 *
931 *******************************************************************************/
Cy_I2S_GetRxReadPointer(I2S_Type const * base)932 __STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base)
933 {
934 return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_RD_PTR, REG_I2S_RX_FIFO_STATUS(base)));
935 }
936
937
938 /*******************************************************************************
939 * Function Name: Cy_I2S_GetRxWritePointer
940 ****************************************************************************//**
941 *
942 * Gets the RX FIFO Write pointer. This function is for debug purposes.
943 *
944 * \param base The pointer to the I2S instance address.
945 *
946 * \return The current RX Write pointer value.
947 *
948 * \funcusage
949 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetRxWritePointer
950 *
951 *******************************************************************************/
Cy_I2S_GetRxWritePointer(I2S_Type const * base)952 __STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base)
953 {
954 return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_WR_PTR, REG_I2S_RX_FIFO_STATUS(base)));
955 }
956
957
958 /*******************************************************************************
959 * Function Name: Cy_I2S_FreezeRxFifo
960 ****************************************************************************//**
961 *
962 * Freezes the RX FIFO. This function is for debug purposes.
963 *
964 * \param base The pointer to the I2S instance address.
965 *
966 * \funcusage
967 * \snippet i2s/snippet/main.c snippet_Cy_I2S_FreezeRxFifo
968 *
969 *******************************************************************************/
Cy_I2S_FreezeRxFifo(I2S_Type * base)970 __STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base)
971 {
972 REG_I2S_RX_FIFO_CTL(base) |= I2S_RX_FIFO_CTL_FREEZE_Msk;
973 }
974
975
976 /*******************************************************************************
977 * Function Name: Cy_I2S_UnfreezeRxFifo
978 ****************************************************************************//**
979 *
980 * Unfreezes the RX FIFO. This function is for debug purposes.
981 *
982 * \param base The pointer to the I2S instance address.
983 *
984 * \funcusage
985 * \snippet i2s/snippet/main.c snippet_Cy_I2S_UnfreezeRxFifo
986 *
987 *******************************************************************************/
Cy_I2S_UnfreezeRxFifo(I2S_Type * base)988 __STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base)
989 {
990 REG_I2S_RX_FIFO_CTL(base) &= (uint32_t) ~I2S_RX_FIFO_CTL_FREEZE_Msk;
991 }
992
993
994 /*******************************************************************************
995 * Function Name: Cy_I2S_GetInterruptStatus
996 ****************************************************************************//**
997 *
998 * Gets an interrupt status (returns a content of the INTR register).
999 *
1000 * \param base The pointer to the I2S instance address.
1001 *
1002 * \return The interrupt bit mask \ref group_i2s_macros_interrupt_masks.
1003 *
1004 * \funcusage
1005 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetInterruptStatus
1006 *
1007 *******************************************************************************/
Cy_I2S_GetInterruptStatus(I2S_Type const * base)1008 __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base)
1009 {
1010 return (REG_I2S_INTR(base));
1011 }
1012
1013
1014 /*******************************************************************************
1015 * Function Name: Cy_I2S_ClearInterrupt
1016 ****************************************************************************//**
1017 *
1018 * Clears one or more interrupt factors (sets the INTR register).
1019 *
1020 * \param base The pointer to the I2S instance address.
1021 *
1022 * \param interrupt Interrupt bit mask \ref group_i2s_macros_interrupt_masks.
1023 *
1024 * \funcusage
1025 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearInterrupt
1026 *
1027 *******************************************************************************/
Cy_I2S_ClearInterrupt(I2S_Type * base,uint32_t interrupt)1028 __STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt)
1029 {
1030 CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt));
1031 REG_I2S_INTR(base) = interrupt;
1032 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
1033 (void) REG_I2S_INTR(base);
1034 }
1035
1036
1037 /*******************************************************************************
1038 * Function Name: Cy_I2S_SetInterrupt
1039 ****************************************************************************//**
1040 *
1041 * Sets one or more interrupt factors (sets the INTR_SET register).
1042 *
1043 * \param base The pointer to the I2S instance address.
1044 *
1045 * \param interrupt Interrupt bit mask \ref group_i2s_macros_interrupt_masks.
1046 *
1047 * \funcusage
1048 * \snippet i2s/snippet/main.c snippet_Cy_I2S_SetInterrupt
1049 *
1050 *******************************************************************************/
Cy_I2S_SetInterrupt(I2S_Type * base,uint32_t interrupt)1051 __STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt)
1052 {
1053 CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt));
1054 REG_I2S_INTR_SET(base) = interrupt;
1055 }
1056
1057
1058 /*******************************************************************************
1059 * Function Name: Cy_I2S_GetInterruptMask
1060 ****************************************************************************//**
1061 *
1062 * Returns the interrupt mask (a content of the INTR_MASK register).
1063 *
1064 * \param base The pointer to the I2S instance address.
1065 *
1066 * \return The interrupt bit mask \ref group_i2s_macros_interrupt_masks.
1067 *
1068 * \funcusage
1069 * \snippet i2s/snippet/main.c snippet_Cy_I2S_GetInterruptMask
1070 *
1071 *******************************************************************************/
Cy_I2S_GetInterruptMask(I2S_Type const * base)1072 __STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base)
1073 {
1074 return (REG_I2S_INTR_MASK(base));
1075 }
1076
1077
1078 /*******************************************************************************
1079 * Function Name: Cy_I2S_SetInterruptMask
1080 ****************************************************************************//**
1081 *
1082 * Sets one or more interrupt factor masks (the INTR_MASK register).
1083 *
1084 * \param base The pointer to the I2S instance address.
1085 *
1086 * \param interrupt Interrupt bit mask \ref group_i2s_macros_interrupt_masks.
1087 *
1088 * \funcusage
1089 * \snippet i2s/snippet/main.c snippet_Cy_I2S_SetInterruptMask
1090 *
1091 *******************************************************************************/
Cy_I2S_SetInterruptMask(I2S_Type * base,uint32_t interrupt)1092 __STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt)
1093 {
1094 CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt));
1095 REG_I2S_INTR_MASK(base) = interrupt;
1096 }
1097
1098
1099 /*******************************************************************************
1100 * Function Name: Cy_I2S_GetInterruptStatusMasked
1101 ****************************************************************************//**
1102 *
1103 * Returns the interrupt status masked (a content of the INTR_MASKED register).
1104 *
1105 * \param base The pointer to the I2S instance address.
1106 *
1107 * \return The interrupt bit mask(s) \ref group_i2s_macros_interrupt_masks.
1108 *
1109 * \funcusage
1110 * \snippet i2s/snippet/main.c snippet_Cy_I2S_ClearInterrupt
1111 *
1112 *******************************************************************************/
Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base)1113 __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base)
1114 {
1115 return (REG_I2S_INTR_MASKED(base));
1116 }
1117
1118 /** \} group_i2s_functions */
1119
1120 #ifdef __cplusplus
1121 }
1122 #endif
1123
1124 #endif /* CY_IP_MXAUDIOSS */
1125
1126 #endif /* CY_I2S_H */
1127
1128 /** \} group_i2s */
1129
1130
1131 /* [] END OF FILE */
1132
