1 /*! 2 \file gd32f3x0_rtc.h 3 \brief definitions for the RTC 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_RTC_H 38 #define GD32F3X0_RTC_H 39 40 #include "gd32f3x0.h" 41 42 /* RTC definitions */ 43 #define RTC RTC_BASE 44 45 /* registers definitions */ 46 #define RTC_TIME REG32(RTC + 0x00000000U) /*!< RTC time of day register */ 47 #define RTC_DATE REG32(RTC + 0x00000004U) /*!< RTC date register */ 48 #define RTC_CTL REG32(RTC + 0x00000008U) /*!< RTC control register */ 49 #define RTC_STAT REG32(RTC + 0x0000000CU) /*!< RTC status register */ 50 #define RTC_PSC REG32(RTC + 0x00000010U) /*!< RTC time prescaler register */ 51 #define RTC_ALRM0TD REG32(RTC + 0x0000001CU) /*!< RTC alarm 0 time and date register */ 52 #define RTC_WPK REG32(RTC + 0x00000024U) /*!< RTC write protection key register */ 53 #define RTC_SS REG32(RTC + 0x00000028U) /*!< RTC sub second register */ 54 #define RTC_SHIFTCTL REG32(RTC + 0x0000002CU) /*!< RTC shift function control register */ 55 #define RTC_TTS REG32(RTC + 0x00000030U) /*!< RTC time of timestamp register */ 56 #define RTC_DTS REG32(RTC + 0x00000034U) /*!< RTC date of timestamp register */ 57 #define RTC_SSTS REG32(RTC + 0x00000038U) /*!< RTC sub second of timestamp register */ 58 #define RTC_HRFC REG32(RTC + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ 59 #define RTC_TAMP REG32(RTC + 0x00000040U) /*!< RTC tamper register */ 60 #define RTC_ALRM0SS REG32(RTC + 0x00000044U) /*!< RTC alarm 0 sub second register */ 61 #define RTC_BKP0 REG32(RTC + 0x00000050U) /*!< RTC backup 0 register */ 62 #define RTC_BKP1 REG32(RTC + 0x00000054U) /*!< RTC backup 1 register */ 63 #define RTC_BKP2 REG32(RTC + 0x00000058U) /*!< RTC backup 2 register */ 64 #define RTC_BKP3 REG32(RTC + 0x0000005CU) /*!< RTC backup 3 register */ 65 #define RTC_BKP4 REG32(RTC + 0x00000060U) /*!< RTC backup 4 register */ 66 67 /* bits definitions */ 68 /* RTC_TIME */ 69 #define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ 70 #define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ 71 #define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ 72 #define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ 73 #define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ 74 #define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ 75 #define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ 76 77 /* RTC_DATE */ 78 #define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ 79 #define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ 80 #define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ 81 #define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ 82 #define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ 83 #define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ 84 #define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ 85 86 /* RTC_CTL */ 87 #define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ 88 #define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ 89 #define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ 90 #define RTC_CTL_CS BIT(6) /*!< display format of clock system */ 91 #define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ 92 #define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ 93 #define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ 94 #define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ 95 #define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ 96 #define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ 97 #define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ 98 #define RTC_CTL_COS BIT(19) /*!< calibration output selection */ 99 #define RTC_CTL_OPOL BIT(20) /*!< output polarity */ 100 #define RTC_CTL_OS BITS(21,22) /*!< output selection */ 101 #define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ 102 103 /* RTC_STAT */ 104 #define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ 105 #define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ 106 #define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ 107 #define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ 108 #define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ 109 #define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ 110 #define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ 111 #define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ 112 #define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ 113 #define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ 114 #define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ 115 #define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ 116 117 /* RTC_PSC */ 118 #define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ 119 #define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ 120 121 /* RTC_ALRM0TD */ 122 #define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ 123 #define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ 124 #define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ 125 #define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ 126 #define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ 127 #define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ 128 #define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ 129 #define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ 130 #define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ 131 #define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ 132 #define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ 133 #define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ 134 #define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ 135 #define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ 136 137 /* RTC_WPK */ 138 #define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ 139 140 /* RTC_SS */ 141 #define RTC_SS_SSC BITS(0,15) /*!< sub second value */ 142 143 /* RTC_SHIFTCTL */ 144 #define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ 145 #define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ 146 147 /* RTC_TTS */ 148 #define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ 149 #define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ 150 #define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ 151 #define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ 152 #define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ 153 #define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ 154 #define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ 155 156 /* RTC_DTS */ 157 #define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ 158 #define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ 159 #define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ 160 #define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ 161 #define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ 162 163 /* RTC_SSTS */ 164 #define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ 165 166 /* RTC_HRFC */ 167 #define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ 168 #define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ 169 #define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ 170 #define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ 171 172 /* RTC_TAMP */ 173 #define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ 174 #define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ 175 #define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ 176 #define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ 177 #define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ 178 #define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ 179 #define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ 180 #define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ 181 #define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ 182 #define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ 183 #define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ 184 #define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ 185 #define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ 186 #define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ 187 #define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ 188 #define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ 189 190 /* RTC_ALRM0SS */ 191 #define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ 192 #define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ 193 194 /* RTC_BKP0 */ 195 #define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ 196 197 /* RTC_BKP1 */ 198 #define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ 199 200 /* RTC_BKP2 */ 201 #define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ 202 203 /* RTC_BKP3 */ 204 #define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ 205 206 /* RTC_BKP4 */ 207 #define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ 208 209 /* constants definitions */ 210 /* structure for initialization of the RTC */ 211 typedef struct 212 { 213 uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ 214 uint8_t rtc_month; /*!< RTC month value */ 215 uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ 216 uint8_t rtc_day_of_week; /*!< RTC weekday value */ 217 uint8_t rtc_hour; /*!< RTC hour value */ 218 uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ 219 uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ 220 uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ 221 uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ 222 uint32_t rtc_am_pm; /*!< RTC AM/PM value */ 223 uint32_t rtc_display_format; /*!< RTC time notation */ 224 }rtc_parameter_struct; 225 226 /* structure for RTC alarm configuration */ 227 typedef struct 228 { 229 uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ 230 uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ 231 uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ 232 uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ 233 uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ 234 uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ 235 uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ 236 }rtc_alarm_struct; 237 238 /* structure for RTC time-stamp configuration */ 239 typedef struct 240 { 241 uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ 242 uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ 243 uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ 244 uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ 245 uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ 246 uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ 247 uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ 248 }rtc_timestamp_struct; 249 250 /* structure for RTC tamper configuration */ 251 typedef struct 252 { 253 uint32_t rtc_tamper_source; /*!< RTC tamper source */ 254 uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ 255 uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ 256 uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ 257 ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ 258 uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ 259 ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ 260 }rtc_tamper_struct; 261 262 /* time register value */ 263 #define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ 264 #define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ 265 266 #define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ 267 #define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ 268 269 #define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ 270 #define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ 271 272 #define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ 273 #define RTC_PM RTC_TIME_PM /*!< PM format */ 274 275 /* date register value */ 276 #define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ 277 #define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ 278 279 #define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ 280 #define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ 281 #define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ 282 #define RTC_FEB ((uint8_t)0x02U) /*!< February */ 283 #define RTC_MAR ((uint8_t)0x03U) /*!< March */ 284 #define RTC_APR ((uint8_t)0x04U) /*!< April */ 285 #define RTC_MAY ((uint8_t)0x05U) /*!< May */ 286 #define RTC_JUN ((uint8_t)0x06U) /*!< June */ 287 #define RTC_JUL ((uint8_t)0x07U) /*!< July */ 288 #define RTC_AUG ((uint8_t)0x08U) /*!< August */ 289 #define RTC_SEP ((uint8_t)0x09U) /*!< September */ 290 #define RTC_OCT ((uint8_t)0x10U) /*!< October */ 291 #define RTC_NOV ((uint8_t)0x11U) /*!< November */ 292 #define RTC_DEC ((uint8_t)0x12U) /*!< December */ 293 294 #define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ 295 #define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ 296 #define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ 297 #define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ 298 #define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ 299 #define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ 300 #define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ 301 #define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ 302 #define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ 303 304 #define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ 305 #define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ 306 307 /* ctl register value */ 308 #define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ 309 #define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ 310 #define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ 311 312 #define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ 313 #define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS /*!< calibration output of 1Hz is enable */ 314 #define RTC_ALARM_HIGH RTC_OS_ENABLE /*!< enable alarm flag output with high level */ 315 #define RTC_ALARM_LOW RTC_OS_ENABLE | RTC_CTL_OPOL /*!< enable alarm flag output with low level*/ 316 317 #define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ 318 #define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ 319 320 #define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ 321 #define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ 322 323 /* psc register value */ 324 #define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ 325 #define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ 326 327 #define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ 328 #define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ 329 330 /* alrm0td register value */ 331 #define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ 332 #define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ 333 334 #define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ 335 #define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ 336 337 #define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ 338 #define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ 339 340 #define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ 341 #define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ 342 343 #define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ 344 #define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ 345 #define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ 346 #define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ 347 #define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ 348 #define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ 349 350 #define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ 351 #define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ 352 353 /* wpk register value */ 354 #define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ 355 356 /* ss register value */ 357 #define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ 358 359 /* shiftctl register value */ 360 #define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ 361 362 #define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ 363 #define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ 364 365 /* tts register value */ 366 #define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ 367 #define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ 368 369 #define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ 370 #define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ 371 372 #define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ 373 #define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ 374 375 /* dts register value */ 376 #define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ 377 #define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ 378 379 #define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ 380 #define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ 381 382 #define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ 383 #define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ 384 385 /* ssts register value */ 386 #define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ 387 388 /* hrfc register value */ 389 #define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ 390 391 #define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ 392 #define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ 393 #define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ 394 395 #define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ 396 #define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ 397 398 /* tamp register value */ 399 #define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ 400 #define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ 401 #define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ 402 #define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ 403 #define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ 404 #define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ 405 #define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ 406 #define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ 407 #define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ 408 409 #define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ 410 #define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ 411 #define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ 412 #define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ 413 #define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ 414 415 #define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ 416 #define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ 417 #define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ 418 #define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ 419 #define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ 420 421 #define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ 422 #define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ 423 424 #define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ 425 #define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ 426 #define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ 427 #define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ 428 429 #define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ 430 431 #define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ 432 #define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ 433 434 /* alrm0ss register value */ 435 #define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ 436 437 #define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ 438 #define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ 439 #define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ 440 #define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ 441 #define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ 442 #define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ 443 #define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ 444 #define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ 445 #define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ 446 #define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ 447 #define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ 448 #define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ 449 #define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ 450 #define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ 451 #define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ 452 #define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ 453 #define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ 454 455 /* RTC interrupt source */ 456 #define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ 457 #define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ 458 #define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ 459 460 /* write protect key */ 461 #define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ 462 #define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ 463 #define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ 464 465 /* registers reset value */ 466 #define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ 467 #define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ 468 #define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ 469 #define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ 470 471 /* RTC timeout value */ 472 #define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ 473 #define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ 474 #define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ 475 #define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ 476 #define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ 477 478 /* RTC flag */ 479 #define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ 480 #define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ 481 #define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ 482 #define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ 483 #define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ 484 #define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ 485 #define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ 486 #define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ 487 #define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ 488 #define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ 489 #define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ 490 491 /* function declarations */ 492 /* reset most of the RTC registers */ 493 ErrStatus rtc_deinit(void); 494 /* initialize RTC registers */ 495 ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); 496 /* enter RTC init mode */ 497 ErrStatus rtc_init_mode_enter(void); 498 /* exit RTC init mode */ 499 void rtc_init_mode_exit(void); 500 /* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ 501 ErrStatus rtc_register_sync_wait(void); 502 503 /* get current time and date */ 504 void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); 505 /* get current subsecond value */ 506 uint32_t rtc_subsecond_get(void); 507 508 /* configure RTC alarm */ 509 void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time); 510 /* configure subsecond of RTC alarm */ 511 void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); 512 /* get RTC alarm */ 513 void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time); 514 /* get RTC alarm subsecond */ 515 uint32_t rtc_alarm_subsecond_get(void); 516 /* enable RTC alarm */ 517 void rtc_alarm_enable(void); 518 /* disable RTC alarm */ 519 ErrStatus rtc_alarm_disable(void); 520 521 /* enable RTC time-stamp */ 522 void rtc_timestamp_enable(uint32_t edge); 523 /* disable RTC time-stamp */ 524 void rtc_timestamp_disable(void); 525 /* get RTC timestamp time and date */ 526 void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); 527 /* get RTC time-stamp subsecond */ 528 uint32_t rtc_timestamp_subsecond_get(void); 529 530 /* enable RTC tamper */ 531 void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); 532 /* disable RTC tamper */ 533 void rtc_tamper_disable(uint32_t source); 534 535 /* enable specified RTC interrupt */ 536 void rtc_interrupt_enable(uint32_t interrupt); 537 /* disble specified RTC interrupt */ 538 void rtc_interrupt_disable(uint32_t interrupt); 539 /* check specified flag */ 540 FlagStatus rtc_flag_get(uint32_t flag); 541 /* clear specified flag */ 542 void rtc_flag_clear(uint32_t flag); 543 544 /* configure RTC alternate output source */ 545 void rtc_alter_output_config(uint32_t source, uint32_t mode); 546 /* configure RTC calibration register */ 547 ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); 548 /* ajust the daylight saving time by adding or substracting one hour from the current time */ 549 void rtc_hour_adjust(uint32_t operation); 550 /* ajust RTC second or subsecond value of current time */ 551 ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); 552 /* enable RTC bypass shadow registers function */ 553 void rtc_bypass_shadow_enable(void); 554 /* disable RTC bypass shadow registers function */ 555 void rtc_bypass_shadow_disable(void); 556 /* enable RTC reference clock detection function */ 557 ErrStatus rtc_refclock_detection_enable(void); 558 /* disable RTC reference clock detection function */ 559 ErrStatus rtc_refclock_detection_disable(void); 560 561 #endif /* GD32F3X0_RTC_H */ 562
