1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include "esp_rom_sys.h"
9 #include "soc/rtc.h"
10 #include "soc/rtc_cntl_reg.h"
11 #include "hal/clk_tree_ll.h"
12 #include "hal/rtc_cntl_ll.h"
13 #include "soc/timer_group_reg.h"
14
15 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
16 * This feature counts the number of XTAL clock cycles within a given number of
17 * RTC_SLOW_CLK cycles.
18 *
19 * Slow clock calibration feature has two modes of operation: one-off and cycling.
20 * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
21 * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
22 * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
23 * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
24 * enabled using TIMG_RTC_CALI_START bit.
25 */
26
27 /**
28 * @brief One-off clock calibration function used by rtc_clk_cal_internal
29 * @param cal_clk which clock to calibrate
30 * @param slowclk_cycles number of slow clock cycles to count
31 * @return number of XTAL clock cycles within the given number of slow clock cycles
32 */
rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)33 static uint32_t rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
34 {
35 /* There may be another calibration process already running during we call this function,
36 * so we should wait the last process is done.
37 */
38 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
39 /**
40 * Set a small timeout threshold to accelerate the generation of timeout.
41 * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
42 */
43 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
44 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
45 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
46 }
47
48 /* Prepare calibration */
49 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
50 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
51 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
52 /* Figure out how long to wait for calibration to finish */
53
54 /* Set timeout reg and expect time delay*/
55 uint32_t expected_freq;
56 if (cal_clk == RTC_CAL_32K_XTAL) {
57 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
58 expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
59 } else if (cal_clk == RTC_CAL_8MD256) {
60 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
61 expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
62 } else {
63 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(slowclk_cycles));
64 expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
65 }
66 uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
67 /* Start calibration */
68 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
69 SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
70
71 /* Wait for calibration to finish up to another us_time_estimate */
72 esp_rom_delay_us(us_time_estimate);
73 uint32_t cal_val;
74 while (true) {
75 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
76 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
77 break;
78 }
79 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
80 cal_val = 0;
81 break;
82 }
83 }
84
85 return cal_val;
86 }
87
88 /**
89 * @brief Cycling clock calibration function used by rtc_clk_cal_internal
90 * @param cal_clk which clock to calibrate
91 * @param slowclk_cycles number of slow clock cycles to count
92 * @return number of XTAL clock cycles within the given number of slow clock cycles
93 */
rtc_clk_cal_internal_cycling(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)94 static uint32_t rtc_clk_cal_internal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
95 {
96 /* Get which slowclk is in calibration and max cali cycles */
97 rtc_cal_sel_t in_calibration_clk;
98 in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL);
99 uint32_t cali_slowclk_cycles = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX);
100 /* If no calibration in process or calibration period equal to 0, use slowclk_cycles cycles to calibrate slowclk */
101 if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING) || in_calibration_clk != cal_clk) {
102 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
103 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
104 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
105 SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
106 cali_slowclk_cycles = slowclk_cycles;
107 }
108
109 /* Wait for calibration finished */
110 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_CYCLING_DATA_VLD));
111 uint32_t cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
112
113 return cal_val;
114 }
115
116 /**
117 * @brief Slowclk period calculating funtion used by rtc_clk_cal and rtc_clk_cal_cycling
118 * @param xtal_cycles number of xtal cycles count
119 * @param slowclk_cycles number of slow clock cycles to count
120 * @return slow clock period
121 */
rtc_clk_xtal_to_slowclk(uint64_t xtal_cycles,uint32_t slowclk_cycles)122 static uint32_t rtc_clk_xtal_to_slowclk(uint64_t xtal_cycles, uint32_t slowclk_cycles)
123 {
124 assert(slowclk_cycles);
125 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
126 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
127 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
128 uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
129 return period;
130 }
131
132 /**
133 * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
134 * @param cal_clk which clock to calibrate
135 * @param slowclk_cycles number of slow clock cycles to count
136 * @return number of XTAL clock cycles within the given number of slow clock cycles
137 */
rtc_clk_cal_internal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles,uint32_t cal_mode)138 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, uint32_t cal_mode)
139 {
140 /* On ESP32S2, choosing RTC_CAL_RTC_MUX results in calibration of
141 * the 90k RTC clock regardless of the currenlty selected SLOW_CLK.
142 * On the ESP32, it used the currently selected SLOW_CLK.
143 * The following code emulates ESP32 behavior:
144 */
145 if (cal_clk == RTC_CAL_RTC_MUX) {
146 soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
147 if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
148 cal_clk = RTC_CAL_32K_XTAL;
149 } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
150 cal_clk = RTC_CAL_8MD256;
151 }
152 } else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
153 cal_clk = RTC_CAL_RTC_MUX;
154 }
155
156 /* Enable requested clock (90k clock is always on) */
157 bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
158 if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
159 clk_ll_xtal32k_digi_enable();
160 }
161
162 bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
163 bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
164 if (cal_clk == RTC_CAL_8MD256) {
165 rtc_clk_8m_enable(true, true);
166 clk_ll_rc_fast_d256_digi_enable();
167 }
168
169 uint32_t cal_val;
170 if (cal_mode == RTC_TIME_CAL_ONEOFF_MODE) {
171 cal_val = rtc_clk_cal_internal_oneoff(cal_clk, slowclk_cycles);
172 } else {
173 cal_val = rtc_clk_cal_internal_cycling(cal_clk, slowclk_cycles);
174 }
175
176 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
177
178 /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
179 if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
180 clk_ll_xtal32k_digi_disable();
181 }
182
183 if (cal_clk == RTC_CAL_8MD256) {
184 clk_ll_rc_fast_d256_digi_disable();
185 rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
186 }
187
188 return cal_val;
189 }
190
rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)191 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
192 {
193 assert(slowclk_cycles);
194 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
195 uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
196 uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
197 return ratio;
198 }
199
rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq,uint32_t slowclk_cycles,uint64_t actual_xtal_cycles)200 static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
201 {
202 uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
203 uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
204 return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
205 }
206
rtc_clk_cal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)207 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
208 {
209 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
210
211 if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) {
212 return 0;
213 }
214
215 return rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles);
216 }
217
rtc_clk_cal_cycling(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)218 uint32_t rtc_clk_cal_cycling(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
219 {
220 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_CYCLING_MODE);
221 uint32_t period = rtc_clk_xtal_to_slowclk(xtal_cycles, slowclk_cycles);
222 return period;
223 }
224
rtc_time_us_to_slowclk(uint64_t time_in_us,uint32_t period)225 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
226 {
227 assert(period);
228 /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
229 * TODO: fix overflow.
230 */
231 return (time_in_us << RTC_CLK_CAL_FRACT) / period;
232 }
233
rtc_time_slowclk_to_us(uint64_t rtc_cycles,uint32_t period)234 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
235 {
236 return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
237 }
238
rtc_time_get(void)239 uint64_t rtc_time_get(void)
240 {
241 return rtc_cntl_ll_get_rtc_time();
242 }
243
rtc_clk_wait_for_slow_cycle(void)244 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
245 {
246 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
247 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
248 esp_rom_delay_us(1);
249 }
250 }
251
rtc_clk_freq_cal(uint32_t cal_val)252 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
253 {
254 if (cal_val == 0) {
255 return 0; // cal_val will be denominator, return 0 as the symbol of failure.
256 }
257 return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
258 }
259
