1/*
2 * Copyright (c) 2023 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8
9/ {
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13
14		cpu0: cpu@0 {
15			device_type = "cpu";
16			compatible = "cdns,tensilica-xtensa-lx3";
17			reg = <0>;
18		};
19	};
20
21	/*
22	 * Although RAM is of size 128MB (0x08000000), limit this to 16MB so
23	 * fewer L2 page table entries are needed when MMU is enabled.
24	 */
25	sram0: memory@0 {
26		device_type = "memory";
27		compatible = "mmio-sram";
28		reg = <0x00000000 0x01000000>;
29	};
30
31	/*
32	 * Although ROM is of size 32MB (0x02000000), limit this to 16KB so
33	 * fewer L2 page table entries are needed when MMU is enabled.
34	 */
35	rom0: memory@fe000000 {
36		device_type = "memory";
37		compatible = "mmio-sram";
38		reg = <0xfe000000 0x00004000>;
39	};
40
41	soc {
42		#address-cells = <1>;
43		#size-cells = <1>;
44		compatible = "simple-bus";
45		ranges;
46
47	};
48};
49