1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdlib.h>
15 #include <string.h>
16 #include <sys/lock.h>
17 #include <sys/cdefs.h>
18 #include "esp_compiler.h"
19 #include "esp_intr_alloc.h"
20 #include "esp_log.h"
21 #include "driver/gpio.h"
22 #include "driver/periph_ctrl.h"
23 #include "driver/rmt.h"
24 #include "freertos/FreeRTOS.h"
25 #include "freertos/task.h"
26 #include "freertos/semphr.h"
27 #include "freertos/ringbuf.h"
28 #include "soc/soc_memory_layout.h"
29 #include "soc/rmt_periph.h"
30 #include "soc/rtc.h"
31 #include "hal/rmt_hal.h"
32 #include "hal/rmt_ll.h"
33 #include "hal/gpio_hal.h"
34 #include "esp_rom_gpio.h"
35 
36 #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
37 #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
38 #define RMT_MEM_CNT_ERROR_STR "RMT MEM BLOCK NUM ERR"
39 #define RMT_CARRIER_ERROR_STR "RMT CARRIER LEVEL ERR"
40 #define RMT_MEM_OWNER_ERROR_STR "RMT MEM OWNER_ERR"
41 #define RMT_BASECLK_ERROR_STR "RMT BASECLK ERR"
42 #define RMT_WR_MEM_OVF_ERROR_STR "RMT WR MEM OVERFLOW"
43 #define RMT_GPIO_ERROR_STR "RMT GPIO ERROR"
44 #define RMT_MODE_ERROR_STR "RMT MODE ERROR"
45 #define RMT_CLK_DIV_ERROR_STR "RMT CLK DIV ERR"
46 #define RMT_DRIVER_ERROR_STR "RMT DRIVER ERR"
47 #define RMT_DRIVER_LENGTH_ERROR_STR "RMT PARAM LEN ERROR"
48 #define RMT_PSRAM_BUFFER_WARN_STR "Using buffer allocated from psram"
49 #define RMT_TRANSLATOR_NULL_STR "RMT translator is null"
50 #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init"
51 #define RMT_PARAM_ERR_STR "RMT param error"
52 
53 static const char *RMT_TAG = "rmt";
54 #define RMT_CHECK(a, str, ret_val, ...)                                          \
55     if (unlikely(!(a))) {                                                        \
56         ESP_LOGE(RMT_TAG, "%s(%d): "str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
57         return (ret_val);                                                        \
58     }
59 
60 // Spinlock for protecting concurrent register-level access only
61 #define RMT_ENTER_CRITICAL()  portENTER_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
62 #define RMT_EXIT_CRITICAL()   portEXIT_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
63 
64 #define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_NUM-SOC_RMT_TX_CHANNELS_NUM)
65 #define RMT_TX_CHANNEL_ENCODING_END   (SOC_RMT_TX_CHANNELS_NUM-1)
66 
67 #define RMT_IS_RX_CHANNEL(channel) ((channel) >= RMT_RX_CHANNEL_ENCODING_START)
68 #define RMT_IS_TX_CHANNEL(channel) ((channel) <= RMT_TX_CHANNEL_ENCODING_END)
69 #define RMT_DECODE_RX_CHANNEL(encode_chan) ((encode_chan - RMT_RX_CHANNEL_ENCODING_START))
70 #define RMT_ENCODE_RX_CHANNEL(decode_chan) ((decode_chan + RMT_RX_CHANNEL_ENCODING_START))
71 
72 typedef struct {
73     rmt_hal_context_t hal;
74     _lock_t rmt_driver_isr_lock;
75     portMUX_TYPE rmt_spinlock; // Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
76     rmt_isr_handle_t rmt_driver_intr_handle;
77     rmt_tx_end_callback_t rmt_tx_end_callback;// Event called when transmission is ended
78     uint8_t rmt_driver_channels; // Bitmask of installed drivers' channels
79     bool rmt_module_enabled;
80 } rmt_contex_t;
81 
82 typedef struct {
83     size_t tx_offset;
84     size_t tx_len_rem;
85     size_t tx_sub_len;
86     bool translator;
87     bool wait_done; //Mark whether wait tx done.
88     rmt_channel_t channel;
89     const rmt_item32_t *tx_data;
90     xSemaphoreHandle tx_sem;
91 #if CONFIG_SPIRAM_USE_MALLOC
92     int intr_alloc_flags;
93     StaticSemaphore_t tx_sem_buffer;
94 #endif
95     rmt_item32_t *tx_buf;
96     RingbufHandle_t rx_buf;
97 #if SOC_RMT_SUPPORT_RX_PINGPONG
98     rmt_item32_t *rx_item_buf;
99     uint32_t rx_item_buf_size;
100     uint32_t rx_item_len;
101     int rx_item_start_idx;
102 #endif
103     sample_to_rmt_t sample_to_rmt;
104     void *tx_context;
105     size_t sample_size_remain;
106     const uint8_t *sample_cur;
107 } rmt_obj_t;
108 
109 static rmt_contex_t rmt_contex = {
110     .hal.regs = RMT_LL_HW_BASE,
111     .hal.mem = RMT_LL_MEM_BASE,
112     .rmt_spinlock = portMUX_INITIALIZER_UNLOCKED,
113     .rmt_driver_intr_handle = NULL,
114     .rmt_tx_end_callback = {
115         .function = NULL,
116     },
117     .rmt_driver_channels = 0,
118     .rmt_module_enabled = false,
119 };
120 
121 static rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0};
122 
123 #if SOC_RMT_SOURCE_CLK_INDEPENDENT
124 static uint32_t s_rmt_source_clock_hz[RMT_CHANNEL_MAX];
125 #else
126 static uint32_t s_rmt_source_clock_hz;
127 #endif
128 
129 //Enable RMT module
rmt_module_enable(void)130 static void rmt_module_enable(void)
131 {
132     RMT_ENTER_CRITICAL();
133     if (rmt_contex.rmt_module_enabled == false) {
134         periph_module_reset(rmt_periph_signals.module);
135         periph_module_enable(rmt_periph_signals.module);
136         rmt_contex.rmt_module_enabled = true;
137     }
138     RMT_EXIT_CRITICAL();
139 }
140 
141 //Disable RMT module
rmt_module_disable(void)142 static void rmt_module_disable(void)
143 {
144     RMT_ENTER_CRITICAL();
145     if (rmt_contex.rmt_module_enabled == true) {
146         periph_module_disable(rmt_periph_signals.module);
147         rmt_contex.rmt_module_enabled = false;
148     }
149     RMT_EXIT_CRITICAL();
150 }
151 
rmt_set_clk_div(rmt_channel_t channel,uint8_t div_cnt)152 esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
153 {
154     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
155     RMT_ENTER_CRITICAL();
156     if (RMT_IS_RX_CHANNEL(channel)) {
157         rmt_ll_rx_set_counter_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt);
158     } else {
159         rmt_ll_tx_set_counter_clock_div(rmt_contex.hal.regs, channel, div_cnt);
160     }
161     RMT_EXIT_CRITICAL();
162     return ESP_OK;
163 }
164 
rmt_get_clk_div(rmt_channel_t channel,uint8_t * div_cnt)165 esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt)
166 {
167     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
168     RMT_CHECK(div_cnt != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
169     RMT_ENTER_CRITICAL();
170     if (RMT_IS_RX_CHANNEL(channel)) {
171         *div_cnt = (uint8_t)rmt_ll_rx_get_counter_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
172     } else {
173         *div_cnt = (uint8_t)rmt_ll_tx_get_counter_clock_div(rmt_contex.hal.regs, channel);
174     }
175     RMT_EXIT_CRITICAL();
176     return ESP_OK;
177 }
178 
rmt_set_rx_idle_thresh(rmt_channel_t channel,uint16_t thresh)179 esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
180 {
181     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
182     RMT_ENTER_CRITICAL();
183     rmt_ll_rx_set_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
184     RMT_EXIT_CRITICAL();
185     return ESP_OK;
186 }
187 
rmt_get_rx_idle_thresh(rmt_channel_t channel,uint16_t * thresh)188 esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
189 {
190     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
191     RMT_CHECK(thresh != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
192     RMT_ENTER_CRITICAL();
193     *thresh = (uint16_t)rmt_ll_rx_get_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
194     RMT_EXIT_CRITICAL();
195     return ESP_OK;
196 }
197 
rmt_set_mem_block_num(rmt_channel_t channel,uint8_t rmt_mem_num)198 esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
199 {
200     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
201     RMT_CHECK(rmt_mem_num <= RMT_CHANNEL_MAX - channel, RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
202     RMT_ENTER_CRITICAL();
203     if (RMT_IS_RX_CHANNEL(channel)) {
204         rmt_ll_rx_set_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rmt_mem_num);
205     } else {
206         rmt_ll_tx_set_mem_blocks(rmt_contex.hal.regs, channel, rmt_mem_num);
207     }
208     RMT_EXIT_CRITICAL();
209     return ESP_OK;
210 }
211 
rmt_get_mem_block_num(rmt_channel_t channel,uint8_t * rmt_mem_num)212 esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num)
213 {
214     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
215     RMT_CHECK(rmt_mem_num != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
216     RMT_ENTER_CRITICAL();
217     if (RMT_IS_RX_CHANNEL(channel)) {
218         *rmt_mem_num = (uint8_t)rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
219     } else {
220         *rmt_mem_num = (uint8_t)rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
221     }
222     RMT_EXIT_CRITICAL();
223     return ESP_OK;
224 }
225 
rmt_set_tx_carrier(rmt_channel_t channel,bool carrier_en,uint16_t high_level,uint16_t low_level,rmt_carrier_level_t carrier_level)226 esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level,
227                              rmt_carrier_level_t carrier_level)
228 {
229     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
230     RMT_CHECK(carrier_level < RMT_CARRIER_LEVEL_MAX, RMT_CARRIER_ERROR_STR, ESP_ERR_INVALID_ARG);
231     RMT_ENTER_CRITICAL();
232     rmt_ll_tx_set_carrier_high_low_ticks(rmt_contex.hal.regs, channel, high_level, low_level);
233     rmt_ll_tx_set_carrier_level(rmt_contex.hal.regs, channel, carrier_level);
234     rmt_ll_tx_enable_carrier_modulation(rmt_contex.hal.regs, channel, carrier_en);
235     RMT_EXIT_CRITICAL();
236     return ESP_OK;
237 }
238 
rmt_set_mem_pd(rmt_channel_t channel,bool pd_en)239 esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
240 {
241     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
242     RMT_ENTER_CRITICAL();
243     rmt_ll_power_down_mem(rmt_contex.hal.regs, pd_en);
244     RMT_EXIT_CRITICAL();
245     return ESP_OK;
246 }
247 
rmt_get_mem_pd(rmt_channel_t channel,bool * pd_en)248 esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
249 {
250     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
251     RMT_ENTER_CRITICAL();
252     *pd_en = rmt_ll_is_mem_power_down(rmt_contex.hal.regs);
253     RMT_EXIT_CRITICAL();
254     return ESP_OK;
255 }
256 
rmt_tx_start(rmt_channel_t channel,bool tx_idx_rst)257 esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
258 {
259     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
260     RMT_ENTER_CRITICAL();
261     if (tx_idx_rst) {
262         rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
263     }
264     rmt_ll_clear_tx_end_interrupt(rmt_contex.hal.regs, channel);
265     // enable tx end interrupt in non-loop mode
266     if (!rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel)) {
267         rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, true);
268     } else {
269 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
270         rmt_ll_tx_reset_loop(rmt_contex.hal.regs, channel);
271         rmt_ll_tx_enable_loop_count(rmt_contex.hal.regs, channel, true);
272         rmt_ll_clear_tx_loop_interrupt(rmt_contex.hal.regs, channel);
273         rmt_ll_enable_tx_loop_interrupt(rmt_contex.hal.regs, channel, true);
274 #endif
275     }
276     rmt_ll_tx_start(rmt_contex.hal.regs, channel);
277     RMT_EXIT_CRITICAL();
278     return ESP_OK;
279 }
280 
rmt_tx_stop(rmt_channel_t channel)281 esp_err_t rmt_tx_stop(rmt_channel_t channel)
282 {
283     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
284     RMT_ENTER_CRITICAL();
285     rmt_ll_tx_stop(rmt_contex.hal.regs, channel);
286     rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
287     RMT_EXIT_CRITICAL();
288     return ESP_OK;
289 }
290 
rmt_rx_start(rmt_channel_t channel,bool rx_idx_rst)291 esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
292 {
293     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
294     RMT_ENTER_CRITICAL();
295     rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
296     if (rx_idx_rst) {
297         rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
298     }
299     rmt_ll_clear_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
300     rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
301 
302 #if SOC_RMT_SUPPORT_RX_PINGPONG
303     const uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
304     p_rmt_obj[channel]->rx_item_start_idx = 0;
305     p_rmt_obj[channel]->rx_item_len = 0;
306     rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2);
307 #endif
308 
309     rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
310     RMT_EXIT_CRITICAL();
311     return ESP_OK;
312 }
313 
rmt_rx_stop(rmt_channel_t channel)314 esp_err_t rmt_rx_stop(rmt_channel_t channel)
315 {
316     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
317     RMT_ENTER_CRITICAL();
318     rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
319     rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
320     rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
321 #if SOC_RMT_SUPPORT_RX_PINGPONG
322     rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
323 #endif
324     RMT_EXIT_CRITICAL();
325     return ESP_OK;
326 }
327 
rmt_tx_memory_reset(rmt_channel_t channel)328 esp_err_t rmt_tx_memory_reset(rmt_channel_t channel)
329 {
330     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
331     RMT_ENTER_CRITICAL();
332     rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
333     RMT_EXIT_CRITICAL();
334     return ESP_OK;
335 }
336 
rmt_rx_memory_reset(rmt_channel_t channel)337 esp_err_t rmt_rx_memory_reset(rmt_channel_t channel)
338 {
339     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
340     RMT_ENTER_CRITICAL();
341     rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
342     RMT_EXIT_CRITICAL();
343     return ESP_OK;
344 }
345 
rmt_set_memory_owner(rmt_channel_t channel,rmt_mem_owner_t owner)346 esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
347 {
348     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
349     RMT_CHECK(owner < RMT_MEM_OWNER_MAX, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
350     RMT_ENTER_CRITICAL();
351     rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), owner);
352     RMT_EXIT_CRITICAL();
353     return ESP_OK;
354 }
355 
rmt_get_memory_owner(rmt_channel_t channel,rmt_mem_owner_t * owner)356 esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner)
357 {
358     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
359     RMT_CHECK(owner != NULL, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
360     RMT_ENTER_CRITICAL();
361     *owner = (rmt_mem_owner_t)rmt_ll_rx_get_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
362     RMT_EXIT_CRITICAL();
363     return ESP_OK;
364 }
365 
rmt_set_tx_loop_mode(rmt_channel_t channel,bool loop_en)366 esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
367 {
368     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
369     RMT_ENTER_CRITICAL();
370     rmt_ll_tx_enable_loop(rmt_contex.hal.regs, channel, loop_en);
371     RMT_EXIT_CRITICAL();
372     return ESP_OK;
373 }
374 
rmt_get_tx_loop_mode(rmt_channel_t channel,bool * loop_en)375 esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en)
376 {
377     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
378     RMT_ENTER_CRITICAL();
379     *loop_en = rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel);
380     RMT_EXIT_CRITICAL();
381     return ESP_OK;
382 }
383 
rmt_set_rx_filter(rmt_channel_t channel,bool rx_filter_en,uint8_t thresh)384 esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
385 {
386     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
387     RMT_ENTER_CRITICAL();
388     rmt_ll_rx_enable_filter(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rx_filter_en);
389     rmt_ll_rx_set_filter_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
390     RMT_EXIT_CRITICAL();
391     return ESP_OK;
392 }
393 
rmt_set_source_clk(rmt_channel_t channel,rmt_source_clk_t base_clk)394 esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
395 {
396     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
397     RMT_CHECK(base_clk < RMT_BASECLK_MAX, RMT_BASECLK_ERROR_STR, ESP_ERR_INVALID_ARG);
398     RMT_ENTER_CRITICAL();
399     rmt_ll_set_counter_clock_src(rmt_contex.hal.regs, channel, base_clk, 0, 0, 0);
400     RMT_EXIT_CRITICAL();
401     return ESP_OK;
402 }
403 
rmt_get_source_clk(rmt_channel_t channel,rmt_source_clk_t * src_clk)404 esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
405 {
406     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
407     RMT_ENTER_CRITICAL();
408     *src_clk = (rmt_source_clk_t)rmt_ll_get_counter_clock_src(rmt_contex.hal.regs, channel);
409     RMT_EXIT_CRITICAL();
410     return ESP_OK;
411 }
412 
rmt_set_idle_level(rmt_channel_t channel,bool idle_out_en,rmt_idle_level_t level)413 esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level)
414 {
415     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
416     RMT_CHECK(level < RMT_IDLE_LEVEL_MAX, "RMT IDLE LEVEL ERR", ESP_ERR_INVALID_ARG);
417     RMT_ENTER_CRITICAL();
418     rmt_ll_tx_enable_idle(rmt_contex.hal.regs, channel, idle_out_en);
419     rmt_ll_tx_set_idle_level(rmt_contex.hal.regs, channel, level);
420     RMT_EXIT_CRITICAL();
421     return ESP_OK;
422 }
423 
rmt_get_idle_level(rmt_channel_t channel,bool * idle_out_en,rmt_idle_level_t * level)424 esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level)
425 {
426     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
427     RMT_ENTER_CRITICAL();
428     *idle_out_en = rmt_ll_is_tx_idle_enabled(rmt_contex.hal.regs, channel);
429     *level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel);
430     RMT_EXIT_CRITICAL();
431     return ESP_OK;
432 }
433 
rmt_get_status(rmt_channel_t channel,uint32_t * status)434 esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status)
435 {
436     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
437     RMT_ENTER_CRITICAL();
438     if (RMT_IS_RX_CHANNEL(channel)) {
439         *status = rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
440     } else {
441         *status = rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel);
442     }
443     RMT_EXIT_CRITICAL();
444     return ESP_OK;
445 }
446 
rmt_set_intr_enable_mask(uint32_t mask)447 void rmt_set_intr_enable_mask(uint32_t mask)
448 {
449     RMT_ENTER_CRITICAL();
450     rmt_ll_set_intr_enable_mask(mask);
451     RMT_EXIT_CRITICAL();
452 }
453 
rmt_clr_intr_enable_mask(uint32_t mask)454 void rmt_clr_intr_enable_mask(uint32_t mask)
455 {
456     RMT_ENTER_CRITICAL();
457     rmt_ll_clr_intr_enable_mask(mask);
458     RMT_EXIT_CRITICAL();
459 }
460 
rmt_set_rx_intr_en(rmt_channel_t channel,bool en)461 esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
462 {
463     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
464     RMT_ENTER_CRITICAL();
465     rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en);
466     RMT_EXIT_CRITICAL();
467     return ESP_OK;
468 }
469 
470 #if SOC_RMT_SUPPORT_RX_PINGPONG
rmt_set_rx_thr_intr_en(rmt_channel_t channel,bool en,uint16_t evt_thresh)471 esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
472 {
473     RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
474     if (en) {
475         uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
476         RMT_CHECK(evt_thresh <= item_block_len, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG);
477         RMT_ENTER_CRITICAL();
478         rmt_ll_rx_set_limit(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), evt_thresh);
479         rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
480         RMT_EXIT_CRITICAL();
481     } else {
482         RMT_ENTER_CRITICAL();
483         rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
484         RMT_EXIT_CRITICAL();
485     }
486     return ESP_OK;
487 }
488 #endif
489 
rmt_set_err_intr_en(rmt_channel_t channel,bool en)490 esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
491 {
492     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
493     RMT_ENTER_CRITICAL();
494     if (RMT_IS_RX_CHANNEL(channel)) {
495         rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en);
496     } else {
497         rmt_ll_enable_tx_err_interrupt(rmt_contex.hal.regs, channel, en);
498     }
499     RMT_EXIT_CRITICAL();
500     return ESP_OK;
501 }
502 
rmt_set_tx_intr_en(rmt_channel_t channel,bool en)503 esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
504 {
505     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
506     RMT_ENTER_CRITICAL();
507     rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, en);
508     RMT_EXIT_CRITICAL();
509     return ESP_OK;
510 }
511 
rmt_set_tx_thr_intr_en(rmt_channel_t channel,bool en,uint16_t evt_thresh)512 esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
513 {
514     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
515     if (en) {
516         uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
517         RMT_CHECK(evt_thresh <= item_block_len, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG);
518         RMT_ENTER_CRITICAL();
519         rmt_ll_tx_set_limit(rmt_contex.hal.regs, channel, evt_thresh);
520         rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, true);
521         RMT_EXIT_CRITICAL();
522     } else {
523         RMT_ENTER_CRITICAL();
524         rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, false);
525         RMT_EXIT_CRITICAL();
526     }
527     return ESP_OK;
528 }
529 
rmt_set_pin(rmt_channel_t channel,rmt_mode_t mode,gpio_num_t gpio_num)530 esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num)
531 {
532     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
533     RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG);
534     RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
535                (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))),
536               RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
537 
538     gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
539     if (mode == RMT_MODE_TX) {
540         RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
541         gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
542         esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.channels[channel].tx_sig, 0, 0);
543     } else {
544         RMT_CHECK(RMT_IS_RX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
545         gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
546         esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.channels[channel].rx_sig, 0);
547     }
548     return ESP_OK;
549 }
550 
rmt_is_channel_number_valid(rmt_channel_t channel,uint8_t mode)551 static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode)
552 {
553     // RX mode
554     if (mode == RMT_MODE_RX) {
555         return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX);
556     }
557     // TX mode
558     return (channel >= 0) && RMT_IS_TX_CHANNEL(channel);
559 }
560 
rmt_internal_config(rmt_dev_t * dev,const rmt_config_t * rmt_param)561 static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_param)
562 {
563     uint8_t mode = rmt_param->rmt_mode;
564     uint8_t channel = rmt_param->channel;
565     uint8_t gpio_num = rmt_param->gpio_num;
566     uint8_t mem_cnt = rmt_param->mem_block_num;
567     uint8_t clk_div = rmt_param->clk_div;
568     uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
569     bool carrier_en = rmt_param->tx_config.carrier_en;
570     uint32_t rmt_source_clk_hz;
571 
572     RMT_CHECK(rmt_is_channel_number_valid(channel, mode), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
573     RMT_CHECK((mem_cnt + channel <= 8 && mem_cnt > 0), RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
574     RMT_CHECK((clk_div > 0), RMT_CLK_DIV_ERROR_STR, ESP_ERR_INVALID_ARG);
575 
576     if (mode == RMT_MODE_TX) {
577         RMT_CHECK((!carrier_en || carrier_freq_hz > 0), "RMT carrier frequency can't be zero", ESP_ERR_INVALID_ARG);
578     }
579 
580     RMT_ENTER_CRITICAL();
581     rmt_ll_enable_mem_access(dev, true);
582 
583     if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
584 #if SOC_RMT_SUPPORT_XTAL
585         // clock src: XTAL_CLK
586         rmt_source_clk_hz = rtc_clk_xtal_freq_get() * 1000000;
587         rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_XTAL, 0, 0, 0);
588 #elif SOC_RMT_SUPPORT_REF_TICK
589         // clock src: REF_CLK
590         rmt_source_clk_hz = REF_CLK_FREQ;
591         rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_REF, 0, 0, 0);
592 #endif
593     } else {
594         // clock src: APB_CLK
595         rmt_source_clk_hz = APB_CLK_FREQ;
596         rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_APB, 0, 0, 0);
597     }
598     RMT_EXIT_CRITICAL();
599 
600 #if SOC_RMT_SOURCE_CLK_INDEPENDENT
601     s_rmt_source_clock_hz[channel] = rmt_source_clk_hz;
602 #else
603     if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) {
604         ESP_LOGW(RMT_TAG, "RMT clock source has been configured to %d by other channel, now reconfigure it to %d", s_rmt_source_clock_hz, rmt_source_clk_hz);
605     }
606     s_rmt_source_clock_hz = rmt_source_clk_hz;
607 #endif
608     ESP_LOGD(RMT_TAG, "rmt_source_clk_hz: %d\n", rmt_source_clk_hz);
609 
610     if (mode == RMT_MODE_TX) {
611         uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
612         uint8_t carrier_level = rmt_param->tx_config.carrier_level;
613         uint8_t idle_level = rmt_param->tx_config.idle_level;
614 
615         RMT_ENTER_CRITICAL();
616         rmt_ll_tx_set_counter_clock_div(dev, channel, clk_div);
617         rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt);
618         rmt_ll_tx_reset_pointer(dev, channel);
619         rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en);
620 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
621         if (rmt_param->tx_config.loop_en) {
622             rmt_ll_tx_set_loop_count(dev, channel, rmt_param->tx_config.loop_count);
623         }
624 #endif
625         /* always enable tx ping-pong */
626         rmt_ll_tx_enable_pingpong(dev, channel, true);
627         /*Set idle level */
628         rmt_ll_tx_enable_idle(dev, channel, rmt_param->tx_config.idle_output_en);
629         rmt_ll_tx_set_idle_level(dev, channel, idle_level);
630         /*Set carrier*/
631         rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en);
632         if (carrier_en) {
633             uint32_t duty_div, duty_h, duty_l;
634             duty_div = rmt_source_clk_hz / carrier_freq_hz;
635             duty_h = duty_div * carrier_duty_percent / 100;
636             duty_l = duty_div - duty_h;
637             rmt_ll_tx_set_carrier_level(dev, channel, carrier_level);
638             rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
639         } else {
640             rmt_ll_tx_set_carrier_level(dev, channel, 0);
641             rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, 0, 0);
642         }
643         RMT_EXIT_CRITICAL();
644 
645         ESP_LOGD(RMT_TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u",
646                  channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
647     } else if (RMT_MODE_RX == mode) {
648         uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
649         uint16_t threshold = rmt_param->rx_config.idle_threshold;
650 
651         RMT_ENTER_CRITICAL();
652         rmt_ll_rx_set_counter_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), clk_div);
653         rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt);
654         rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel));
655         rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), RMT_MEM_OWNER_HW);
656         /*Set idle threshold*/
657         rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), threshold);
658         /* Set RX filter */
659         rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), filter_cnt);
660         rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.filter_en);
661 
662 #if SOC_RMT_SUPPORT_RX_PINGPONG
663         /* always enable rx ping-pong */
664         rmt_ll_rx_enable_pingpong(dev, RMT_DECODE_RX_CHANNEL(channel), true);
665 #endif
666 
667 #if SOC_RMT_SUPPORT_RX_DEMODULATION
668         rmt_ll_rx_enable_carrier_demodulation(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.rm_carrier);
669         if (rmt_param->rx_config.rm_carrier) {
670             uint32_t duty_total = rmt_source_clk_hz / rmt_ll_rx_get_counter_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel)) / rmt_param->rx_config.carrier_freq_hz;
671             uint32_t duty_high = duty_total * rmt_param->rx_config.carrier_duty_percent / 100;
672             // there could be residual in timing the carrier pulse, so double enlarge the theoretical value
673             rmt_ll_rx_set_carrier_high_low_ticks(dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, (duty_total - duty_high) * 2);
674             rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.carrier_level);
675         }
676 #endif
677         RMT_EXIT_CRITICAL();
678 
679         ESP_LOGD(RMT_TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u",
680                  channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
681     }
682 
683     return ESP_OK;
684 }
685 
rmt_config(const rmt_config_t * rmt_param)686 esp_err_t rmt_config(const rmt_config_t *rmt_param)
687 {
688     rmt_module_enable();
689 
690     RMT_CHECK(rmt_set_pin(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num) == ESP_OK,
691               "set gpio for RMT driver failed", ESP_ERR_INVALID_ARG);
692 
693     RMT_CHECK(rmt_internal_config(&RMT, rmt_param) == ESP_OK,
694               "initialize RMT driver failed", ESP_ERR_INVALID_ARG);
695 
696     return ESP_OK;
697 }
698 
rmt_fill_memory(rmt_channel_t channel,const rmt_item32_t * item,uint16_t item_num,uint16_t mem_offset)699 static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
700                                       uint16_t item_num, uint16_t mem_offset)
701 {
702     RMT_ENTER_CRITICAL();
703     rmt_ll_write_memory(rmt_contex.hal.mem, channel, item, item_num, mem_offset);
704     RMT_EXIT_CRITICAL();
705 }
706 
rmt_fill_tx_items(rmt_channel_t channel,const rmt_item32_t * item,uint16_t item_num,uint16_t mem_offset)707 esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset)
708 {
709     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, (0));
710     RMT_CHECK((item != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
711     RMT_CHECK((item_num > 0), RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
712 
713     /*Each block has 64 x 32 bits of data*/
714     uint8_t mem_cnt = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
715     RMT_CHECK((mem_cnt * RMT_MEM_ITEM_NUM >= item_num), RMT_WR_MEM_OVF_ERROR_STR, ESP_ERR_INVALID_ARG);
716     rmt_fill_memory(channel, item, item_num, mem_offset);
717     return ESP_OK;
718 }
719 
rmt_isr_register(void (* fn)(void *),void * arg,int intr_alloc_flags,rmt_isr_handle_t * handle)720 esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, rmt_isr_handle_t *handle)
721 {
722     RMT_CHECK((fn != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
723     RMT_CHECK(rmt_contex.rmt_driver_channels == 0, "RMT driver installed, can not install generic ISR handler", ESP_FAIL);
724 
725     return esp_intr_alloc(rmt_periph_signals.irq, intr_alloc_flags, fn, arg, handle);
726 }
727 
rmt_isr_deregister(rmt_isr_handle_t handle)728 esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
729 {
730     return esp_intr_free(handle);
731 }
732 
rmt_rx_get_mem_len_in_isr(rmt_channel_t channel)733 static int IRAM_ATTR rmt_rx_get_mem_len_in_isr(rmt_channel_t channel)
734 {
735     int block_num = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel);
736     int item_block_len = block_num * RMT_MEM_ITEM_NUM;
737     volatile rmt_item32_t *data = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
738     int idx;
739     for (idx = 0; idx < item_block_len; idx++) {
740         if (data[idx].duration0 == 0) {
741             return idx;
742         } else if (data[idx].duration1 == 0) {
743             return idx + 1;
744         }
745     }
746     return idx;
747 }
748 
rmt_driver_isr_default(void * arg)749 static void IRAM_ATTR rmt_driver_isr_default(void *arg)
750 {
751     uint32_t status = 0;
752     rmt_item32_t volatile *addr = NULL;
753     uint8_t channel = 0;
754     rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
755     portBASE_TYPE HPTaskAwoken = pdFALSE;
756 
757     // Tx end interrupt
758     status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
759     while (status) {
760         channel = __builtin_ffs(status) - 1;
761         status &= ~(1 << channel);
762         rmt_obj_t *p_rmt = p_rmt_obj[channel];
763         if (p_rmt) {
764             xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
765             rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
766             p_rmt->tx_data = NULL;
767             p_rmt->tx_len_rem = 0;
768             p_rmt->tx_offset = 0;
769             p_rmt->tx_sub_len = 0;
770             p_rmt->sample_cur = NULL;
771             p_rmt->translator = false;
772             if (rmt_contex.rmt_tx_end_callback.function != NULL) {
773                 rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
774             }
775         }
776         rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
777     }
778 
779     // Tx thres interrupt
780     status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
781     while (status) {
782         channel = __builtin_ffs(status) - 1;
783         status &= ~(1 << channel);
784         rmt_obj_t *p_rmt = p_rmt_obj[channel];
785         if (p_rmt) {
786             if (p_rmt->translator) {
787                 if (p_rmt->sample_size_remain > 0) {
788                     size_t translated_size = 0;
789                     p_rmt->sample_to_rmt((void *)p_rmt->sample_cur,
790                                          p_rmt->tx_buf,
791                                          p_rmt->sample_size_remain,
792                                          p_rmt->tx_sub_len,
793                                          &translated_size,
794                                          &p_rmt->tx_len_rem);
795                     p_rmt->sample_size_remain -= translated_size;
796                     p_rmt->sample_cur += translated_size;
797                     p_rmt->tx_data = p_rmt->tx_buf;
798                 } else {
799                     p_rmt->sample_cur = NULL;
800                     p_rmt->translator = false;
801                 }
802             }
803             const rmt_item32_t *pdata = p_rmt->tx_data;
804             size_t len_rem = p_rmt->tx_len_rem;
805             if (len_rem >= p_rmt->tx_sub_len) {
806                 rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, p_rmt->tx_offset);
807                 p_rmt->tx_data += p_rmt->tx_sub_len;
808                 p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
809             } else if (len_rem == 0) {
810                 rmt_item32_t stop_data = {0};
811                 rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_offset);
812             } else {
813                 rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
814                 rmt_item32_t stop_data = {0};
815                 rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_offset + len_rem);
816                 p_rmt->tx_data += len_rem;
817                 p_rmt->tx_len_rem -= len_rem;
818             }
819             if (p_rmt->tx_offset == 0) {
820                 p_rmt->tx_offset = p_rmt->tx_sub_len;
821             } else {
822                 p_rmt->tx_offset = 0;
823             }
824         }
825         rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
826     }
827 
828     // Rx end interrupt
829     status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
830     while (status) {
831         channel = __builtin_ffs(status) - 1;
832         status &= ~(1 << channel);
833         rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
834         if (p_rmt) {
835             rmt_ll_rx_enable(rmt_contex.hal.regs, channel, false);
836             int item_len = rmt_rx_get_mem_len_in_isr(channel);
837             rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW);
838             if (p_rmt->rx_buf) {
839                 addr = RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
840 #if SOC_RMT_SUPPORT_RX_PINGPONG
841                 if (item_len > p_rmt->rx_item_start_idx) {
842                     item_len = item_len - p_rmt->rx_item_start_idx;
843                 }
844                 memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(addr + p_rmt->rx_item_start_idx), item_len * 4);
845                 p_rmt->rx_item_len += item_len;
846                 BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)(p_rmt->rx_item_buf), p_rmt->rx_item_len * 4, &HPTaskAwoken);
847 #else
848                 BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken);
849 #endif
850                 if (res == pdFALSE) {
851                     ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER FULL");
852                 }
853             } else {
854                 ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER ERROR");
855             }
856 
857 #if SOC_RMT_SUPPORT_RX_PINGPONG
858             p_rmt->rx_item_start_idx = 0;
859             p_rmt->rx_item_len = 0;
860             memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size);
861 #endif
862             rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
863             rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_HW);
864             rmt_ll_rx_enable(rmt_contex.hal.regs, channel, true);
865         }
866         rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
867     }
868 
869 #if SOC_RMT_SUPPORT_RX_PINGPONG
870     // Rx thres interrupt
871     status = rmt_ll_get_rx_thres_interrupt_status(hal->regs);
872     while (status) {
873         channel = __builtin_ffs(status) - 1;
874         status &= ~(1 << channel);
875         rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
876         int mem_item_size = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
877         int rx_thres_lim = rmt_ll_rx_get_limit(rmt_contex.hal.regs, channel);
878         int item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : (mem_item_size - rx_thres_lim);
879         if ((p_rmt->rx_item_len + item_len) < (p_rmt->rx_item_buf_size / 4)) {
880             rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW);
881             memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 + p_rmt->rx_item_start_idx), item_len * 4);
882             rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_HW);
883             p_rmt->rx_item_len += item_len;
884             p_rmt->rx_item_start_idx += item_len;
885             if (p_rmt->rx_item_start_idx >= mem_item_size) {
886                 p_rmt->rx_item_start_idx = 0;
887             }
888         } else {
889             ESP_EARLY_LOGE(RMT_TAG, "---RX buffer too small: %d", sizeof(p_rmt->rx_item_buf));
890         }
891         rmt_ll_clear_rx_thres_interrupt(hal->regs, channel);
892     }
893 #endif
894 
895 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
896     // loop count interrupt
897     status = rmt_ll_get_tx_loop_interrupt_status(hal->regs);
898     while (status) {
899         channel = __builtin_ffs(status) - 1;
900         status &= ~(1 << channel);
901         rmt_obj_t *p_rmt = p_rmt_obj[channel];
902         if (p_rmt) {
903             xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
904             if (rmt_contex.rmt_tx_end_callback.function != NULL) {
905                 rmt_contex.rmt_tx_end_callback.function(channel,  rmt_contex.rmt_tx_end_callback.arg);
906             }
907         }
908         rmt_ll_clear_tx_loop_interrupt(hal->regs, channel);
909     }
910 #endif
911 
912     // RX Err interrupt
913     status = rmt_ll_get_rx_err_interrupt_status(hal->regs);
914     while (status) {
915         channel = __builtin_ffs(status) - 1;
916         status &= ~(1 << channel);
917         rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
918         if (p_rmt) {
919             // Reset the receiver's write/read addresses to prevent endless err interrupts.
920             rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
921             ESP_EARLY_LOGD(RMT_TAG, "RMT RX channel %d error", channel);
922             ESP_EARLY_LOGD(RMT_TAG, "status: 0x%08x", rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, channel));
923         }
924         rmt_ll_clear_rx_err_interrupt(hal->regs, channel);
925     }
926 
927     // TX Err interrupt
928     status = rmt_ll_get_tx_err_interrupt_status(hal->regs);
929     while (status) {
930         channel = __builtin_ffs(status) - 1;
931         status &= ~(1 << channel);
932         rmt_obj_t *p_rmt = p_rmt_obj[channel];
933         if (p_rmt) {
934             // Reset the transmitter's write/read addresses to prevent endless err interrupts.
935             rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
936             ESP_EARLY_LOGD(RMT_TAG, "RMT TX channel %d error", channel);
937             ESP_EARLY_LOGD(RMT_TAG, "status: 0x%08x", rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel));
938         }
939         rmt_ll_clear_tx_err_interrupt(hal->regs, channel);
940     }
941 
942     if (HPTaskAwoken == pdTRUE) {
943         portYIELD_FROM_ISR();
944     }
945 }
946 
rmt_driver_uninstall(rmt_channel_t channel)947 esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
948 {
949     esp_err_t err = ESP_OK;
950     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
951     RMT_CHECK((rmt_contex.rmt_driver_channels & BIT(channel)) != 0, "No RMT driver for this channel", ESP_ERR_INVALID_STATE);
952     if (p_rmt_obj[channel] == NULL) {
953         return ESP_OK;
954     }
955     //Avoid blocking here(when the interrupt is disabled and do not wait tx done).
956     if (p_rmt_obj[channel]->wait_done) {
957         xSemaphoreTake(p_rmt_obj[channel]->tx_sem, portMAX_DELAY);
958     }
959 
960     RMT_ENTER_CRITICAL();
961     // check channel's working mode
962     if (p_rmt_obj[channel]->rx_buf) {
963         rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
964         rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
965 #if SOC_RMT_SUPPORT_RX_PINGPONG
966         rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
967 #endif
968     } else {
969         rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, 0);
970         rmt_ll_enable_tx_err_interrupt(rmt_contex.hal.regs, channel, 0);
971         rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, false);
972     }
973     RMT_EXIT_CRITICAL();
974 
975     _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
976     rmt_contex.rmt_driver_channels &= ~BIT(channel);
977     if (rmt_contex.rmt_driver_channels == 0) {
978         rmt_module_disable();
979         // all channels have driver disabled
980         err = rmt_isr_deregister(rmt_contex.rmt_driver_intr_handle);
981         rmt_contex.rmt_driver_intr_handle = NULL;
982     }
983     _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
984 
985     if (err != ESP_OK) {
986         return err;
987     }
988 
989     if (p_rmt_obj[channel]->tx_sem) {
990         vSemaphoreDelete(p_rmt_obj[channel]->tx_sem);
991         p_rmt_obj[channel]->tx_sem = NULL;
992     }
993     if (p_rmt_obj[channel]->rx_buf) {
994         vRingbufferDelete(p_rmt_obj[channel]->rx_buf);
995         p_rmt_obj[channel]->rx_buf = NULL;
996     }
997     if (p_rmt_obj[channel]->tx_buf) {
998         free(p_rmt_obj[channel]->tx_buf);
999         p_rmt_obj[channel]->tx_buf = NULL;
1000     }
1001     if (p_rmt_obj[channel]->sample_to_rmt) {
1002         p_rmt_obj[channel]->sample_to_rmt = NULL;
1003     }
1004 #if SOC_RMT_SUPPORT_RX_PINGPONG
1005     if (p_rmt_obj[channel]->rx_item_buf) {
1006         free(p_rmt_obj[channel]->rx_item_buf);
1007         p_rmt_obj[channel]->rx_item_buf = NULL;
1008         p_rmt_obj[channel]->rx_item_buf_size = 0;
1009     }
1010 #endif
1011 
1012     free(p_rmt_obj[channel]);
1013     p_rmt_obj[channel] = NULL;
1014     return ESP_OK;
1015 }
1016 
rmt_driver_install(rmt_channel_t channel,size_t rx_buf_size,int intr_alloc_flags)1017 esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
1018 {
1019     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1020     RMT_CHECK((rmt_contex.rmt_driver_channels & BIT(channel)) == 0,
1021               "RMT driver already installed for channel", ESP_ERR_INVALID_STATE);
1022 
1023     esp_err_t err = ESP_OK;
1024 
1025     if (p_rmt_obj[channel] != NULL) {
1026         ESP_LOGD(RMT_TAG, "RMT driver already installed");
1027         return ESP_ERR_INVALID_STATE;
1028     }
1029 
1030 #if !CONFIG_SPIRAM_USE_MALLOC
1031     p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
1032 #else
1033     if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
1034         p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
1035     } else {
1036         p_rmt_obj[channel] = heap_caps_calloc(1, sizeof(rmt_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
1037     }
1038 #endif
1039 
1040     if (p_rmt_obj[channel] == NULL) {
1041         ESP_LOGE(RMT_TAG, "RMT driver malloc error");
1042         return ESP_ERR_NO_MEM;
1043     }
1044 
1045     p_rmt_obj[channel]->tx_len_rem = 0;
1046     p_rmt_obj[channel]->tx_data = NULL;
1047     p_rmt_obj[channel]->channel = channel;
1048     p_rmt_obj[channel]->tx_offset = 0;
1049     p_rmt_obj[channel]->tx_sub_len = 0;
1050     p_rmt_obj[channel]->wait_done = false;
1051     p_rmt_obj[channel]->translator = false;
1052     p_rmt_obj[channel]->sample_to_rmt = NULL;
1053     if (p_rmt_obj[channel]->tx_sem == NULL) {
1054 #if !CONFIG_SPIRAM_USE_MALLOC
1055         p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
1056 #else
1057         p_rmt_obj[channel]->intr_alloc_flags = intr_alloc_flags;
1058         if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
1059             p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
1060         } else {
1061             p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinaryStatic(&p_rmt_obj[channel]->tx_sem_buffer);
1062         }
1063 #endif
1064         xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
1065     }
1066     if (p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
1067         p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
1068     }
1069 
1070 #if SOC_RMT_SUPPORT_RX_PINGPONG
1071     if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) {
1072 #if !CONFIG_SPIRAM_USE_MALLOC
1073         p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
1074 #else
1075         if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
1076             p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
1077         } else {
1078             p_rmt_obj[channel]->rx_item_buf = heap_caps_calloc(1, rx_buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
1079         }
1080 #endif
1081         if (p_rmt_obj[channel]->rx_item_buf == NULL) {
1082             ESP_LOGE(RMT_TAG, "RMT malloc fail");
1083             return ESP_FAIL;
1084         }
1085         p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size;
1086     }
1087 #endif
1088 
1089     _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
1090 
1091     if (rmt_contex.rmt_driver_channels == 0) {
1092         // first RMT channel using driver
1093         err = rmt_isr_register(rmt_driver_isr_default, &rmt_contex.hal, intr_alloc_flags, &(rmt_contex.rmt_driver_intr_handle));
1094     }
1095     if (err == ESP_OK) {
1096         rmt_contex.rmt_driver_channels |= BIT(channel);
1097     }
1098     _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
1099 
1100     rmt_module_enable();
1101 
1102     if (RMT_IS_RX_CHANNEL(channel)) {
1103         rmt_hal_rx_channel_reset(&rmt_contex.hal, RMT_DECODE_RX_CHANNEL(channel));
1104     } else {
1105         rmt_hal_tx_channel_reset(&rmt_contex.hal, channel);
1106     }
1107 
1108     return err;
1109 }
1110 
rmt_write_items(rmt_channel_t channel,const rmt_item32_t * rmt_item,int item_num,bool wait_tx_done)1111 esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, int item_num, bool wait_tx_done)
1112 {
1113     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1114     RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
1115     RMT_CHECK(rmt_item != NULL, RMT_ADDR_ERROR_STR, ESP_FAIL);
1116     RMT_CHECK(item_num > 0, RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
1117 #if CONFIG_SPIRAM_USE_MALLOC
1118     if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
1119         if (!esp_ptr_internal(rmt_item)) {
1120             ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR);
1121             return ESP_ERR_INVALID_ARG;
1122         }
1123     }
1124 #endif
1125     rmt_obj_t *p_rmt = p_rmt_obj[channel];
1126     int block_num = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
1127     int item_block_len = block_num * RMT_MEM_ITEM_NUM;
1128     int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
1129     int len_rem = item_num;
1130     xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1131     // fill the memory block first
1132     if (item_num >= item_block_len) {
1133         rmt_fill_memory(channel, rmt_item, item_block_len, 0);
1134         len_rem -= item_block_len;
1135         rmt_set_tx_loop_mode(channel, false);
1136         rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
1137         p_rmt->tx_data = rmt_item + item_block_len;
1138         p_rmt->tx_len_rem = len_rem;
1139         p_rmt->tx_offset = 0;
1140         p_rmt->tx_sub_len = item_sub_len;
1141     } else {
1142         rmt_fill_memory(channel, rmt_item, len_rem, 0);
1143         rmt_item32_t stop_data = {0};
1144         rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, len_rem);
1145         p_rmt->tx_len_rem = 0;
1146     }
1147     rmt_tx_start(channel, true);
1148     p_rmt->wait_done = wait_tx_done;
1149     if (wait_tx_done) {
1150         // wait loop done
1151         if (rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel)) {
1152 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
1153             xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1154             xSemaphoreGive(p_rmt->tx_sem);
1155 #endif
1156         } else {
1157             // wait tx end
1158             xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1159             xSemaphoreGive(p_rmt->tx_sem);
1160         }
1161     }
1162     return ESP_OK;
1163 }
1164 
rmt_wait_tx_done(rmt_channel_t channel,TickType_t wait_time)1165 esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
1166 {
1167     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1168     RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
1169     if (xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) {
1170         p_rmt_obj[channel]->wait_done = false;
1171         xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
1172         return ESP_OK;
1173     } else {
1174         if (wait_time != 0) {
1175             // Don't emit error message if just polling.
1176             ESP_LOGE(RMT_TAG, "Timeout on wait_tx_done");
1177         }
1178         return ESP_ERR_TIMEOUT;
1179     }
1180 }
1181 
rmt_get_ringbuf_handle(rmt_channel_t channel,RingbufHandle_t * buf_handle)1182 esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t *buf_handle)
1183 {
1184     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1185     RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
1186     RMT_CHECK(buf_handle != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
1187     *buf_handle = p_rmt_obj[channel]->rx_buf;
1188     return ESP_OK;
1189 }
1190 
rmt_register_tx_end_callback(rmt_tx_end_fn_t function,void * arg)1191 rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg)
1192 {
1193     rmt_tx_end_callback_t previous = rmt_contex.rmt_tx_end_callback;
1194     rmt_contex.rmt_tx_end_callback.function = function;
1195     rmt_contex.rmt_tx_end_callback.arg = arg;
1196     return previous;
1197 }
1198 
rmt_translator_init(rmt_channel_t channel,sample_to_rmt_t fn)1199 esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
1200 {
1201     RMT_CHECK(fn != NULL, RMT_TRANSLATOR_NULL_STR, ESP_ERR_INVALID_ARG);
1202     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1203     RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
1204     const uint32_t block_size = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) *
1205                                 RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
1206     if (p_rmt_obj[channel]->tx_buf == NULL) {
1207 #if !CONFIG_SPIRAM_USE_MALLOC
1208         p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
1209 #else
1210         if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
1211             p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
1212         } else {
1213             p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
1214         }
1215 #endif
1216         if (p_rmt_obj[channel]->tx_buf == NULL) {
1217             ESP_LOGE(RMT_TAG, "RMT translator buffer create fail");
1218             return ESP_FAIL;
1219         }
1220     }
1221     p_rmt_obj[channel]->sample_to_rmt = fn;
1222     p_rmt_obj[channel]->tx_context = NULL;
1223     p_rmt_obj[channel]->sample_size_remain = 0;
1224     p_rmt_obj[channel]->sample_cur = NULL;
1225     ESP_LOGD(RMT_TAG, "RMT translator init done");
1226     return ESP_OK;
1227 }
1228 
rmt_translator_set_context(rmt_channel_t channel,void * context)1229 esp_err_t rmt_translator_set_context(rmt_channel_t channel, void *context)
1230 {
1231     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1232     RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
1233 
1234     p_rmt_obj[channel]->tx_context = context;
1235     return ESP_OK;
1236 }
1237 
rmt_translator_get_context(const size_t * item_num,void ** context)1238 esp_err_t rmt_translator_get_context(const size_t *item_num, void **context)
1239 {
1240     RMT_CHECK(item_num && context, "invalid arguments", ESP_ERR_INVALID_ARG);
1241 
1242     // the address of tx_len_rem is directlly passed to the callback,
1243     // so it's possible to get the object address from that
1244     rmt_obj_t *obj = __containerof(item_num, rmt_obj_t, tx_len_rem);
1245     *context = obj->tx_context;
1246 
1247     return ESP_OK;
1248 }
1249 
rmt_write_sample(rmt_channel_t channel,const uint8_t * src,size_t src_size,bool wait_tx_done)1250 esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done)
1251 {
1252     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1253     RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
1254     RMT_CHECK(p_rmt_obj[channel]->sample_to_rmt != NULL, RMT_TRANSLATOR_UNINIT_STR, ESP_FAIL);
1255 #if CONFIG_SPIRAM_USE_MALLOC
1256     if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
1257         if (!esp_ptr_internal(src)) {
1258             ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR);
1259             return ESP_ERR_INVALID_ARG;
1260         }
1261     }
1262 #endif
1263     size_t translated_size = 0;
1264     rmt_obj_t *p_rmt = p_rmt_obj[channel];
1265     const uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
1266     const uint32_t item_sub_len = item_block_len / 2;
1267     xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1268     p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &p_rmt->tx_len_rem);
1269     p_rmt->sample_size_remain = src_size - translated_size;
1270     p_rmt->sample_cur = src + translated_size;
1271     rmt_fill_memory(channel, p_rmt->tx_buf, p_rmt->tx_len_rem, 0);
1272     if (p_rmt->tx_len_rem == item_block_len) {
1273         rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
1274         p_rmt->tx_data = p_rmt->tx_buf;
1275         p_rmt->tx_offset = 0;
1276         p_rmt->tx_sub_len = item_sub_len;
1277         p_rmt->translator = true;
1278     } else {
1279         rmt_item32_t stop_data = {0};
1280         rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_len_rem);
1281         p_rmt->tx_len_rem = 0;
1282         p_rmt->sample_cur = NULL;
1283         p_rmt->translator = false;
1284     }
1285     rmt_tx_start(channel, true);
1286     p_rmt->wait_done = wait_tx_done;
1287     if (wait_tx_done) {
1288         xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
1289         xSemaphoreGive(p_rmt->tx_sem);
1290     }
1291     return ESP_OK;
1292 }
1293 
rmt_get_channel_status(rmt_channel_status_result_t * channel_status)1294 esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
1295 {
1296     RMT_CHECK(channel_status != NULL, RMT_PARAM_ERR_STR, ESP_ERR_INVALID_ARG);
1297     for (int i = 0; i < RMT_CHANNEL_MAX; i++) {
1298         channel_status->status[i] = RMT_CHANNEL_UNINIT;
1299         if (p_rmt_obj[i] != NULL) {
1300             if (p_rmt_obj[i]->tx_sem != NULL) {
1301                 if (xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE) {
1302                     channel_status->status[i] = RMT_CHANNEL_IDLE;
1303                     xSemaphoreGive(p_rmt_obj[i]->tx_sem);
1304                 } else {
1305                     channel_status->status[i] = RMT_CHANNEL_BUSY;
1306                 }
1307             }
1308         }
1309     }
1310     return ESP_OK;
1311 }
1312 
rmt_get_counter_clock(rmt_channel_t channel,uint32_t * clock_hz)1313 esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
1314 {
1315     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1316     RMT_CHECK(clock_hz, "parameter clock_hz can't be null", ESP_ERR_INVALID_ARG);
1317     RMT_ENTER_CRITICAL();
1318     uint32_t rmt_source_clk_hz = 0;
1319 #if SOC_RMT_SOURCE_CLK_INDEPENDENT
1320     rmt_source_clk_hz = s_rmt_source_clock_hz[channel];
1321 #else
1322     rmt_source_clk_hz = s_rmt_source_clock_hz;
1323 #endif
1324     if (RMT_IS_RX_CHANNEL(channel)) {
1325         *clock_hz = rmt_source_clk_hz / rmt_ll_rx_get_counter_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
1326     } else {
1327         *clock_hz = rmt_source_clk_hz / rmt_ll_tx_get_counter_clock_div(rmt_contex.hal.regs, channel);
1328     }
1329     RMT_EXIT_CRITICAL();
1330     return ESP_OK;
1331 }
1332 
1333 #if SOC_RMT_SUPPORT_TX_GROUP
rmt_add_channel_to_group(rmt_channel_t channel)1334 esp_err_t rmt_add_channel_to_group(rmt_channel_t channel)
1335 {
1336     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1337     RMT_ENTER_CRITICAL();
1338     rmt_ll_tx_enable_sync(rmt_contex.hal.regs, true);
1339     rmt_ll_tx_add_channel_to_group(rmt_contex.hal.regs, channel);
1340     rmt_ll_tx_reset_counter_clock_div(rmt_contex.hal.regs, channel);
1341     RMT_EXIT_CRITICAL();
1342     return ESP_OK;
1343 }
1344 
rmt_remove_channel_from_group(rmt_channel_t channel)1345 esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel)
1346 {
1347     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1348     RMT_ENTER_CRITICAL();
1349     if (rmt_ll_tx_remove_channel_from_group(rmt_contex.hal.regs, channel) == 0) {
1350         rmt_ll_tx_enable_sync(rmt_contex.hal.regs, false);
1351     }
1352     RMT_EXIT_CRITICAL();
1353     return ESP_OK;
1354 }
1355 
rmt_memory_rw_rst(rmt_channel_t channel)1356 esp_err_t rmt_memory_rw_rst(rmt_channel_t channel)
1357 {
1358     RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1359     RMT_ENTER_CRITICAL();
1360     if (RMT_IS_RX_CHANNEL(channel)) {
1361         rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
1362     } else {
1363         rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
1364     }
1365     RMT_EXIT_CRITICAL();
1366     return ESP_OK;
1367 }
1368 #endif
1369 
1370 #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
rmt_set_tx_loop_count(rmt_channel_t channel,uint32_t count)1371 esp_err_t rmt_set_tx_loop_count(rmt_channel_t channel, uint32_t count)
1372 {
1373     RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
1374     RMT_ENTER_CRITICAL();
1375     rmt_ll_tx_set_loop_count(rmt_contex.hal.regs, channel, count);
1376     RMT_EXIT_CRITICAL();
1377     return ESP_OK;
1378 }
1379 #endif
1380