1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include "hal/rmt_hal.h"
15 #include "hal/rmt_ll.h"
16 #include "soc/soc_caps.h"
17
rmt_hal_init(rmt_hal_context_t * hal)18 void rmt_hal_init(rmt_hal_context_t *hal)
19 {
20 hal->regs = &RMT;
21 hal->mem = &RMTMEM;
22 }
23
rmt_hal_tx_channel_reset(rmt_hal_context_t * hal,uint32_t channel)24 void rmt_hal_tx_channel_reset(rmt_hal_context_t *hal, uint32_t channel)
25 {
26 rmt_ll_tx_reset_pointer(hal->regs, channel);
27 rmt_ll_tx_reset_loop(hal->regs, channel);
28 rmt_ll_enable_tx_err_interrupt(hal->regs, channel, false);
29 rmt_ll_enable_tx_end_interrupt(hal->regs, channel, false);
30 rmt_ll_enable_tx_thres_interrupt(hal->regs, channel, false);
31 rmt_ll_clear_tx_err_interrupt(hal->regs, channel);
32 rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
33 rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
34 }
35
rmt_hal_rx_channel_reset(rmt_hal_context_t * hal,uint32_t channel)36 void rmt_hal_rx_channel_reset(rmt_hal_context_t *hal, uint32_t channel)
37 {
38 rmt_ll_rx_reset_pointer(hal->regs, channel);
39 rmt_ll_enable_rx_err_interrupt(hal->regs, channel, false);
40 rmt_ll_enable_rx_end_interrupt(hal->regs, channel, false);
41 rmt_ll_clear_rx_err_interrupt(hal->regs, channel);
42 rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
43 }
44
rmt_hal_tx_set_channel_clock(rmt_hal_context_t * hal,uint32_t channel,uint32_t base_clk_hz,uint32_t counter_clk_hz)45 void rmt_hal_tx_set_channel_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz)
46 {
47 rmt_ll_tx_reset_channel_clock_div(hal->regs, channel);
48 uint32_t counter_div = (base_clk_hz + counter_clk_hz / 2) / counter_clk_hz;
49 rmt_ll_tx_set_channel_clock_div(hal->regs, channel, counter_div);
50 }
51
rmt_hal_set_carrier_clock(rmt_hal_context_t * hal,uint32_t channel,uint32_t base_clk_hz,uint32_t carrier_clk_hz,float carrier_clk_duty)52 void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty)
53 {
54 uint32_t carrier_div = (base_clk_hz + carrier_clk_hz / 2) / carrier_clk_hz;
55 uint32_t div_high = (uint32_t)(carrier_div * carrier_clk_duty);
56 uint32_t div_low = carrier_div - div_high;
57 rmt_ll_tx_set_carrier_high_low_ticks(hal->regs, channel, div_high, div_low);
58 }
59
rmt_hal_set_rx_filter_thres(rmt_hal_context_t * hal,uint32_t channel,uint32_t base_clk_hz,uint32_t thres_us)60 void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
61 {
62 uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
63 rmt_ll_rx_set_filter_thres(hal->regs, channel, thres);
64 }
65
rmt_hal_set_rx_idle_thres(rmt_hal_context_t * hal,uint32_t channel,uint32_t base_clk_hz,uint32_t thres_us)66 void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
67 {
68 uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
69 rmt_ll_rx_set_idle_thres(hal->regs, channel, thres);
70 }
71
rmt_hal_receive(rmt_hal_context_t * hal,uint32_t channel,rmt_item32_t * buf)72 uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf)
73 {
74 uint32_t len = 0;
75 rmt_ll_rx_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
76 for (len = 0; len < SOC_RMT_MEM_WORDS_PER_CHANNEL; len++) {
77 buf[len].val = hal->mem->chan[channel].data32[len].val;
78 if (!(buf[len].val & 0x7FFF)) {
79 break;
80 } else if (!(buf[len].val & 0x7FFF0000)) {
81 len++;
82 break;
83 }
84 }
85 rmt_ll_rx_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
86 rmt_ll_rx_reset_pointer(hal->regs, channel);
87 return len;
88 }
89
