1 /*
2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
3 * Contributors: 2018 Antmicro <www.antmicro.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT sifive_plic_1_0_0
9
10 /**
11 * @brief Platform Level Interrupt Controller (PLIC) driver
12 * for RISC-V processors
13 */
14
15 #include <zephyr/kernel.h>
16 #include <zephyr/arch/cpu.h>
17 #include <zephyr/device.h>
18 #include <soc.h>
19
20 #include <zephyr/sw_isr_table.h>
21 #include <zephyr/drivers/interrupt_controller/riscv_plic.h>
22 #include <zephyr/irq.h>
23
24 #define PLIC_BASE_ADDR(n) DT_INST_REG_ADDR(n)
25 /*
26 * These registers' offset are defined in the RISCV PLIC specs, see:
27 * https://github.com/riscv/riscv-plic-spec
28 */
29 #define PLIC_REG_PRIO_OFFSET 0x0
30 #define PLIC_REG_IRQ_EN_OFFSET 0x2000
31 #define PLIC_REG_REGS_OFFSET 0x200000
32 /*
33 * Trigger type is mentioned, but not defined in the RISCV PLIC specs.
34 * However, it is defined and supported by at least the Andes & Telink datasheet, and supported
35 * in Linux's SiFive PLIC driver
36 */
37 #define PLIC_REG_TRIG_TYPE_OFFSET 0x1080
38
39 #define PLIC_MAX_PRIO DT_INST_PROP(0, riscv_max_priority)
40 #define PLIC_PRIO (PLIC_BASE_ADDR(0) + PLIC_REG_PRIO_OFFSET)
41 #define PLIC_IRQ_EN (PLIC_BASE_ADDR(0) + PLIC_REG_IRQ_EN_OFFSET)
42 #define PLIC_REG (PLIC_BASE_ADDR(0) + PLIC_REG_REGS_OFFSET)
43
44 #define PLIC_IRQS (CONFIG_NUM_IRQS - CONFIG_2ND_LVL_ISR_TBL_OFFSET)
45 #define PLIC_EN_SIZE ((PLIC_IRQS >> 5) + 1)
46
47 #define PLIC_EDGE_TRIG_TYPE (PLIC_BASE_ADDR(0) + PLIC_REG_TRIG_TYPE_OFFSET)
48 #define PLIC_EDGE_TRIG_SHIFT 5
49
50 struct plic_regs_t {
51 uint32_t threshold_prio;
52 uint32_t claim_complete;
53 };
54
55 static int save_irq;
56
57 /**
58 * @brief return edge irq value or zero
59 *
60 * In the event edge irq is enable this will return the trigger
61 * value of the irq. In the event edge irq is not supported this
62 * routine will return 0
63 *
64 * @param irq IRQ number to add to the trigger
65 *
66 * @return irq value when enabled 0 otherwise
67 */
riscv_plic_is_edge_irq(uint32_t irq)68 static int riscv_plic_is_edge_irq(uint32_t irq)
69 {
70 volatile uint32_t *trig = (volatile uint32_t *)PLIC_EDGE_TRIG_TYPE;
71
72 trig += (irq >> PLIC_EDGE_TRIG_SHIFT);
73 return *trig & BIT(irq);
74 }
75
76 /**
77 * @brief Enable a riscv PLIC-specific interrupt line
78 *
79 * This routine enables a RISCV PLIC-specific interrupt line.
80 * riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGED
81 * arch_irq_enable function to enable external interrupts for
82 * IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
83 *
84 * @param irq IRQ number to enable
85 */
riscv_plic_irq_enable(uint32_t irq)86 void riscv_plic_irq_enable(uint32_t irq)
87 {
88 uint32_t key;
89 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
90
91 key = irq_lock();
92 en += (irq >> 5);
93 *en |= (1 << (irq & 31));
94 irq_unlock(key);
95 }
96
97 /**
98 * @brief Disable a riscv PLIC-specific interrupt line
99 *
100 * This routine disables a RISCV PLIC-specific interrupt line.
101 * riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGED
102 * arch_irq_disable function to disable external interrupts, for
103 * IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
104 *
105 * @param irq IRQ number to disable
106 */
riscv_plic_irq_disable(uint32_t irq)107 void riscv_plic_irq_disable(uint32_t irq)
108 {
109 uint32_t key;
110 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
111
112 key = irq_lock();
113 en += (irq >> 5);
114 *en &= ~(1 << (irq & 31));
115 irq_unlock(key);
116 }
117
118 /**
119 * @brief Check if a riscv PLIC-specific interrupt line is enabled
120 *
121 * This routine checks if a RISCV PLIC-specific interrupt line is enabled.
122 * @param irq IRQ number to check
123 *
124 * @return 1 or 0
125 */
riscv_plic_irq_is_enabled(uint32_t irq)126 int riscv_plic_irq_is_enabled(uint32_t irq)
127 {
128 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
129
130 en += (irq >> 5);
131 return !!(*en & (1 << (irq & 31)));
132 }
133
134 /**
135 * @brief Set priority of a riscv PLIC-specific interrupt line
136 *
137 * This routine set the priority of a RISCV PLIC-specific interrupt line.
138 * riscv_plic_irq_set_prio is called by riscv arch_irq_priority_set to set
139 * the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
140 *
141 * @param irq IRQ number for which to set priority
142 * @param priority Priority of IRQ to set to
143 */
riscv_plic_set_priority(uint32_t irq,uint32_t priority)144 void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
145 {
146 volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
147
148 if (priority > PLIC_MAX_PRIO)
149 priority = PLIC_MAX_PRIO;
150
151 prio += irq;
152 *prio = priority;
153 }
154
155 /**
156 * @brief Get riscv PLIC-specific interrupt line causing an interrupt
157 *
158 * This routine returns the RISCV PLIC-specific interrupt line causing an
159 * interrupt.
160 *
161 * @return PLIC-specific interrupt line causing an interrupt.
162 */
riscv_plic_get_irq(void)163 int riscv_plic_get_irq(void)
164 {
165 return save_irq;
166 }
167
plic_irq_handler(const void * arg)168 static void plic_irq_handler(const void *arg)
169 {
170 volatile struct plic_regs_t *regs =
171 (volatile struct plic_regs_t *) PLIC_REG;
172
173 uint32_t irq;
174 struct _isr_table_entry *ite;
175 int edge_irq;
176
177 /* Get the IRQ number generating the interrupt */
178 irq = regs->claim_complete;
179
180 /*
181 * Save IRQ in save_irq. To be used, if need be, by
182 * subsequent handlers registered in the _sw_isr_table table,
183 * as IRQ number held by the claim_complete register is
184 * cleared upon read.
185 */
186 save_irq = irq;
187
188 /*
189 * If the IRQ is out of range, call z_irq_spurious.
190 * A call to z_irq_spurious will not return.
191 */
192 if (irq == 0U || irq >= PLIC_IRQS)
193 z_irq_spurious(NULL);
194
195 edge_irq = riscv_plic_is_edge_irq(irq);
196
197 /*
198 * For edge triggered interrupts, write to the claim_complete register
199 * to indicate to the PLIC controller that the IRQ has been handled
200 * for edge triggered interrupts.
201 */
202 if (edge_irq)
203 regs->claim_complete = save_irq;
204
205 irq += CONFIG_2ND_LVL_ISR_TBL_OFFSET;
206
207 /* Call the corresponding IRQ handler in _sw_isr_table */
208 ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
209 ite->isr(ite->arg);
210
211 /*
212 * Write to claim_complete register to indicate to
213 * PLIC controller that the IRQ has been handled
214 * for level triggered interrupts.
215 */
216 if (!edge_irq)
217 regs->claim_complete = save_irq;
218 }
219
220 /**
221 * @brief Initialize the Platform Level Interrupt Controller
222 *
223 * @retval 0 on success.
224 */
plic_init(const struct device * dev)225 static int plic_init(const struct device *dev)
226 {
227
228 volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
229 volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
230 volatile struct plic_regs_t *regs =
231 (volatile struct plic_regs_t *)PLIC_REG;
232 int i;
233
234 /* Ensure that all interrupts are disabled initially */
235 for (i = 0; i < PLIC_EN_SIZE; i++) {
236 *en = 0U;
237 en++;
238 }
239
240 /* Set priority of each interrupt line to 0 initially */
241 for (i = 0; i < PLIC_IRQS; i++) {
242 *prio = 0U;
243 prio++;
244 }
245
246 /* Set threshold priority to 0 */
247 regs->threshold_prio = 0U;
248
249 /* Setup IRQ handler for PLIC driver */
250 IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
251 0,
252 plic_irq_handler,
253 NULL,
254 0);
255
256 /* Enable IRQ for PLIC driver */
257 irq_enable(RISCV_MACHINE_EXT_IRQ);
258
259 return 0;
260 }
261
262 DEVICE_DT_INST_DEFINE(0, plic_init, NULL, NULL, NULL,
263 PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
264
