1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_PWM_H__
35 #define NRF_PWM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_pwm_hal PWM HAL
45 * @{
46 * @ingroup nrf_pwm
47 * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
48 */
49
50 #if defined(PWM_DMA_SEQ_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether dedicated DMA register is present. */
52 #define NRF_PWM_HAS_DMA_REG 1
53 #else
54 #define NRF_PWM_HAS_DMA_REG 0
55 #endif
56
57 #if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || defined(__NRFX_DOXYGEN__)
58 /** @brief Symbol indicating whether shorting SEQSTART task with LOOPSDONE event is available. */
59 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 1
60 #else
61 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 0
62 #endif
63
64 #if (defined(PWM_TASKS_DMA_SEQ_START_START_Msk) && defined(PWM_EVENTS_DMA_SEQ_END_END_Msk)) || \
65 defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether PWM DMA tasks and events are present. */
67 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 1
68 #else
69 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 0
70 #endif
71
72 /**
73 * @brief Macro getting pointer to the structure of registers of the PWM peripheral.
74 *
75 * @param[in] idx PWM instance index.
76 *
77 * @return Pointer to the structure of registers of the PWM peripheral.
78 */
79 #define NRF_PWM_INST_GET(idx) NRFX_CONCAT_2(NRF_PWM, idx)
80
81 /**
82 * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
83 * function call to specify that a given output channel shall not be
84 * connected to a physical pin.
85 */
86 #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
87
88 /** @brief Number of channels in each PWM instance. */
89 #define NRF_PWM_CHANNEL_COUNT 4
90
91 /**
92 * @brief Helper macro for calculating the number of 16-bit values in the specified
93 * array of duty cycle values.
94 */
95 #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
96
97
98 /** @brief PWM tasks. */
99 typedef enum
100 {
101 NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
102 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
103 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[0].START), ///< Starts playback of sequence 0.
104 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[1].START), ///< Starts playback of sequence 1.
105 #else
106 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
107 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
108 #endif
109 NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
110 } nrf_pwm_task_t;
111
112 /** @brief PWM events. */
113 typedef enum
114 {
115 NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
116 NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
117 NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
118 NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
119 NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
120 NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
121 NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the specified number of times.
122 } nrf_pwm_event_t;
123
124 /** @brief PWM interrupts. */
125 typedef enum
126 {
127 NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
128 NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
129 NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
130 NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
131 NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
132 NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
133 NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
134 } nrf_pwm_int_mask_t;
135
136 /** @brief PWM shortcuts. */
137 typedef enum
138 {
139 NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
140 NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
141 #if NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART
142 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
143 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
144 #endif
145 NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
146 } nrf_pwm_short_mask_t;
147
148 /** @brief PWM modes of operation. */
149 typedef enum
150 {
151 NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
152 NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
153 } nrf_pwm_mode_t;
154
155 /** @brief PWM base clock frequencies. */
156 typedef enum
157 {
158 NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
159 NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
160 NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
161 NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
162 NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
163 NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
164 NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
165 NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
166 } nrf_pwm_clk_t;
167
168 /**
169 * @brief PWM decoder load modes.
170 *
171 * The selected mode determines how the sequence data is read from RAM and
172 * spread to the compare registers.
173 */
174 typedef enum
175 {
176 NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
177 NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
178 NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
179 NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
180 } nrf_pwm_dec_load_t;
181
182 /**
183 * @brief PWM decoder next step modes.
184 *
185 * The selected mode determines when the next value from the active sequence
186 * is loaded.
187 */
188 typedef enum
189 {
190 NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
191 NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
192 } nrf_pwm_dec_step_t;
193
194 /**
195 * @brief Type used for defining duty cycle values for a sequence
196 * loaded in @ref NRF_PWM_LOAD_COMMON mode.
197 */
198 typedef uint16_t nrf_pwm_values_common_t;
199
200 /**
201 * @brief Structure for defining duty cycle values for a sequence
202 * loaded in @ref NRF_PWM_LOAD_GROUPED mode.
203 */
204 typedef struct {
205 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
206 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
207 } nrf_pwm_values_grouped_t;
208
209 /**
210 * @brief Structure for defining duty cycle values for a sequence
211 * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
212 */
213 typedef struct
214 {
215 uint16_t channel_0; ///< Duty cycle value for channel 0.
216 uint16_t channel_1; ///< Duty cycle value for channel 1.
217 uint16_t channel_2; ///< Duty cycle value for channel 2.
218 uint16_t channel_3; ///< Duty cycle value for channel 3.
219 } nrf_pwm_values_individual_t;
220
221 /**
222 * @brief Structure for defining duty cycle values for a sequence
223 * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
224 */
225 typedef struct {
226 uint16_t channel_0; ///< Duty cycle value for channel 0.
227 uint16_t channel_1; ///< Duty cycle value for channel 1.
228 uint16_t channel_2; ///< Duty cycle value for channel 2.
229 uint16_t counter_top; ///< Top value for the pulse generator counter.
230 } nrf_pwm_values_wave_form_t;
231
232 /**
233 * @brief Union grouping pointers to arrays of duty cycle values applicable to
234 * various loading modes.
235 */
236 typedef union {
237 nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
238 nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
239 nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
240 nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
241 uint16_t const * p_raw; ///< Pointer providing raw access to the values.
242 } nrf_pwm_values_t;
243
244 /**
245 * @brief Structure for defining a sequence of PWM duty cycles.
246 *
247 * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
248 * provided duty cycle values are not copied. The @p values pointer is stored
249 * in the internal register of the peripheral, and the values are loaded from RAM
250 * during the sequence playback. Therefore, you must ensure that the values
251 * do not change before and during the sequence playback (for example,
252 * the values cannot be placed in a local variable that is allocated on stack).
253 * If the sequence is played in a loop and the values are to be updated
254 * before the next iteration, it is safe to modify them when the corresponding
255 * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
256 * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
257 *
258 * @note The @p repeats and @p end_delay values (which are written to the
259 * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
260 * respectively) are ignored at the end of a complex sequence
261 * playback, indicated by the LOOPSDONE event.
262 * See the Product Specification for more information.
263 */
264 typedef struct
265 {
266 nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
267 /**< This field is defined as an union of pointers
268 * to provide a convenient way to define duty
269 * cycle values in various loading modes
270 * (see @ref nrf_pwm_dec_load_t).
271 * In each value, the most significant bit (15)
272 * determines the polarity of the output and the
273 * others (14-0) compose the 15-bit value to be
274 * compared with the pulse generator counter. */
275 uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
276 uint32_t repeats; ///< Number of times that each duty cycle is to be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
277 uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
278 } nrf_pwm_sequence_t;
279
280
281 /**
282 * @brief Function for activating the specified PWM task.
283 *
284 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
285 * @param[in] task Task to be activated.
286 */
287 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
288 nrf_pwm_task_t task);
289
290 /**
291 * @brief Function for getting the address of the specified PWM task register.
292 *
293 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
294 * @param[in] task PWM task.
295 *
296 * @return Address of the specified task register.
297 */
298 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
299 nrf_pwm_task_t task);
300
301 /**
302 * @brief Function for clearing the specified PWM event.
303 *
304 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
305 * @param[in] event Event to clear.
306 */
307 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
308 nrf_pwm_event_t event);
309
310 /**
311 * @brief Function for retrieving the state of the PWM event.
312 *
313 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
314 * @param[in] event Event to be checked.
315 *
316 * @retval true The event has been generated.
317 * @retval false The event has not been generated.
318 */
319 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
320 nrf_pwm_event_t event);
321
322 /**
323 * @brief Function for getting the address of the specified PWM event register.
324 *
325 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
326 * @param[in] event PWM event.
327 *
328 * @return Address of the specified event register.
329 */
330 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
331 nrf_pwm_event_t event);
332
333 /**
334 * @brief Function for enabling the specified shortcuts.
335 *
336 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
337 * @param[in] mask Mask of shortcuts to be enabled.
338 */
339 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
340 uint32_t mask);
341
342 /**
343 * @brief Function for disabling the specified shortcuts.
344 *
345 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
346 * @param[in] mask Mask of shortcuts to be disabled.
347 */
348 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
349 uint32_t mask);
350
351 /**
352 * @brief Function for setting the configuration of PWM shortcuts.
353 *
354 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
355 * @param[in] mask Shortcuts configuration to be set.
356 */
357 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
358 uint32_t mask);
359
360 /**
361 * @brief Function for enabling specified interrupts.
362 *
363 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
364 * @param[in] mask Mask of interrupts to be enabled.
365 */
366 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
367 uint32_t mask);
368
369 /**
370 * @brief Function for disabling specified interrupts.
371 *
372 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
373 * @param[in] mask Mask of interrupts to be disabled.
374 */
375 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
376 uint32_t mask);
377
378 /**
379 * @brief Function for setting the configuration of PWM interrupts.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 * @param[in] mask Mask of interrupts to be set.
383 */
384 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
385 uint32_t mask);
386
387 /**
388 * @brief Function for checking if the specified interrupts are enabled.
389 *
390 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
391 * @param[in] mask Mask of interrupts to be checked.
392 *
393 * @return Mask of enabled interrupts.
394 */
395 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask);
396
397 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
398 /**
399 * @brief Function for setting the subscribe configuration for a given
400 * PWM task.
401 *
402 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
403 * @param[in] task Task for which to set the configuration.
404 * @param[in] channel Channel through which to subscribe events.
405 */
406 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
407 nrf_pwm_task_t task,
408 uint8_t channel);
409
410 /**
411 * @brief Function for clearing the subscribe configuration for a given
412 * PWM task.
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 * @param[in] task Task for which to clear the configuration.
416 */
417 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
418 nrf_pwm_task_t task);
419
420 /**
421 * @brief Function for setting the publish configuration for a given
422 * PWM event.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] event Event for which to set the configuration.
426 * @param[in] channel Channel through which to publish the event.
427 */
428 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
429 nrf_pwm_event_t event,
430 uint8_t channel);
431
432 /**
433 * @brief Function for clearing the publish configuration for a given
434 * PWM event.
435 *
436 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
437 * @param[in] event Event for which to clear the configuration.
438 */
439 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
440 nrf_pwm_event_t event);
441 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
442
443 /**
444 * @brief Function for enabling the PWM peripheral.
445 *
446 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
447 */
448 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
449
450 /**
451 * @brief Function for disabling the PWM peripheral.
452 *
453 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
454 */
455 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
456
457 /**
458 * @brief Function for assigning pins to PWM output channels.
459 *
460 * Usage of all PWM output channels is optional. If a given channel is not
461 * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
462 * number.
463 *
464 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
465 * @param[in] out_pins Array with pin numbers for individual PWM output channels.
466 */
467 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
468 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT]);
469
470 /**
471 * @brief Function for getting pin selection associated with specified PWM output channel.
472 *
473 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
474 * @param[in] channel PWM output channel.
475 *
476 * @return Pin selection associated with specified PWM output channel.
477 */
478 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
479
480 /**
481 * @brief Function for configuring the PWM peripheral.
482 *
483 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
484 * @param[in] base_clock Base clock frequency.
485 * @param[in] mode Operating mode of the pulse generator counter.
486 * @param[in] top_value Value up to which the pulse generator counter counts.
487 */
488 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
489 nrf_pwm_clk_t base_clock,
490 nrf_pwm_mode_t mode,
491 uint16_t top_value);
492
493 /**
494 * @brief Function for defining a sequence of PWM duty cycles.
495 *
496 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
497 * @param[in] seq_id Identifier of the sequence (0 or 1).
498 * @param[in] p_seq Pointer to the sequence definition.
499 */
500 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
501 uint8_t seq_id,
502 nrf_pwm_sequence_t const * p_seq);
503
504 /**
505 * @brief Function for modifying the pointer to the duty cycle values
506 * in the specified sequence.
507 *
508 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
509 * @param[in] seq_id Identifier of the sequence (0 or 1).
510 * @param[in] p_values Pointer to an array with duty cycle values.
511 */
512 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
513 uint8_t seq_id,
514 uint16_t const * p_values);
515
516 /**
517 * @brief Function for modifying the total number of duty cycle values
518 * in the specified sequence.
519 *
520 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
521 * @param[in] seq_id Identifier of the sequence (0 or 1).
522 * @param[in] length Number of duty cycle values.
523 */
524 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
525 uint8_t seq_id,
526 uint16_t length);
527
528 /**
529 * @brief Function for modifying the additional number of PWM periods spent
530 * on each duty cycle value in the specified sequence.
531 *
532 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
533 * @param[in] seq_id Identifier of the sequence (0 or 1).
534 * @param[in] refresh Number of additional PWM periods for each duty cycle value.
535 */
536 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
537 uint8_t seq_id,
538 uint32_t refresh);
539
540 /**
541 * @brief Function for modifying the additional time added after the sequence
542 * is played.
543 *
544 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
545 * @param[in] seq_id Identifier of the sequence (0 or 1).
546 * @param[in] end_delay Number of PWM periods added at the end of the sequence.
547 */
548 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
549 uint8_t seq_id,
550 uint32_t end_delay);
551
552 /**
553 * @brief Function for setting the mode of loading sequence data from RAM
554 * and advancing the sequence.
555 *
556 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
557 * @param[in] dec_load Mode of loading sequence data from RAM.
558 * @param[in] dec_step Mode of advancing the active sequence.
559 */
560 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
561 nrf_pwm_dec_load_t dec_load,
562 nrf_pwm_dec_step_t dec_step);
563
564 /**
565 * @brief Function for setting the number of times the sequence playback
566 * should be performed.
567 *
568 * This function applies to two-sequence playback (concatenated sequence 0 and 1).
569 * A single sequence can be played back only once.
570 *
571 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
572 * @param[in] loop_count Number of times to perform the sequence playback.
573 */
574 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, uint16_t loop_count);
575
576 /**
577 * @brief Function for getting the specified PWM SEQSTART task.
578 *
579 * @param[in] seq_id Sequence index.
580 *
581 * @return The specified PWM SEQSTART task.
582 */
583 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id);
584
585 /**
586 * @brief Function for getting the specified PWM SEQEND event.
587 *
588 * @param[in] seq_id Sequence index.
589 *
590 * @return The specified PWM SEQEND event.
591 */
592 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id);
593
594
595 #ifndef NRF_DECLARE_ONLY
596
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)597 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
598 nrf_pwm_task_t task)
599 {
600 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
601 }
602
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)603 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
604 nrf_pwm_task_t task)
605 {
606 return ((uint32_t)p_reg + (uint32_t)task);
607 }
608
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)609 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
610 nrf_pwm_event_t event)
611 {
612 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
613 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
614 }
615
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)616 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
617 nrf_pwm_event_t event)
618 {
619 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
620 }
621
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)622 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
623 nrf_pwm_event_t event)
624 {
625 return ((uint32_t)p_reg + (uint32_t)event);
626 }
627
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t mask)628 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, uint32_t mask)
629 {
630 p_reg->SHORTS |= mask;
631 }
632
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t mask)633 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, uint32_t mask)
634 {
635 p_reg->SHORTS &= ~(mask);
636 }
637
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t mask)638 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, uint32_t mask)
639 {
640 p_reg->SHORTS = mask;
641 }
642
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t mask)643 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, uint32_t mask)
644 {
645 p_reg->INTENSET = mask;
646 }
647
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t mask)648 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, uint32_t mask)
649 {
650 p_reg->INTENCLR = mask;
651 }
652
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t mask)653 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, uint32_t mask)
654 {
655 p_reg->INTEN = mask;
656 }
657
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,uint32_t mask)658 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask)
659 {
660 return p_reg->INTENSET & mask;
661 }
662
663 #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)664 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
665 nrf_pwm_task_t task,
666 uint8_t channel)
667 {
668 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
669 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
670 }
671
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)672 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
673 nrf_pwm_task_t task)
674 {
675 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
676 }
677
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)678 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
679 nrf_pwm_event_t event,
680 uint8_t channel)
681 {
682 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
683 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
684 }
685
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)686 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
687 nrf_pwm_event_t event)
688 {
689 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
690 }
691 #endif // defined(DPPI_PRESENT)
692
nrf_pwm_enable(NRF_PWM_Type * p_reg)693 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
694 {
695 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
696 }
697
nrf_pwm_disable(NRF_PWM_Type * p_reg)698 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
699 {
700 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
701 }
702
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])703 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
704 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])
705 {
706 uint8_t i;
707 for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
708 {
709 p_reg->PSEL.OUT[i] = out_pins[i];
710 }
711 }
712
nrf_pwm_pin_get(NRF_PWM_Type const * p_reg,uint8_t channel)713 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
714 {
715 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
716 return p_reg->PSEL.OUT[channel];
717 }
718
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)719 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
720 nrf_pwm_clk_t base_clock,
721 nrf_pwm_mode_t mode,
722 uint16_t top_value)
723 {
724 NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
725
726 p_reg->PRESCALER = base_clock;
727 p_reg->MODE = mode;
728 p_reg->COUNTERTOP = top_value;
729 }
730
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)731 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
732 uint8_t seq_id,
733 nrf_pwm_sequence_t const * p_seq)
734 {
735 NRFX_ASSERT(p_seq != NULL);
736
737 nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
738 nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
739 nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
740 nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
741 }
742
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)743 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
744 uint8_t seq_id,
745 uint16_t const * p_values)
746 {
747 NRFX_ASSERT(seq_id <= 1);
748 NRFX_ASSERT(p_values != NULL);
749 #if NRF_PWM_HAS_DMA_REG
750 p_reg->DMA.SEQ[seq_id].PTR = (uint32_t)p_values;
751 #else
752 p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
753 #endif
754 }
755
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)756 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
757 uint8_t seq_id,
758 uint16_t length)
759 {
760 NRFX_ASSERT(seq_id <= 1);
761 NRFX_ASSERT(length != 0);
762 NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
763 p_reg->SEQ[seq_id].CNT = length;
764 }
765
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)766 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
767 uint8_t seq_id,
768 uint32_t refresh)
769 {
770 NRFX_ASSERT(seq_id <= 1);
771 NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
772 p_reg->SEQ[seq_id].REFRESH = refresh;
773 }
774
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)775 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
776 uint8_t seq_id,
777 uint32_t end_delay)
778 {
779 NRFX_ASSERT(seq_id <= 1);
780 NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
781 p_reg->SEQ[seq_id].ENDDELAY = end_delay;
782 }
783
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)784 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
785 nrf_pwm_dec_load_t dec_load,
786 nrf_pwm_dec_step_t dec_step)
787 {
788 p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
789 ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
790 }
791
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)792 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
793 uint16_t loop_count)
794 {
795 p_reg->LOOP = loop_count;
796 }
797
nrf_pwm_seqstart_task_get(uint8_t seq_id)798 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id)
799 {
800 NRFX_ASSERT(seq_id <= 1);
801 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
802 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_DMA.SEQ[seq_id].START);
803 #else
804 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_SEQSTART[seq_id]);
805 #endif
806 }
807
nrf_pwm_seqend_event_get(uint8_t seq_id)808 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id)
809 {
810 NRFX_ASSERT(seq_id <= 1);
811 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
812 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_DMA.SEQ[seq_id].END);
813 #else
814 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_SEQEND[seq_id]);
815 #endif
816 }
817
818 #endif // NRF_DECLARE_ONLY
819
820 /** @} */
821
822 #ifdef __cplusplus
823 }
824 #endif
825
826 #endif // NRF_PWM_H__
827
828
