1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	timer_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef TIMER_REG_H
28 #define TIMER_REG_H
29 #include "../sys.h"
30 
31 /*******************************      timer registers: 0x140140     ******************************/
32 #define reg_tmr_ctrl0			REG_ADDR8(0x140140)
33 #define reg_tmr_ctrl16			REG_ADDR16(0x140140)
34 #define reg_tmr_ctrl32			REG_ADDR32(0x140140)
35 enum{
36 	FLD_TMR0_MODE =				BIT_RNG(0,1),
37 	FLD_TMR0_EN =				BIT(2),
38 	FLD_TMR0_NOWRAP = 			BIT(3),
39 	FLD_TMR1_MODE =				BIT_RNG(4,5),
40 	FLD_TMR1_EN =				BIT(6),
41 	FLD_TMR1_NOWRAP  = 			BIT(7),
42 };
43 
44 #define reg_tmr_ctrl2			REG_ADDR8(0x140142)
45 
46 enum{
47 	FLD_TMR_WD_EN =				BIT(7),
48 };
49 
50 #define reg_tmr_sta				REG_ADDR8(0x140143)
51 enum{
52 	FLD_TMR_STA_TMR0   =		BIT(0),
53 	FLD_TMR_STA_TMR1   =		BIT(1),
54 	FLD_TMR_STA_WD     =		BIT(2),
55 	FLD_TMR_WD_CNT_CLR =		BIT(3),
56 	FLD_TMR_SW_IRQ     =		BIT(7),
57 };
58 
59 #define  reg_tmr0_capt          REG_ADDR32(0x140144)
60 #define  reg_tmr1_capt          REG_ADDR32(0x140148)
61 #define  reg_tmr_capt(i)		REG_ADDR32(0x140144 + ((i) << 2))
62 
63 #define  reg_wt_target0         REG_ADDR8(0x14014c)// always is 0x00
64 #define  reg_wt_target1         REG_ADDR8(0x14014d)
65 #define  reg_wt_target2         REG_ADDR8(0x14014e)
66 #define  reg_wt_target3         REG_ADDR8(0x14014f)
67 #define  reg_wt_target          REG_ADDR32(0x14014c)
68 
69 
70 #define reg_tmr0_tick			REG_ADDR32(0X140150)
71 #define reg_tmr1_tick			REG_ADDR32(0X140154)
72 #define reg_tmr_tick(i)			REG_ADDR32(0X140150 + ((i) << 2))
73 
74 #endif
75