1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	swire_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef SWIRE_REG_H
28 #define SWIRE_REG_H
29 #include "../sys.h"
30 
31 
32 
33 
34 #define    SWIRE_BASE_ADDR			        0x100c00
35 
36 
37 #define   reg_swire_data      		    REG_ADDR8(SWIRE_BASE_ADDR)
38 
39 #define   reg_swire_ctl				    REG_ADDR8(SWIRE_BASE_ADDR+1)
40 enum{
41 	FLD_SWIRE_WR	        	= BIT(0),
42 	FLD_SWIRE_RD 	     	    = BIT(1),
43 	FLD_SWIRE_CMD 		        = BIT(2),
44 	FLD_SWIRE_ERR_FLAG			= BIT(3),
45 	// default :FLD_SWIRE_EOP = 1: 1byte format--- 1bit cmd + 8bit data +1 clock end(0)
46 	// FLD_SWIRE_EOP = 0: 1byte format--- 1bit cmd + 8bit data +1bit(1) + 1 clock end(0)
47 	FLD_SWIRE_EOP     			= BIT(4),
48 	FLD_SWIRE_USB_DET    	  	= BIT(6),
49 	FLD_SWIRE_USB_EN      		= BIT(7),
50 };
51 #define   reg_swire_ctl2				 REG_ADDR8(SWIRE_BASE_ADDR+2)
52 enum{
53 	FLD_SWIRE_CLK_DIV	        = BIT_RNG(0,6),
54 };
55 
56 #define   reg_swire_id				    REG_ADDR8(SWIRE_BASE_ADDR+3)
57 enum{
58 	FLD_SWIRE_ID_VALID	        = BIT_RNG(0,4),
59 	FLD_SWIRE_FIFO_MODE	        = BIT(7),
60 };
61 #endif
62