1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file pwm_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef PWM_REG_H 28 #define PWM_REG_H 29 30 #include "../sys.h" 31 32 33 34 /******************************* pwm registers: 0x140400 ******************************/ 35 #define reg_pwm_data_buf_adr 0x80140448 36 37 38 /** 39 * Represents the base address register of the PWM 40 */ 41 #define REG_PWM_BASE 0x140400 42 43 44 /** 45 * This register is used to enable PWM5 ~ PWM1 46 */ 47 #define reg_pwm_enable REG_ADDR8(REG_PWM_BASE) 48 enum{ 49 FLD_PWM1_EN = BIT(1), 50 FLD_PWM2_EN = BIT(2), 51 FLD_PWM3_EN = BIT(3), 52 FLD_PWM4_EN = BIT(4), 53 FLD_PWM5_EN = BIT(5), 54 }; 55 56 57 /** 58 * This register is used to enable PWM0. 59 */ 60 #define reg_pwm0_enable REG_ADDR8(REG_PWM_BASE+0x01) 61 enum{ 62 FLD_PWM0_EN = BIT(0), 63 }; 64 65 66 /** 67 * This register is used to set the division factor of the PWM clock. 68 */ 69 #define reg_pwm_clkdiv REG_ADDR8(REG_PWM_BASE+0x02) 70 71 72 /** 73 * BIT[3:0] of this register is used to set the working mode of PWM0.Only PWM0 supports 5 modes. 74 */ 75 #define reg_pwm0_mode REG_ADDR8(REG_PWM_BASE+0x03) 76 77 78 /** 79 * This register is used to set the inversion of the output state of PWM5 ~ PWM0. 80 * PWM and PWM_N can be inverted independently 81 */ 82 #define reg_pwm_invert REG_ADDR8(REG_PWM_BASE+0x04) 83 enum{ 84 FLD_PWM0_OUT_INVERT = BIT(0), 85 FLD_PWM1_OUT_INVERT = BIT(1), 86 FLD_PWM2_OUT_INVERT = BIT(2), 87 FLD_PWM3_OUT_INVERT = BIT(3), 88 FLD_PWM4_OUT_INVERT = BIT(4), 89 FLD_PWM5_OUT_INVERT = BIT(5), 90 }; 91 92 93 /** 94 * This register is used to set the inversion of the output state of PWM5_N ~ PWM0_N. 95 * PWM and PWM_N can be inverted independently 96 */ 97 #define reg_pwm_n_invert REG_ADDR8(REG_PWM_BASE+0x05) 98 enum{ 99 FLD_PWM0_INV_OUT_INVERT = BIT(0), 100 FLD_PWM1_INV_OUT_INVERT = BIT(1), 101 FLD_PWM2_INV_OUT_INVERT = BIT(2), 102 FLD_PWM3_INV_OUT_INVERT = BIT(3), 103 FLD_PWM4_INV_OUT_INVERT = BIT(4), 104 FLD_PWM5_INV_OUT_INVERT = BIT(5), 105 }; 106 107 108 /* 109 * This register represents Signal frame polarity of PWM5~PWM0.By default, PWM outputs high level under Count status and low level under Remaining status. 110 * If the corresponding bit is set to 1, the high and low levels in different states will be reversed. 111 * BIT(0):pwm0 out low level first. ~BIT(0):pwm0 out high level first. 112 * BIT(1):pwm1 out low level first. ~BIT(1):pwm1 out high level first. 113 * BIT(2):pwm2 out low level first. ~BIT(2):pwm2 out high level first. 114 * BIT(3):pwm3 out low level first. ~BIT(3):pwm3 out high level first. 115 * BIT(4):pwm4 out low level first. ~BIT(4):pwm4 out high level first. 116 * BIT(5):pwm5 out low level first. ~BIT(5):pwm5 out high level first. 117 */ 118 #define reg_pwm_pol REG_ADDR8(REG_PWM_BASE+0x06) 119 enum{ 120 FLD_PWM0_FIRST_OUT_LEVEL = BIT(0), 121 FLD_PWM1_FIRST_OUT_LEVEL = BIT(1), 122 FLD_PWM2_FIRST_OUT_LEVEL = BIT(2), 123 FLD_PWM3_FIRST_OUT_LEVEL = BIT(3), 124 FLD_PWM4_FIRST_OUT_LEVEL = BIT(4), 125 FLD_PWM5_FIRST_OUT_LEVEL = BIT(5), 126 }; 127 128 129 /* 130 * This register represents 32K clock source with PWM5 ~ PWM0 enabled 131 * If the system has a 32K clock source, whether it is 32K_RC or 32K_Crystal, as long as the corresponding 132 * BIT of 0x140407 is configured, the corresponding PWM Channel can get 32K clock source. 133 */ 134 #define reg_pwm_mode32k REG_ADDR8(REG_PWM_BASE+0x07) 135 enum{ 136 FLD_PWM0_32K_ENABLE = BIT(0), 137 FLD_PWM1_32K_ENABLE = BIT(1), 138 FLD_PWM2_32K_ENABLE = BIT(2), 139 FLD_PWM3_32K_ENABLE = BIT(3), 140 FLD_PWM4_32K_ENABLE = BIT(4), 141 FLD_PWM5_32K_ENABLE = BIT(5), 142 }; 143 144 145 /** 146 * This register configures the length of the capture segment of PWM5 ~ PWM0. 147 * This value has a total of 16 bits, divided into lower 8 bits and higher 8 bits. 148 */ 149 #define reg_pwm_cmp(i) REG_ADDR16(REG_PWM_BASE+0x14 +(i << 2)) 150 151 152 /** 153 * This register is used to configure the period of the PWM waveform. There are 32 bits in total. 154 * The lower 16 bits indicate the length of the CMP segment. The higher 16 bits indicate the length of the MAX segment. 155 */ 156 #define reg_pwm_cycle(i) REG_ADDR32(REG_PWM_BASE+0x14 + (i << 2)) 157 //enum{ 158 // FLD_PWM_CMP = BIT_RNG(0,15), 159 // FLD_PWM_MAX = BIT_RNG(16,31), 160 //}; 161 // in C99 FLD_PWM_MAX = BIT_RNG(16,31) is error 162 #define FLD_PWM_CMP = BIT_RNG(0,15), 163 #define FLD_PWM_MAX = BIT_RNG(16,31), 164 /** 165 * This register configures the length of the max segment of PWM5 ~ PWM0. 166 * This value has a total of 16 bits, divided into lower 8 bits and higher 8 bits. 167 */ 168 #define reg_pwm_max(i) REG_ADDR16(REG_PWM_BASE+0x16 + (i << 2)) 169 170 /* 171 * when update the duty cycle in 32K, this register bit(0) set 1. 172 */ 173 #define reg_pwm_cnt5_l REG_ADDR8(REG_PWM_BASE+0x3e) 174 175 enum{ 176 FLD_PWM_32K_DUTY_CYCLE_UPDATE = BIT(0), 177 }; 178 179 /** 180 * When PWM0 is in count mode or ir mode, the total number of pulse_number is set by the following two registers. 181 */ 182 #define reg_pwm0_pulse_num0 REG_ADDR8(REG_PWM_BASE+0x2c)//0x2c[7:0] 183 #define reg_pwm0_pulse_num1 REG_ADDR8(REG_PWM_BASE+0x2d)//0x2d[5:0] 184 185 186 /** 187 * PWM interrupt mask or interrupt status 188 */ 189 190 typedef enum{ 191 FLD_PWM0_PNUM_IRQ = BIT(0), 192 FLD_PWM0_IR_DMA_FIFO_IRQ = BIT(1), 193 FLD_PWM0_FRAME_DONE_IRQ = BIT(2), 194 FLD_PWM1_FRAME_DONE_IRQ = BIT(3), 195 FLD_PWM2_FRAME_DONE_IRQ = BIT(4), 196 FLD_PWM3_FRAME_DONE_IRQ = BIT(5), 197 FLD_PWM4_FRAME_DONE_IRQ = BIT(6), 198 FLD_PWM5_FRAME_DONE_IRQ = BIT(7), 199 200 FLD_PWM0_IR_FIFO_IRQ = BIT(16), 201 202 }pwm_irq_e; 203 204 /** 205 * This register is used to configure the PWM interrupt function. 206 * BIT[0]:If this bit is set, an interrupt will be generated after a set of pulses has been sent. When this interrupt is enabled, you can capture an interrupt after a pulse is sent by detecting whether bit[0] of 0x140431 is set. 207 * BIT[1]:Enable ir dma fifo mode interrupt.This bit is usually used with 0x140431BIT[1]. 208 * BIT[2]:Enable pwm0 frame interrupt. 209 * BIT[3]:Enable pwm1 frame interrupt. 210 * BIT[4]:Enable pwm2 frame interrupt. 211 * BIT[5]:Enable pwm3 frame interrupt. 212 * BIT[6]:Enable pwm4 frame interrupt. 213 * BIT[7]:Enable pwm5 frame interrupt. 214 * BIT[16]:The Bit is to enable the mask_lvl(This level specifically indicates the number of bytes in the FIFO that can trigger an interrupt) interrupt. 215 */ 216 #define reg_pwm_irq_mask(i) REG_ADDR8(REG_PWM_BASE+0x30+i*2) 217 218 219 /** 220 * The bits in this register are used to indicate the various interrupt states of the PWM. 221 * BIT[0]:This bit is usually used with BIT[0] of 0x140430. If this bit is set to 1, it means that a pulse group of PWM has been sent.An interrupt was also generated. You can manually write 1 to clear the interrupt flag. 222 * BIT[1]:In ir dma fifo mode. If this is set 1 Indicates that a set of pulse of group has been sent. You can manually write 1 to clear the interrupt flag. 223 * BIT[2]:If this is set 1 Indicates that a signal frame interrupt has been generated. You can manually write 1 to clear the interrupt flag. 224 * BIT[3]:If this is set 1 Indicates that a signal frame interrupt has been generated. You can manually write 1 to clear the interrupt flag. 225 * BIT[4]:If this is set 1 Indicates that a signal frame interrupt has been generated. You can manually write 1 to clear the interrupt flag. 226 * BIT[5]:If this is set 1 Indicates that a signal frame interrupt has been generated. You can manually write 1 to clear the interrupt flag. 227 * BIT[6]:If this is set 1 Indicates that a signal frame interrupt has been generated. You can manually write 1 to clear the interrupt flag. 228 * BIT[7]:If this is set 1 Indicates that a signal frame interrupt has been generated. You can manually write 1 to clear the interrupt flag. 229 * BIT[16]:When the FIFO value is less than the set value, an interrupt is generated(The premise is that this interrupt has been enabled by register 0x140432 previous). 230 * The user can know whether this interrupt is generated by reading the status of this register.If BIT(16):1 Indicates that this interrupt has been generated. 231 */ 232 #define reg_pwm_irq_sta(i) REG_ADDR8(REG_PWM_BASE+0x31+i*2) 233 234 235 /** 236 * This register is used to count the number of PWM5~PWM0 pulses.The number of pulses of each PWM consists of 16 bits 237 */ 238 #define reg_pwm_cnt(i) REG_ADDR16(REG_PWM_BASE+0x34 +(i << 1)) 239 240 241 /** 242 * PWM0 pulse_cnt value BIT[7:0]. 243 */ 244 #define reg_pwm_ncnt_l REG_ADDR8(REG_PWM_BASE+0x40) 245 246 247 /** 248 * PWM0 pulse_cnt value BIT[15:8]. 249 */ 250 #define reg_pwm_ncnt_h REG_ADDR8(REG_PWM_BASE+0x41) 251 252 253 /** 254 * [7:0] bits 7-0 of PWM0's high time or low time(if pola[0]=1),if shadow bit(fifo data[14]) is 1 in ir fifo mode or dma fifo mode. 255 */ 256 #define reg_pwm_tcmp0_shadow REG_ADDR16(REG_PWM_BASE+0x44) 257 258 259 /** 260 * [15:8] bits 15-8 of PWM0's high time or low time(if pola[0]=1),if shadow bit(fifo data[14]) is 1 in ir fifo mode or dma fifo mode. 261 */ 262 #define reg_pwm_tmax0_shadow REG_ADDR16(REG_PWM_BASE+0x46) 263 264 265 /** 266 * PWM data fifo.0x140448~0x14044b. 267 */ 268 #define reg_pwm_ir_fifo_dat(i) REG_ADDR16(REG_PWM_BASE+0x48+i*2) 269 270 271 /** 272 * This register BIT[3:0] indicates the interrupt trigger level in ir_fifo mode. 273 * When fifo numbers is less than this value.It's will take effect. 274 */ 275 #define reg_pwm_ir_fifo_irq_trig_level REG_ADDR8(REG_PWM_BASE+0x4c) 276 enum{ 277 FLD_PWM0_FIFO_NUM_OF_TRIGGLE_LEVEL = BIT_RNG(0,3), 278 }; 279 280 281 /** 282 * This register indicates the fifo data status in. 283 * BIT[3:0]:Indicates the amount of data in the FIFO. 284 * BIT[4]:if BIT[4]=1,Indicates the data fifo is empty. 285 * BIT[5]:if BIT[5]=1,Indicates the data fifo is full. 286 */ 287 #define reg_pwm_ir_fifo_data_status REG_ADDR8(0x14044d) 288 enum{ 289 FLD_PWM0_IR_FIFO_DATA_NUM = BIT_RNG(0,3), 290 FLD_PWM0_IR_FIFO_EMPTY = BIT(4), 291 FLD_PWM0_IR_FIFO_FULL = BIT(5), 292 }; 293 294 295 /** 296 * This register can be configured to clear the data FIFO. 297 * BIT[0]:if BIT[0]=1,Indicates the data FIFO is clear. 298 */ 299 #define reg_pwm_ir_clr_fifo_data REG_ADDR8(0x14044e) 300 enum{ 301 FLD_PWM0_IR_FIFO_CLR_DATA = BIT(0), 302 303 }; 304 305 306 307 308 309 #endif 310 311 312 313 314 315 316 317 318 319
