1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file i2c_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef I2C_REG_H_ 28 #define I2C_REG_H_ 29 #include "../sys.h" 30 /******************************* i2c registers: 0x140280 ******************************/ 31 32 33 #define REG_I2C_BASE 0x140280 34 35 36 #define reg_i2c_data_buf0_addr 0x80140288 37 38 39 /** 40 * this register to configure I2C master clock speed,eagle i2c has default clock speed. 41 * for eagle i2c,its default clock resource is 24M, its default speed is 200K. 42 * user can configure this register to get other speed: i2c clock = i2c_system_clock/(4*DivClock) 43 * DivClock=0x80140280[7:0].max_value=0xff. 44 */ 45 #define reg_i2c_sp REG_ADDR8(REG_I2C_BASE) 46 47 48 /** 49 * this register to configure I2C ID. 50 * BIT[0] to set write or read bit:0=0 for write, bit:0=1 for read. 51 * BIT[7:1] for ID. 52 */ 53 #define reg_i2c_id REG_ADDR8(REG_I2C_BASE+0x01) 54 enum{ 55 FLD_I2C_WRITE_READ_BIT = BIT(0), 56 FLD_I2C_ID = BIT_RNG(1,7), 57 }; 58 59 60 /** 61 * this register is to configure i2c master 62 * BIT[0] means i2c bus whether busy. 63 * BIT[1] means that a start signal is coming, it is 1, and an end signal is coming it will be 0. 64 * BIT[2] Indicates the status of master send and receive,bit[2]=1,means have not ability to send or receivebit[2]=0,means have ability to send or receive. 65 * BIT_RNG[3:5] Indicate what state the i2c is in when it acts as master, BIT_RNG[3:5] defaule value is 0x06 it means master's state is IDLE. 66 * BIT_RNG[6:7] Indicate what state the i2c is in when it acts as slave. 67 */ 68 #define reg_i2c_mst REG_ADDR8(REG_I2C_BASE+0x02) 69 enum{ 70 FLD_I2C_MST_BUSY = BIT(0), 71 FLD_I2C_SCS_N = BIT(1), 72 FLD_I2C_ACK_IN = BIT(2), 73 FLD_I2C_MST_P = BIT_RNG(3,5), 74 FLD_I2C_SS = BIT_RNG(6,7), 75 }; 76 77 78 /** 79 * This shows the status control register of i2c 80 * BIT[0] i2c master enable. 81 * BIT[1] clk stretch enable: suspend transimission by pulling SCL down to low level,and continue transmission after SCL is pelesed to hign level. 82 * BIT[2] rx interrupt enable.RX is related to rx_irq_trig_lev function (this function is always present and does not need any setting to enable). 83 * fifo_data_cnt> = rx_irq_trig_lev generates an interrupt. 84 * BIT[3] tx interrupt enable.Related to tx_irq_trig_lev function,(This function is always present and does not require any setting to enable). 85 * fifo_data_cnt <= tx_irq_trig_lev, generate interrupt. 86 * BIT[4] tx_done.An interrupt is generated when one frame of data is sent. 87 * BIT[5] rx_done.An interrupt is generated when one frame of data is received. 88 * BIT[6] If the bit is set to 1, when the master reads, the hardware will automatically return ack / nak, no software processing is required. 89 * It is a new feature of eagle.Previously, software processed it through FLD_I2C_LS_ACK. Setting this bit to 0 will ack, and setting it to 1 will NAK. 90 * BIT[7] means,before master ack, delay sda data bus. 91 */ 92 #define reg_i2c_sct0 REG_ADDR8(REG_I2C_BASE+0x03) 93 typedef enum{ 94 FLD_I2C_MASTER = BIT(0), 95 FLD_I2C_R_CLK_STRETCH_EN = BIT(1), 96 FLD_I2C_RX_BUF_MASK = BIT(2), 97 FLD_I2C_TX_BUF_MASK = BIT(3), 98 FLD_I2C_TX_DONE_MASK = BIT(4), 99 FLD_I2C_RX_DONE_MASK = BIT(5), 100 FLD_I2C_RNCK_EN = BIT(6), 101 FLD_I2C_MANUAL_SDA_DELAY = BIT(7), 102 }i2c_mask_irq_type_e; 103 104 105 106 /** 107 * This shows the status control register of i2c 108 * BIT[0] launch i2c ID cycle. 109 * BIT[1] launch i2c address cycle. 110 * BIT[2] launch data write cycle. 111 * BIT[3] launch data read cycle. 112 * BIT[4] launch start cycle. 113 * BIT[5] launch stop cycle. 114 * BIT[6] enable if BIT[6]=1,Its role is to convert the SDA from output to input, so that the master can accept the data sent by the slave when it reads. 115 * BIT[7] enable ACK in read command.When the master is reading, it needs to return to ack or nak. 116 * If it is in manual mode,when the master is reading, you need to configure this bit to determine whether it will ack. 117 * BIT[7] = 0,return ack. BIT[7] = 1,return nak. 118 */ 119 #define reg_i2c_sct1 REG_ADDR8(REG_I2C_BASE+0x04) 120 enum{ 121 FLD_I2C_LS_ID = BIT(0), 122 FLD_I2C_LS_ADDR = BIT(1), 123 FLD_I2C_LS_DATAW = BIT(2), 124 FLD_I2C_LS_DATAR = BIT(3), 125 FLD_I2C_LS_START = BIT(4), 126 FLD_I2C_LS_STOP = BIT(5), 127 FLD_I2C_LS_ID_R = BIT(6), 128 FLD_I2C_LS_ACK = BIT(7), 129 }; 130 131 132 /** 133 * This is the register that configures the i2c trigger interrupt 134 * BIT_RNG[0,3] to configure the interrupt trigger level of rx_status, for example BIT_RNG[0:3]=0x04,when rx 4bytes,will trigger interrupt. 135 * BIT_RNG[4,7] to configure the interrupt trigger level of tx_status, for example BIT_RNG[0:3]=0x04,when tx 4bytes,will trigger interrupt. 136 */ 137 #define reg_i2c_trig REG_ADDR8(REG_I2C_BASE+0x05) 138 enum{ 139 FLD_I2C_RX_IRQ_TRIG_LEV = BIT_RNG(0,3), 140 FLD_I2C_TX_IRQ_TRIG_LEV = BIT_RNG(4,7), 141 }; 142 143 144 //As a master, you need to configure this length for both sending and receiving, and the hardware needs to know what the length is. 145 #define reg_i2c_len REG_ADDR8(REG_I2C_BASE+0x06) 146 147 148 /** 149 * This register is to configure the slave stretch function. 150 * BIT[0] slave auto stretch clk eanble,open this function, use slave to receive data,when data buffer is full, scl bus will be low to stop receive data. 151 * BIT[1] slave manul stretch clk enable,open this function, use slave to receive data,when data buffer is full, scl bus will be low to stop receive data. 152 * BIT[2] clear slave stretch. 153 * BIT[6] in high speed mode,when open slave auto stretch clk function,Suddenly data came over, to meet the requirements of time setting. 154 * BIT[7] in fast speed mode,when open slave auto stretch clk function,Suddenly data came over, to meet the requirements of time setting. 155 */ 156 #define reg_i2c_slave_strech_en REG_ADDR8(REG_I2C_BASE+0x07) 157 enum{ 158 FLD_I2C_R_CLK_STRETCH_SEN = BIT(0), 159 FLD_I2C_R_MANUAL_STRETCH = BIT(1), 160 FLD_I2C_MANUAL_STRETCH_CLR = BIT(2), 161 FLD_I2C_R_HS_MODE = BIT(6), 162 FLD_I2C_R_FAST_MODE = BIT(7), 163 }; 164 165 #define reg_i2c_data_buf(i) REG_ADDR8(( REG_I2C_BASE+0x08 +(i) )) 166 /** 167 * This register represents the data buffer of i2c. 168 * BIT_RNG[0,7] Buffer that stores one byte of data 169 */ 170 #define reg_i2c_data_buf0 REG_ADDR8(REG_I2C_BASE+0x08) 171 enum{ 172 FLD_I2C_BUF0 = BIT_RNG(0,7), 173 }; 174 175 176 /** 177 * This register represents the data buffer of i2c. 178 * BIT_RNG[0,7] Buffer that stores one byte of data 179 */ 180 #define reg_i2c_data_buf1 REG_ADDR8(REG_I2C_BASE+0x09) 181 enum{ 182 FLD_I2C_BUF1 = BIT_RNG(0,7), 183 }; 184 185 186 /** 187 * This register represents the data buffer of i2c. 188 * BIT_RNG[0,7] Buffer that stores one byte of data 189 */ 190 #define reg_i2c_data_buf2 REG_ADDR8(REG_I2C_BASE+0x0a) 191 enum{ 192 FLD_I2C_BUF2 = BIT_RNG(0,7), 193 }; 194 195 196 /** 197 * This register represents the data buffer of i2c. 198 * BIT_RNG[0,7] Buffer that stores one byte of data 199 */ 200 #define reg_i2c_data_buf3 REG_ADDR8(REG_I2C_BASE+0x0b) 201 enum{ 202 FLD_I2C_BUF3 = BIT_RNG(0,7), 203 }; 204 205 206 /** 207 * This register is used to configure the number of bytes in the i2c buffer 208 * BIT_RNG[0,3] rx_bufcnt is equivalent to a pointer to fifo, one in data plus one, one out data minus one. 209 * BIT_RNG[4,7] tx_bufcnt is equivalent to a pointer to fifo, one in data plus one, one out data minus one. 210 */ 211 #define reg_i2c_buf_cnt REG_ADDR8(REG_I2C_BASE+0x0c) 212 enum{ 213 FLD_I2C_RX_BUFCNT = BIT_RNG(0,3), 214 FLD_I2C_TX_BUFCNT = BIT_RNG(4,7), 215 }; 216 217 218 /** 219 * This register used to configure the status of i2c. 220 * BIT_RNG[0,2] rbcnt is the accumulation of this action read, fifo clear will clear. 221 * BIT[3] Indicates whether i2c is in an interrupted state. 222 * BIT_RNG[4,6] if configure BIT[6]=1,will manual clean rx_fifo. BIT[5,4] Indicates the number of bytes of tx_buffer. 223 * BIT[7] if configure BIT[7]=1,will manual clean tx_fifo. 224 */ 225 #define reg_i2c_status REG_ADDR8(REG_I2C_BASE+0x0d) 226 enum{ 227 FLD_I2C_RBCNT = BIT_RNG(0,2), 228 FLD_I2C_IRQ_O = BIT(3), 229 FLD_I2C_WBCNT = BIT_RNG(4,6), 230 FLD_I2C_RX_CLR = BIT(6), 231 FLD_I2C_TX_CLR = BIT(7), 232 }; 233 234 235 236 /** 237 * This register is used to indicate the interrupt status of i2c. 238 * BIT[0] means Generate an interrupt after the transmission is completed. 239 * BIT[1] If there is data in tx_buffer, an interrupt will be generated. 240 * BIT[2] means Generate an interrupt after the receive is completed. 241 * BIT[3] If there is data in rx_buffer, an interrupt will be generated. 242 * BIT[4] Enable transmission function. 243 */ 244 #define reg_i2c_irq_status REG_ADDR8(REG_I2C_BASE+0x0e) 245 enum{ 246 FLD_I2C_TXDONE = BIT(0), 247 FLD_I2C_TX_BUF_IRQ = BIT(1), 248 FLD_I2C_RXDONE = BIT(2), 249 FLD_I2C_RX_BUF_IRQ = BIT(3), 250 FLD_I2C_TX_EN = BIT(4), 251 }; 252 253 254 //reg_i2c_rx_fifo_len is the number actually entered in the hardware fifo, it is an accumulated value, and fifo clear will clear. 255 #define reg_i2c_rx_fifo_len REG_ADDR8(REG_I2C_BASE+0x0f) 256 enum{ 257 FLD_I2C_RX_FIFO_LEN = BIT_RNG(0,7), 258 }; 259 260 261 262 263 264 #endif 265 266 267 268 269 270 271 272 273 274 275
