1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file dma_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef DMA_REG_H 28 #define DMA_REG_H 29 #include "../sys.h" 30 /******************************* dma registers: 0x100400 ******************************/ 31 #define reg_dma_id REG_ADDR32(0x100400) 32 #define reg_dma_cfg REG_ADDR32(0x100410) 33 //enum{ 34 // FLD_DMA_CHANNEL_NUM = BIT_RNG(0,3), 35 // FLD_DMA_FIFO_DEPTH = BIT_RNG(4,9), 36 // FLD_DMA_REQ_NUM = BIT_RNG(10,14), 37 // FLD_DMA_REQ_SYNC = BIT(30), 38 // FLD_DMA_CHANINXFR = BIT(31), 39 //}; 40 //in C99, FLD_DMA_CHANINXFR = BIT(31) is error 41 #define FLD_DMA_CHANNEL_NUM = BIT_RNG(0,3), 42 #define FLD_DMA_FIFO_DEPTH = BIT_RNG(4,9), 43 #define FLD_DMA_REQ_NUM = BIT_RNG(10,14), 44 #define FLD_DMA_REQ_SYNC = BIT(30), 45 #define FLD_DMA_CHANINXFR = BIT(31), 46 47 #define reg_dma_ctrl(i) REG_ADDR32(( 0x00100444 +(i)*0x14)) 48 49 enum{ 50 FLD_DMA_CHANNEL_ENABLE = BIT(0), 51 FLD_DMA_CHANNEL_TC_MASK = BIT(1), 52 FLD_DMA_CHANNEL_ERR_MASK = BIT(2), 53 FLD_DMA_CHANNEL_ABT_MASK = BIT(3), 54 FLD_DMA_CHANNEL_DST_REQ_SEL = BIT_RNG(4,8), 55 FLD_DMA_CHANNEL_SRC_REQ_SEL = BIT_RNG(9,13), 56 FLD_DMA_CHANNEL_DST_ADDR_CTRL = BIT_RNG(14,15), 57 FLD_DMA_CHANNEL_SRC_ADDR_CTRL = BIT_RNG(16,17), 58 FLD_DMA_CHANNEL_DST_MODE = BIT(18), 59 FLD_DMA_CHANNEL_SRC_MODE = BIT(19), 60 FLD_DMA_CHANNEL_DST_WIDTH = BIT_RNG(20,21), 61 FLD_DMA_CHANNEL_SRC_WIDTH = BIT_RNG(22,23), 62 }; 63 64 #define reg_dma_ctr0(i) REG_ADDR8(( 0x00100444 +(i)*0x14)) 65 66 67 #define reg_dma_err_isr REG_ADDR8(0x100430) 68 #define reg_dma_abt_isr REG_ADDR8(0x100431) 69 #define reg_dma_tc_isr REG_ADDR8(0x100432) 70 71 enum{ 72 FLD_DMA_CHANNEL0_IRQ = BIT(0), 73 FLD_DMA_CHANNEL1_IRQ = BIT(1), 74 FLD_DMA_CHANNEL2_IRQ = BIT(2), 75 FLD_DMA_CHANNEL3_IRQ = BIT(3), 76 FLD_DMA_CHANNEL4_IRQ = BIT(4), 77 FLD_DMA_CHANNEL5_IRQ = BIT(5), 78 FLD_DMA_CHANNEL6_IRQ = BIT(6), 79 FLD_DMA_CHANNEL7_IRQ = BIT(7), 80 }; 81 82 83 84 85 86 #define reg_dma_ctr3(i) REG_ADDR8((0x00100447 +(i)*0x14)) 87 88 enum{ 89 FLD_DMA_SRC_BURST_SIZE = BIT_RNG(0,2), 90 FLD_DMA_R_NUM_EN = BIT(4), 91 FLD_DMA_PRIORITY = BIT(5), 92 FLD_DMA_W_NUM_EN = BIT(6), 93 FLD_DMA_AUTO_ENABLE_EN = BIT(7), 94 }; 95 96 97 98 #define reg_dma_src_addr(i) REG_ADDR32 (( 0x00100448 +(i)*0x14)) 99 #define reg_dma_dst_addr(i) REG_ADDR32 (( 0x0010044c +(i)*0x14)) 100 #define reg_dma_size(i) REG_ADDR32 (( 0x00100450 +(i)*0x14)) 101 102 enum{ 103 FLD_DMA_TX_SIZE = BIT_RNG(0,21), 104 FLD_DMA_TX_SIZE_IDX = BIT_RNG(22,23), 105 }; 106 107 108 109 110 #define reg_dma_cr3_size(i) (*(volatile unsigned long*) ( 0x00100452 +(i)*0x14)) 111 112 enum{ 113 FLD_DMA_TSR2_SIZE_IDX = BIT_RNG(6,7), 114 }; 115 116 #define reg_dma_llp(i) REG_ADDR32 (( 0x00100454 +(i)*0x14)) 117 118 119 #define reg_dma_rx_wptr REG_ADDR8(0x801004f4) 120 #define reg_dma_tx_wptr REG_ADDR8(0x80100500) 121 122 enum{ 123 FLD_DMA_WPTR_MASK = BIT_RNG(0,4), 124 }; 125 126 127 #define reg_dma_rx_rptr REG_ADDR8(0x801004f5) 128 #define reg_dma_tx_rptr REG_ADDR8(0x80100501) 129 enum{ 130 FLD_DMA_RPTR_MASK = BIT_RNG(0,4), 131 FLD_DMA_RPTR_SET = BIT(5), 132 FLD_DMA_RPTR_NEXT = BIT(6), 133 FLD_DMA_RPTR_CLR = BIT(7), 134 }; 135 136 #endif 137
