| /hal_espressif-3.6.0/components/ulp/include/esp32s3/ |
| D | ulp.h | 406 #define I_TSENS(reg_dest, delay) { .tsens = { \ argument
418 #define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ argument
455 #define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ argument
583 #define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
595 #define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
607 #define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
619 #define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
631 #define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ argument
643 #define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ argument
656 #define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ argument
[all …]
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| /hal_espressif-3.6.0/components/ulp/include/esp32s2/ |
| D | ulp.h | 405 #define I_TSENS(reg_dest, delay) { .tsens = { \ argument
417 #define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ argument
455 #define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ argument
583 #define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
595 #define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
607 #define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
619 #define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
631 #define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ argument
643 #define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ argument
656 #define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ argument
[all …]
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| /hal_espressif-3.6.0/components/ulp/include/esp32/ |
| D | ulp.h | 439 #define I_TSENS(reg_dest, delay) { .tsens = { \ argument
451 #define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ argument
489 #define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ argument
617 #define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
629 #define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
641 #define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
653 #define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ argument
665 #define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ argument
677 #define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ argument
690 #define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ argument
[all …]
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