1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	aes_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef _AES_REG_H_
28 #define _AES_REG_H_
29 
30 #include "../sys.h"
31 
32 
33 #define reg_aes_mode     			REG_ADDR32(0x1600b0)
34 enum{
35 	FLD_AES_START	=	BIT(0),
36 	FLD_AES_MODE	=	BIT(1),   /**< 0-ciher  1-deciher */
37 };
38 
39 #define reg_embase_addr     		REG_ADDR32(0x140b04)
40 
41 #define	reg_aes_irq_mask			REG_ADDR32(0x16000c)
42 
43 #define reg_aes_irq_status			REG_ADDR32(0x160010)
44 
45 #define reg_aes_clr_irq_status		REG_ADDR32(0x160018)
46 /**
47  *  @brief  Define AES IRQ
48  */
49 typedef enum{
50 	FLD_CRYPT_IRQ		= BIT(7),
51 }aes_irq_e;
52 
53 
54 #define reg_aes_key(v)     			REG_ADDR32(0x1600b4+(v*4))
55 
56 #define reg_aes_ptr     			REG_ADDR32(0x1600c4)
57 
58 #endif /* _AES_REG_H_ */
59