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Searched defs:regAddr (Results 1 – 25 of 101) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/include/
DRegLockMacros.h303 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
391 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
401 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
411 #define REG_SET_SOFT_LOCK32(baseAddr, regAddr, prot_mem) \ argument
434 #define REG_CLR_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
444 #define REG_CLR_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
454 #define REG_CLR_SOFT_LOCK32(baseAddr, regAddr, prot_mem) \ argument
475 …#define REG_GET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) … argument
485 …#define REG_GET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) … argument
495 …#define REG_GET_SOFT_LOCK32(baseAddr, regAddr, prot_mem) … argument
[all …]
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/include/
DRegLockMacros.h303 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
391 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
401 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
411 #define REG_SET_SOFT_LOCK32(baseAddr, regAddr, prot_mem) \ argument
434 #define REG_CLR_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
444 #define REG_CLR_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
454 #define REG_CLR_SOFT_LOCK32(baseAddr, regAddr, prot_mem) \ argument
475 …#define REG_GET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) … argument
485 …#define REG_GET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) … argument
495 …#define REG_GET_SOFT_LOCK32(baseAddr, regAddr, prot_mem) … argument
[all …]
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/include/
DRegLockMacros.h302 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
390 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
400 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
410 #define REG_SET_SOFT_LOCK32(baseAddr, regAddr, prot_mem) \ argument
433 #define REG_CLR_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
443 #define REG_CLR_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
453 #define REG_CLR_SOFT_LOCK32(baseAddr, regAddr, prot_mem) \ argument
474 …#define REG_GET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) … argument
484 …#define REG_GET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) … argument
494 …#define REG_GET_SOFT_LOCK32(baseAddr, regAddr, prot_mem) … argument
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/netc/
Dfsl_netc_mdio.c96 static status_t NETC_PEMDIO_Write(netc_mdio_hw_t *base, uint8_t phyAddr, uint8_t regAddr, uint16_t … in NETC_PEMDIO_Write()
116 static status_t NETC_PEMDIO_Read(netc_mdio_hw_t *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *… in NETC_PEMDIO_Read()
138 netc_mdio_hw_t *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data) in NETC_PEMDIO_C45Write()
162 netc_mdio_hw_t *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData) in NETC_PEMDIO_C45Read()
233 static void NETC_PIMDIO_Write(NETC_ETH_LINK_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t … in NETC_PIMDIO_Write()
243 static void NETC_PIMDIO_Read(NETC_ETH_LINK_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *… in NETC_PIMDIO_Read()
258 NETC_ETH_LINK_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data) in NETC_PIMDIO_C45Write()
276 NETC_ETH_LINK_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData) in NETC_PIMDIO_C45Read()
363 status_t NETC_MDIOWrite(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in NETC_MDIOWrite()
381 status_t NETC_MDIORead(netc_mdio_handle_t *handle, uint8_t phyAddr, uint8_t regAddr, uint16_t *pDat… in NETC_MDIORead()
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Dfsl_netc_phy_wrapper.c14 uint16_t regAddr = getPhyReg(reg); in NETC_PHYWriteRegBits() local
38 uint16_t regAddr = getPhyReg(reg); in NETC_PHYReadReg() local
/hal_nxp-latest/mcux/mcux-sdk/components/pca9422/
Dfsl_pca9422.c1217 uint8_t regVal, regAddr; in PCA9422_InitRegulator() local
1704 uint8_t regVal, regAddr; in PCA9422_GetRegulatorEnMode() local
1807 uint8_t regVal, regAddr, regMask; in PCA9422_SetRegulatorEnMode() local
1878 uint8_t regVal, regAddr; in PCA9422_GetRegulatorLPMode() local
2005 uint8_t regVal, regAddr, regMask; in PCA9422_SetRegulatorLPMode() local
2105 uint8_t regVal, regAddr, regMask; in PCA9422_SetRegulatorVoltage() local
2405 uint8_t regVal, regAddr, regMask = 0U; in PCA9422_GetRegulatorVoltage() local
2902 uint8_t regVal, regAddr, regMask; in PCA9422_SetBuckDVSControl() local
2939 uint8_t regVal, regAddr, regMask; in PCA9422_SetEnableRegulatorRunState() local
3002 uint8_t regVal, regAddr, regMask; in PCA9422_GetEnableRegulatorRunState() local
/hal_nxp-latest/mcux/mcux-sdk/drivers/enet_qos/
Dfsl_enet_qos.c209 static status_t ENET_QOS_PollStatusFlag(volatile uint32_t *regAddr, uint32_t mask, uint32_t readySt… in ENET_QOS_PollStatusFlag()
1832 void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_QOS_StartSMIWrite()
1852 void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr) in ENET_QOS_StartSMIRead()
1874 ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data) in ENET_QOS_StartExtC45SMIWrite()
1895 …ET_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr) in ENET_QOS_StartExtC45SMIRead()
1944 status_t ENET_QOS_MDIOWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_QOS_MDIOWrite()
1961 status_t ENET_QOS_MDIORead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData) in ENET_QOS_MDIORead()
1990 …DIOC45Write(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t dat… in ENET_QOS_MDIOC45Write()
2008 …MDIOC45Read(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pD… in ENET_QOS_MDIOC45Read()
/hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_enet/
Dfsl_enet.c1016 void ENET_StartSMIWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_StartSMIWrite()
1035 void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr) in ENET_StartSMIRead()
1083 status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_MDIOWrite()
1100 status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData) in ENET_MDIORead()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_enet/
Dfsl_enet.c1015 void ENET_StartSMIWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_StartSMIWrite()
1034 void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr) in ENET_StartSMIRead()
1082 status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_MDIOWrite()
1099 status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData) in ENET_MDIORead()
/hal_nxp-latest/mcux/mcux-sdk/components/pf5020/
Dfsl_pf5020.c279 status_t PF5020_WriteReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t val) in PF5020_WriteReg()
298 status_t PF5020_ReadReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t *val) in PF5020_ReadReg()
318 status_t PF5020_ModifyReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t mask, uint8_t val) in PF5020_ModifyReg()
349 status_t PF5020_DumpReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t *buffer, uint8_t length) in PF5020_DumpReg()
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8041/
Dfsl_phyksz8041.c32 #define PHY_KSZ8041_WRITE(handle, regAddr, data) \ argument
34 #define PHY_KSZ8041_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8720a/
Dfsl_phylan8720a.c38 #define PHY_LAN8720A_WRITE(handle, regAddr, data) \ argument
40 #define PHY_LAN8720A_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/drivers/enet/
Dfsl_enet.c1264 status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data) in ENET_MDIOWrite()
1296 status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData) in ENET_MDIORead()
1335 status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, ui… in ENET_MDIOC45Write()
1371 status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uin… in ENET_MDIOC45Read()
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyvsc8541/
Dfsl_phyvsc8541.c37 #define PHY_VSC8541_WRITE(handle, regAddr, data) \ argument
39 #define PHY_VSC8541_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8741/
Dfsl_phylan8741.c39 #define PHY_LAN8741_WRITE(handle, regAddr, data) \ argument
41 #define PHY_LAN8741_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyrtl8201/
Dfsl_phyrtl8201.c30 #define PHY_RTL8201_WRITE(handle, regAddr, data) \ argument
32 #define PHY_RTL8201_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8081/
Dfsl_phyksz8081.c42 #define PHY_KSZ8081_WRITE(handle, regAddr, data) \ argument
44 #define PHY_KSZ8081_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyrtl8211f/
Dfsl_phyrtl8211f.c62 #define PHY_RTL8211F_WRITE(handle, regAddr, data) \ argument
64 #define PHY_RTL8211F_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyar8031/
Dfsl_phyar8031.c71 #define PHY_AR8031_WRITE(handle, regAddr, data) \ argument
73 #define PHY_AR8031_READ(handle, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt685audevk/
Dboard.c57 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_write_mcr()
76 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_get_mcr()
/hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyaqr113c/
Dfsl_phyaqr113c.c119 #define PHY_AQR113C_WRITE(handle, devAddr, regAddr, data) \ argument
121 #define PHY_AQR113C_READ(handle, devAddr, regAddr, pData) \ argument
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.c313 static void xspi_hyper_ram_get_mcr(XSPI_Type *base, uint32_t regAddr, uint8_t *mrVal) in xspi_hyper_ram_get_mcr()
336 static void xspi_hyper_ram_write_mcr(XSPI_Type *base, uint32_t regAddr, uint8_t *mrVal) in xspi_hyper_ram_write_mcr()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt685/
Dboard.c64 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_write_mcr()
83 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal) in flexspi_hyper_ram_get_mcr()
/hal_nxp-latest/mcux/mcux-sdk/drivers/trdc_1/
Dfsl_trdc.c689 …uint32_t regAddr = (uint32_t) & (TRDC_MRC_BASE(base, config->mrcIdx)->MRC_DOM0_RGD_W[config->regio… in TRDC_MrcSetRegionDescriptorConfig() local
842 …uint32_t regAddr = (uint32_t) & (TRDC_MBC_BASE(base, config->mbcIdx)->MBC_DOM0_MEM0_BLK_CFG_W[0… in TRDC_MbcSetMemoryBlockConfig() local
/hal_nxp-latest/mcux/mcux-sdk/drivers/trdc/
Dfsl_trdc.c682 …uint32_t regAddr = (uint32_t) & (base->MRC_INDEX[config->mrcIdx].MRC_DOM0_RGD_W[config->regionIdx]… in TRDC_MrcSetRegionDescriptorConfig() local
828 …uint32_t regAddr = (uint32_t) & (base->MBC_INDEX[config->mbcIdx].MBC_DOM0_MEM0_BLK_CFG_W[0]… in TRDC_MbcSetMemoryBlockConfig() local

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